phy-samsung-ufs.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * UFS PHY driver for Samsung SoC
  4. *
  5. * Copyright (C) 2020 Samsung Electronics Co., Ltd.
  6. * Author: Seungwon Jeon <essuuj@gmail.com>
  7. * Author: Alim Akhtar <alim.akhtar@samsung.com>
  8. *
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/err.h>
  13. #include <linux/of.h>
  14. #include <linux/io.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/module.h>
  18. #include <linux/phy/phy.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include "phy-samsung-ufs.h"
  22. #define for_each_phy_lane(phy, i) \
  23. for (i = 0; i < (phy)->lane_cnt; i++)
  24. #define for_each_phy_cfg(cfg) \
  25. for (; (cfg)->id; (cfg)++)
  26. #define PHY_DEF_LANE_CNT 1
  27. static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
  28. const struct samsung_ufs_phy_cfg *cfg,
  29. u8 lane)
  30. {
  31. enum {LANE_0, LANE_1}; /* lane index */
  32. switch (lane) {
  33. case LANE_0:
  34. writel(cfg->val, (phy)->reg_pma + cfg->off_0);
  35. break;
  36. case LANE_1:
  37. if (cfg->id == PHY_TRSV_BLK)
  38. writel(cfg->val, (phy)->reg_pma + cfg->off_1);
  39. break;
  40. }
  41. }
  42. static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
  43. {
  44. struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
  45. const unsigned int timeout_us = 100000;
  46. const unsigned int sleep_us = 10;
  47. u32 val;
  48. int err;
  49. err = readl_poll_timeout(
  50. ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
  51. val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
  52. if (err) {
  53. dev_err(ufs_phy->dev,
  54. "failed to get phy pll lock acquisition %d\n", err);
  55. goto out;
  56. }
  57. err = readl_poll_timeout(
  58. ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
  59. val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
  60. if (err)
  61. dev_err(ufs_phy->dev,
  62. "failed to get phy cdr lock acquisition %d\n", err);
  63. out:
  64. return err;
  65. }
  66. static int samsung_ufs_phy_calibrate(struct phy *phy)
  67. {
  68. struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
  69. struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
  70. const struct samsung_ufs_phy_cfg *cfg;
  71. int err = 0;
  72. int i;
  73. if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
  74. ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
  75. dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
  76. return -EINVAL;
  77. }
  78. cfg = cfgs[ufs_phy->ufs_phy_state];
  79. if (!cfg)
  80. goto out;
  81. for_each_phy_cfg(cfg) {
  82. for_each_phy_lane(ufs_phy, i) {
  83. samsung_ufs_phy_config(ufs_phy, cfg, i);
  84. }
  85. }
  86. if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
  87. err = samsung_ufs_phy_wait_for_lock_acq(phy);
  88. /**
  89. * In Samsung ufshci, PHY need to be calibrated at different
  90. * stages / state mainly before Linkstartup, after Linkstartup,
  91. * before power mode change and after power mode change.
  92. * Below state machine to make sure to calibrate PHY in each
  93. * state. Here after configuring PHY in a given state, will
  94. * change the state to next state so that next state phy
  95. * calibration value can be programed
  96. */
  97. out:
  98. switch (ufs_phy->ufs_phy_state) {
  99. case CFG_PRE_INIT:
  100. ufs_phy->ufs_phy_state = CFG_POST_INIT;
  101. break;
  102. case CFG_POST_INIT:
  103. ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
  104. break;
  105. case CFG_PRE_PWR_HS:
  106. ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
  107. break;
  108. case CFG_POST_PWR_HS:
  109. /* Change back to INIT state */
  110. ufs_phy->ufs_phy_state = CFG_PRE_INIT;
  111. break;
  112. default:
  113. dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
  114. }
  115. return err;
  116. }
  117. static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
  118. {
  119. int ret;
  120. phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
  121. if (IS_ERR(phy->tx0_symbol_clk)) {
  122. dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
  123. return PTR_ERR(phy->tx0_symbol_clk);
  124. }
  125. phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
  126. if (IS_ERR(phy->rx0_symbol_clk)) {
  127. dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
  128. return PTR_ERR(phy->rx0_symbol_clk);
  129. }
  130. phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
  131. if (IS_ERR(phy->rx1_symbol_clk)) {
  132. dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
  133. return PTR_ERR(phy->rx1_symbol_clk);
  134. }
  135. ret = clk_prepare_enable(phy->tx0_symbol_clk);
  136. if (ret) {
  137. dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", __func__, ret);
  138. goto out;
  139. }
  140. ret = clk_prepare_enable(phy->rx0_symbol_clk);
  141. if (ret) {
  142. dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", __func__, ret);
  143. goto out_disable_tx0_clk;
  144. }
  145. ret = clk_prepare_enable(phy->rx1_symbol_clk);
  146. if (ret) {
  147. dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", __func__, ret);
  148. goto out_disable_rx0_clk;
  149. }
  150. return 0;
  151. out_disable_rx0_clk:
  152. clk_disable_unprepare(phy->rx0_symbol_clk);
  153. out_disable_tx0_clk:
  154. clk_disable_unprepare(phy->tx0_symbol_clk);
  155. out:
  156. return ret;
  157. }
  158. static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
  159. {
  160. int ret;
  161. phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
  162. if (IS_ERR(phy->ref_clk))
  163. dev_err(phy->dev, "failed to get ref_clk clock\n");
  164. ret = clk_prepare_enable(phy->ref_clk);
  165. if (ret) {
  166. dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, ret);
  167. return ret;
  168. }
  169. dev_dbg(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", clk_get_rate(phy->ref_clk));
  170. return 0;
  171. }
  172. static int samsung_ufs_phy_init(struct phy *phy)
  173. {
  174. struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
  175. int ret;
  176. ss_phy->lane_cnt = phy->attrs.bus_width;
  177. ss_phy->ufs_phy_state = CFG_PRE_INIT;
  178. if (ss_phy->drvdata->has_symbol_clk) {
  179. ret = samsung_ufs_phy_symbol_clk_init(ss_phy);
  180. if (ret)
  181. dev_err(ss_phy->dev, "failed to set ufs phy symbol clocks\n");
  182. }
  183. ret = samsung_ufs_phy_clks_init(ss_phy);
  184. if (ret)
  185. dev_err(ss_phy->dev, "failed to set ufs phy clocks\n");
  186. ret = samsung_ufs_phy_calibrate(phy);
  187. if (ret)
  188. dev_err(ss_phy->dev, "ufs phy calibration failed\n");
  189. return ret;
  190. }
  191. static int samsung_ufs_phy_power_on(struct phy *phy)
  192. {
  193. struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
  194. samsung_ufs_phy_ctrl_isol(ss_phy, false);
  195. return 0;
  196. }
  197. static int samsung_ufs_phy_power_off(struct phy *phy)
  198. {
  199. struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
  200. samsung_ufs_phy_ctrl_isol(ss_phy, true);
  201. return 0;
  202. }
  203. static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
  204. enum phy_mode mode, int submode)
  205. {
  206. struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(generic_phy);
  207. ss_phy->mode = PHY_MODE_INVALID;
  208. if (mode > 0)
  209. ss_phy->mode = mode;
  210. return 0;
  211. }
  212. static int samsung_ufs_phy_exit(struct phy *phy)
  213. {
  214. struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
  215. clk_disable_unprepare(ss_phy->ref_clk);
  216. if (ss_phy->drvdata->has_symbol_clk) {
  217. clk_disable_unprepare(ss_phy->tx0_symbol_clk);
  218. clk_disable_unprepare(ss_phy->rx0_symbol_clk);
  219. clk_disable_unprepare(ss_phy->rx1_symbol_clk);
  220. }
  221. return 0;
  222. }
  223. static const struct phy_ops samsung_ufs_phy_ops = {
  224. .init = samsung_ufs_phy_init,
  225. .exit = samsung_ufs_phy_exit,
  226. .power_on = samsung_ufs_phy_power_on,
  227. .power_off = samsung_ufs_phy_power_off,
  228. .calibrate = samsung_ufs_phy_calibrate,
  229. .set_mode = samsung_ufs_phy_set_mode,
  230. .owner = THIS_MODULE,
  231. };
  232. static const struct of_device_id samsung_ufs_phy_match[];
  233. static int samsung_ufs_phy_probe(struct platform_device *pdev)
  234. {
  235. struct device *dev = &pdev->dev;
  236. const struct of_device_id *match;
  237. struct samsung_ufs_phy *phy;
  238. struct phy *gen_phy;
  239. struct phy_provider *phy_provider;
  240. const struct samsung_ufs_phy_drvdata *drvdata;
  241. int err = 0;
  242. match = of_match_node(samsung_ufs_phy_match, dev->of_node);
  243. if (!match) {
  244. err = -EINVAL;
  245. dev_err(dev, "failed to get match_node\n");
  246. goto out;
  247. }
  248. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  249. if (!phy) {
  250. err = -ENOMEM;
  251. goto out;
  252. }
  253. phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
  254. if (IS_ERR(phy->reg_pma)) {
  255. err = PTR_ERR(phy->reg_pma);
  256. goto out;
  257. }
  258. phy->reg_pmu = syscon_regmap_lookup_by_phandle(
  259. dev->of_node, "samsung,pmu-syscon");
  260. if (IS_ERR(phy->reg_pmu)) {
  261. err = PTR_ERR(phy->reg_pmu);
  262. dev_err(dev, "failed syscon remap for pmu\n");
  263. goto out;
  264. }
  265. gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
  266. if (IS_ERR(gen_phy)) {
  267. err = PTR_ERR(gen_phy);
  268. dev_err(dev, "failed to create PHY for ufs-phy\n");
  269. goto out;
  270. }
  271. drvdata = match->data;
  272. phy->dev = dev;
  273. phy->drvdata = drvdata;
  274. phy->cfg = (struct samsung_ufs_phy_cfg **)drvdata->cfg;
  275. phy->isol = &drvdata->isol;
  276. phy->lane_cnt = PHY_DEF_LANE_CNT;
  277. phy_set_drvdata(gen_phy, phy);
  278. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  279. if (IS_ERR(phy_provider)) {
  280. err = PTR_ERR(phy_provider);
  281. dev_err(dev, "failed to register phy-provider\n");
  282. goto out;
  283. }
  284. out:
  285. return err;
  286. }
  287. static const struct of_device_id samsung_ufs_phy_match[] = {
  288. {
  289. .compatible = "samsung,exynos7-ufs-phy",
  290. .data = &exynos7_ufs_phy,
  291. },
  292. {},
  293. };
  294. MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
  295. static struct platform_driver samsung_ufs_phy_driver = {
  296. .probe = samsung_ufs_phy_probe,
  297. .driver = {
  298. .name = "samsung-ufs-phy",
  299. .of_match_table = samsung_ufs_phy_match,
  300. },
  301. };
  302. module_platform_driver(samsung_ufs_phy_driver);
  303. MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
  304. MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
  305. MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
  306. MODULE_LICENSE("GPL v2");