phy-s5pv210-usb2.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. * Authors: Kamil Debski <k.debski@samsung.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/phy/phy.h>
  11. #include "phy-samsung-usb2.h"
  12. /* Exynos USB PHY registers */
  13. /* PHY power control */
  14. #define S5PV210_UPHYPWR 0x0
  15. #define S5PV210_UPHYPWR_PHY0_SUSPEND BIT(0)
  16. #define S5PV210_UPHYPWR_PHY0_PWR BIT(3)
  17. #define S5PV210_UPHYPWR_PHY0_OTG_PWR BIT(4)
  18. #define S5PV210_UPHYPWR_PHY0 ( \
  19. S5PV210_UPHYPWR_PHY0_SUSPEND | \
  20. S5PV210_UPHYPWR_PHY0_PWR | \
  21. S5PV210_UPHYPWR_PHY0_OTG_PWR)
  22. #define S5PV210_UPHYPWR_PHY1_SUSPEND BIT(6)
  23. #define S5PV210_UPHYPWR_PHY1_PWR BIT(7)
  24. #define S5PV210_UPHYPWR_PHY1 ( \
  25. S5PV210_UPHYPWR_PHY1_SUSPEND | \
  26. S5PV210_UPHYPWR_PHY1_PWR)
  27. /* PHY clock control */
  28. #define S5PV210_UPHYCLK 0x4
  29. #define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
  30. #define S5PV210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
  31. #define S5PV210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
  32. #define S5PV210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
  33. #define S5PV210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
  34. #define S5PV210_UPHYCLK_PHY0_COMMON_ON BIT(4)
  35. #define S5PV210_UPHYCLK_PHY1_COMMON_ON BIT(7)
  36. /* PHY reset control */
  37. #define S5PV210_UPHYRST 0x8
  38. #define S5PV210_URSTCON_PHY0 BIT(0)
  39. #define S5PV210_URSTCON_OTG_HLINK BIT(1)
  40. #define S5PV210_URSTCON_OTG_PHYLINK BIT(2)
  41. #define S5PV210_URSTCON_PHY1_ALL BIT(3)
  42. #define S5PV210_URSTCON_HOST_LINK_ALL BIT(4)
  43. /* Isolation, configured in the power management unit */
  44. #define S5PV210_USB_ISOL_OFFSET 0x680c
  45. #define S5PV210_USB_ISOL_DEVICE BIT(0)
  46. #define S5PV210_USB_ISOL_HOST BIT(1)
  47. enum s5pv210_phy_id {
  48. S5PV210_DEVICE,
  49. S5PV210_HOST,
  50. S5PV210_NUM_PHYS,
  51. };
  52. /*
  53. * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
  54. * can be written to the phy register.
  55. */
  56. static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
  57. {
  58. switch (rate) {
  59. case 12 * MHZ:
  60. *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
  61. break;
  62. case 24 * MHZ:
  63. *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
  64. break;
  65. case 48 * MHZ:
  66. *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
  67. break;
  68. default:
  69. return -EINVAL;
  70. }
  71. return 0;
  72. }
  73. static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
  74. {
  75. struct samsung_usb2_phy_driver *drv = inst->drv;
  76. u32 mask;
  77. switch (inst->cfg->id) {
  78. case S5PV210_DEVICE:
  79. mask = S5PV210_USB_ISOL_DEVICE;
  80. break;
  81. case S5PV210_HOST:
  82. mask = S5PV210_USB_ISOL_HOST;
  83. break;
  84. default:
  85. return;
  86. }
  87. regmap_update_bits(drv->reg_pmu, S5PV210_USB_ISOL_OFFSET,
  88. mask, on ? 0 : mask);
  89. }
  90. static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
  91. {
  92. struct samsung_usb2_phy_driver *drv = inst->drv;
  93. u32 rstbits = 0;
  94. u32 phypwr = 0;
  95. u32 rst;
  96. u32 pwr;
  97. switch (inst->cfg->id) {
  98. case S5PV210_DEVICE:
  99. phypwr = S5PV210_UPHYPWR_PHY0;
  100. rstbits = S5PV210_URSTCON_PHY0;
  101. break;
  102. case S5PV210_HOST:
  103. phypwr = S5PV210_UPHYPWR_PHY1;
  104. rstbits = S5PV210_URSTCON_PHY1_ALL |
  105. S5PV210_URSTCON_HOST_LINK_ALL;
  106. break;
  107. }
  108. if (on) {
  109. writel(drv->ref_reg_val, drv->reg_phy + S5PV210_UPHYCLK);
  110. pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
  111. pwr &= ~phypwr;
  112. writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
  113. rst = readl(drv->reg_phy + S5PV210_UPHYRST);
  114. rst |= rstbits;
  115. writel(rst, drv->reg_phy + S5PV210_UPHYRST);
  116. udelay(10);
  117. rst &= ~rstbits;
  118. writel(rst, drv->reg_phy + S5PV210_UPHYRST);
  119. /* The following delay is necessary for the reset sequence to be
  120. * completed
  121. */
  122. udelay(80);
  123. } else {
  124. pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
  125. pwr |= phypwr;
  126. writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
  127. }
  128. }
  129. static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
  130. {
  131. s5pv210_isol(inst, 0);
  132. s5pv210_phy_pwr(inst, 1);
  133. return 0;
  134. }
  135. static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
  136. {
  137. s5pv210_phy_pwr(inst, 0);
  138. s5pv210_isol(inst, 1);
  139. return 0;
  140. }
  141. static const struct samsung_usb2_common_phy s5pv210_phys[S5PV210_NUM_PHYS] = {
  142. [S5PV210_DEVICE] = {
  143. .label = "device",
  144. .id = S5PV210_DEVICE,
  145. .power_on = s5pv210_power_on,
  146. .power_off = s5pv210_power_off,
  147. },
  148. [S5PV210_HOST] = {
  149. .label = "host",
  150. .id = S5PV210_HOST,
  151. .power_on = s5pv210_power_on,
  152. .power_off = s5pv210_power_off,
  153. },
  154. };
  155. const struct samsung_usb2_phy_config s5pv210_usb2_phy_config = {
  156. .num_phys = ARRAY_SIZE(s5pv210_phys),
  157. .phys = s5pv210_phys,
  158. .rate_to_clk = s5pv210_rate_to_clk,
  159. };