phy-exynos5250-usb2.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. * Author: Kamil Debski <k.debski@samsung.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/phy/phy.h>
  11. #include <linux/regmap.h>
  12. #include "phy-samsung-usb2.h"
  13. /* Exynos USB PHY registers */
  14. #define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0
  15. #define EXYNOS_5250_REFCLKSEL_XO 0x1
  16. #define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2
  17. #define EXYNOS_5250_FSEL_9MHZ6 0x0
  18. #define EXYNOS_5250_FSEL_10MHZ 0x1
  19. #define EXYNOS_5250_FSEL_12MHZ 0x2
  20. #define EXYNOS_5250_FSEL_19MHZ2 0x3
  21. #define EXYNOS_5250_FSEL_20MHZ 0x4
  22. #define EXYNOS_5250_FSEL_24MHZ 0x5
  23. #define EXYNOS_5250_FSEL_50MHZ 0x7
  24. /* Normal host */
  25. #define EXYNOS_5250_HOSTPHYCTRL0 0x0
  26. #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31)
  27. #define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19
  28. #define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK \
  29. (0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT)
  30. #define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT 16
  31. #define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \
  32. (0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT)
  33. #define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN BIT(11)
  34. #define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10)
  35. #define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9)
  36. #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK (0x3 << 7)
  37. #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL (0x0 << 7)
  38. #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 << 7)
  39. #define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST (0x2 << 7)
  40. #define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ BIT(6)
  41. #define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP BIT(5)
  42. #define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND BIT(4)
  43. #define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE BIT(3)
  44. #define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST BIT(2)
  45. #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
  46. #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST BIT(0)
  47. /* HSIC0 & HSIC1 */
  48. #define EXYNOS_5250_HSICPHYCTRL1 0x10
  49. #define EXYNOS_5250_HSICPHYCTRL2 0x20
  50. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_MASK (0x3 << 23)
  51. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT (0x2 << 23)
  52. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_MASK (0x7f << 16)
  53. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 (0x24 << 16)
  54. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_15 (0x1c << 16)
  55. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_16 (0x1a << 16)
  56. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_19_2 (0x15 << 16)
  57. #define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_20 (0x14 << 16)
  58. #define EXYNOS_5250_HSICPHYCTRLX_SIDDQ BIT(6)
  59. #define EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP BIT(5)
  60. #define EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND BIT(4)
  61. #define EXYNOS_5250_HSICPHYCTRLX_WORDINTERFACE BIT(3)
  62. #define EXYNOS_5250_HSICPHYCTRLX_UTMISWRST BIT(2)
  63. #define EXYNOS_5250_HSICPHYCTRLX_PHYSWRST BIT(0)
  64. /* EHCI control */
  65. #define EXYNOS_5250_HOSTEHCICTRL 0x30
  66. #define EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN BIT(29)
  67. #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 BIT(28)
  68. #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 BIT(27)
  69. #define EXYNOS_5250_HOSTEHCICTRL_ENAINCR16 BIT(26)
  70. #define EXYNOS_5250_HOSTEHCICTRL_AUTOPPDONOVRCUREN BIT(25)
  71. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT 19
  72. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK \
  73. (0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
  74. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT 13
  75. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_MASK \
  76. (0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT)
  77. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL2_SHIFT 7
  78. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK \
  79. (0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
  80. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT 1
  81. #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_MASK \
  82. (0x1 << EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT)
  83. #define EXYNOS_5250_HOSTEHCICTRL_SIMULATIONMODE BIT(0)
  84. /* OHCI control */
  85. #define EXYNOS_5250_HOSTOHCICTRL 0x34
  86. #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT 1
  87. #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_MASK \
  88. (0x3ff << EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT)
  89. #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVALEN BIT(0)
  90. /* USBOTG */
  91. #define EXYNOS_5250_USBOTGSYS 0x38
  92. #define EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET BIT(14)
  93. #define EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG BIT(13)
  94. #define EXYNOS_5250_USBOTGSYS_PHY_SW_RST BIT(12)
  95. #define EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT 9
  96. #define EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK \
  97. (0x3 << EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT)
  98. #define EXYNOS_5250_USBOTGSYS_ID_PULLUP BIT(8)
  99. #define EXYNOS_5250_USBOTGSYS_COMMON_ON BIT(7)
  100. #define EXYNOS_5250_USBOTGSYS_FSEL_SHIFT 4
  101. #define EXYNOS_5250_USBOTGSYS_FSEL_MASK \
  102. (0x3 << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT)
  103. #define EXYNOS_5250_USBOTGSYS_FORCE_SLEEP BIT(3)
  104. #define EXYNOS_5250_USBOTGSYS_OTGDISABLE BIT(2)
  105. #define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1)
  106. #define EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND BIT(0)
  107. /* Isolation, configured in the power management unit */
  108. #define EXYNOS_5250_USB_ISOL_OTG_OFFSET 0x704
  109. #define EXYNOS_5250_USB_ISOL_OTG BIT(0)
  110. #define EXYNOS_5250_USB_ISOL_HOST_OFFSET 0x708
  111. #define EXYNOS_5250_USB_ISOL_HOST BIT(0)
  112. /* Mode swtich register */
  113. #define EXYNOS_5250_MODE_SWITCH_OFFSET 0x230
  114. #define EXYNOS_5250_MODE_SWITCH_MASK 1
  115. #define EXYNOS_5250_MODE_SWITCH_DEVICE 0
  116. #define EXYNOS_5250_MODE_SWITCH_HOST 1
  117. enum exynos4x12_phy_id {
  118. EXYNOS5250_DEVICE,
  119. EXYNOS5250_HOST,
  120. EXYNOS5250_HSIC0,
  121. EXYNOS5250_HSIC1,
  122. EXYNOS5250_NUM_PHYS,
  123. };
  124. /*
  125. * exynos5250_rate_to_clk() converts the supplied clock rate to the value that
  126. * can be written to the phy register.
  127. */
  128. static int exynos5250_rate_to_clk(unsigned long rate, u32 *reg)
  129. {
  130. /* EXYNOS_5250_FSEL_MASK */
  131. switch (rate) {
  132. case 9600 * KHZ:
  133. *reg = EXYNOS_5250_FSEL_9MHZ6;
  134. break;
  135. case 10 * MHZ:
  136. *reg = EXYNOS_5250_FSEL_10MHZ;
  137. break;
  138. case 12 * MHZ:
  139. *reg = EXYNOS_5250_FSEL_12MHZ;
  140. break;
  141. case 19200 * KHZ:
  142. *reg = EXYNOS_5250_FSEL_19MHZ2;
  143. break;
  144. case 20 * MHZ:
  145. *reg = EXYNOS_5250_FSEL_20MHZ;
  146. break;
  147. case 24 * MHZ:
  148. *reg = EXYNOS_5250_FSEL_24MHZ;
  149. break;
  150. case 50 * MHZ:
  151. *reg = EXYNOS_5250_FSEL_50MHZ;
  152. break;
  153. default:
  154. return -EINVAL;
  155. }
  156. return 0;
  157. }
  158. static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on)
  159. {
  160. struct samsung_usb2_phy_driver *drv = inst->drv;
  161. u32 offset;
  162. u32 mask;
  163. switch (inst->cfg->id) {
  164. case EXYNOS5250_DEVICE:
  165. offset = EXYNOS_5250_USB_ISOL_OTG_OFFSET;
  166. mask = EXYNOS_5250_USB_ISOL_OTG;
  167. break;
  168. case EXYNOS5250_HOST:
  169. offset = EXYNOS_5250_USB_ISOL_HOST_OFFSET;
  170. mask = EXYNOS_5250_USB_ISOL_HOST;
  171. break;
  172. default:
  173. return;
  174. }
  175. regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
  176. }
  177. static int exynos5250_power_on(struct samsung_usb2_phy_instance *inst)
  178. {
  179. struct samsung_usb2_phy_driver *drv = inst->drv;
  180. u32 ctrl0;
  181. u32 otg;
  182. u32 ehci;
  183. u32 ohci;
  184. u32 hsic;
  185. switch (inst->cfg->id) {
  186. case EXYNOS5250_DEVICE:
  187. regmap_update_bits(drv->reg_sys,
  188. EXYNOS_5250_MODE_SWITCH_OFFSET,
  189. EXYNOS_5250_MODE_SWITCH_MASK,
  190. EXYNOS_5250_MODE_SWITCH_DEVICE);
  191. /* OTG configuration */
  192. otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  193. /* The clock */
  194. otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
  195. otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
  196. /* Reset */
  197. otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
  198. EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
  199. EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
  200. otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
  201. EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
  202. EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
  203. EXYNOS_5250_USBOTGSYS_OTGDISABLE;
  204. /* Ref clock */
  205. otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
  206. otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
  207. EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
  208. writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  209. udelay(100);
  210. otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
  211. EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
  212. EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
  213. EXYNOS_5250_USBOTGSYS_OTGDISABLE);
  214. writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  215. break;
  216. case EXYNOS5250_HOST:
  217. case EXYNOS5250_HSIC0:
  218. case EXYNOS5250_HSIC1:
  219. /* Host registers configuration */
  220. ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
  221. /* The clock */
  222. ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK;
  223. ctrl0 |= drv->ref_reg_val <<
  224. EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT;
  225. /* Reset */
  226. ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
  227. EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL |
  228. EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
  229. EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
  230. EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP);
  231. ctrl0 |= EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
  232. EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST |
  233. EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N;
  234. writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
  235. udelay(10);
  236. ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST |
  237. EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST);
  238. writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
  239. /* OTG configuration */
  240. otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  241. /* The clock */
  242. otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
  243. otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
  244. /* Reset */
  245. otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
  246. EXYNOS_5250_USBOTGSYS_FORCE_SLEEP |
  247. EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG);
  248. otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
  249. EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET |
  250. EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
  251. EXYNOS_5250_USBOTGSYS_OTGDISABLE;
  252. /* Ref clock */
  253. otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
  254. otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
  255. EXYNOS_5250_USBOTGSYS_REFCLKSEL_SHIFT;
  256. writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  257. udelay(10);
  258. otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
  259. EXYNOS_5250_USBOTGSYS_LINK_SW_RST_UOTG |
  260. EXYNOS_5250_USBOTGSYS_PHYLINK_SW_RESET);
  261. /* HSIC phy configuration */
  262. hsic = (EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 |
  263. EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT |
  264. EXYNOS_5250_HSICPHYCTRLX_PHYSWRST);
  265. writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
  266. writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
  267. udelay(10);
  268. hsic &= ~EXYNOS_5250_HSICPHYCTRLX_PHYSWRST;
  269. writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
  270. writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
  271. /* The following delay is necessary for the reset sequence to be
  272. * completed */
  273. udelay(80);
  274. /* Enable EHCI DMA burst */
  275. ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
  276. ehci |= EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN |
  277. EXYNOS_5250_HOSTEHCICTRL_ENAINCR4 |
  278. EXYNOS_5250_HOSTEHCICTRL_ENAINCR8 |
  279. EXYNOS_5250_HOSTEHCICTRL_ENAINCR16;
  280. writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
  281. /* OHCI settings */
  282. ohci = readl(drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
  283. /* Following code is based on the old driver */
  284. ohci |= 0x1 << 3;
  285. writel(ohci, drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
  286. break;
  287. }
  288. exynos5250_isol(inst, 0);
  289. return 0;
  290. }
  291. static int exynos5250_power_off(struct samsung_usb2_phy_instance *inst)
  292. {
  293. struct samsung_usb2_phy_driver *drv = inst->drv;
  294. u32 ctrl0;
  295. u32 otg;
  296. u32 hsic;
  297. exynos5250_isol(inst, 1);
  298. switch (inst->cfg->id) {
  299. case EXYNOS5250_DEVICE:
  300. otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  301. otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
  302. EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG |
  303. EXYNOS_5250_USBOTGSYS_FORCE_SLEEP);
  304. writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
  305. break;
  306. case EXYNOS5250_HOST:
  307. ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
  308. ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ |
  309. EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND |
  310. EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP |
  311. EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST |
  312. EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL);
  313. writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
  314. break;
  315. case EXYNOS5250_HSIC0:
  316. case EXYNOS5250_HSIC1:
  317. hsic = (EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12 |
  318. EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT |
  319. EXYNOS_5250_HSICPHYCTRLX_SIDDQ |
  320. EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP |
  321. EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND
  322. );
  323. writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
  324. writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
  325. break;
  326. }
  327. return 0;
  328. }
  329. static const struct samsung_usb2_common_phy exynos5250_phys[] = {
  330. {
  331. .label = "device",
  332. .id = EXYNOS5250_DEVICE,
  333. .power_on = exynos5250_power_on,
  334. .power_off = exynos5250_power_off,
  335. },
  336. {
  337. .label = "host",
  338. .id = EXYNOS5250_HOST,
  339. .power_on = exynos5250_power_on,
  340. .power_off = exynos5250_power_off,
  341. },
  342. {
  343. .label = "hsic0",
  344. .id = EXYNOS5250_HSIC0,
  345. .power_on = exynos5250_power_on,
  346. .power_off = exynos5250_power_off,
  347. },
  348. {
  349. .label = "hsic1",
  350. .id = EXYNOS5250_HSIC1,
  351. .power_on = exynos5250_power_on,
  352. .power_off = exynos5250_power_off,
  353. },
  354. };
  355. const struct samsung_usb2_phy_config exynos5250_usb2_phy_config = {
  356. .has_mode_switch = 1,
  357. .num_phys = EXYNOS5250_NUM_PHYS,
  358. .phys = exynos5250_phys,
  359. .rate_to_clk = exynos5250_rate_to_clk,
  360. };