phy-exynos5250-sata.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung SATA SerDes(PHY) driver
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. * Authors: Girish K S <ks.giri@samsung.com>
  7. * Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/i2c.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/mfd/syscon.h>
  22. #define SATAPHY_CONTROL_OFFSET 0x0724
  23. #define EXYNOS5_SATAPHY_PMU_ENABLE BIT(0)
  24. #define EXYNOS5_SATA_RESET 0x4
  25. #define RESET_GLOBAL_RST_N BIT(0)
  26. #define RESET_CMN_RST_N BIT(1)
  27. #define RESET_CMN_BLOCK_RST_N BIT(2)
  28. #define RESET_CMN_I2C_RST_N BIT(3)
  29. #define RESET_TX_RX_PIPE_RST_N BIT(4)
  30. #define RESET_TX_RX_BLOCK_RST_N BIT(5)
  31. #define RESET_TX_RX_I2C_RST_N (BIT(6) | BIT(7))
  32. #define LINK_RESET 0xf0000
  33. #define EXYNOS5_SATA_MODE0 0x10
  34. #define SATA_SPD_GEN3 BIT(1)
  35. #define EXYNOS5_SATA_CTRL0 0x14
  36. #define CTRL0_P0_PHY_CALIBRATED_SEL BIT(9)
  37. #define CTRL0_P0_PHY_CALIBRATED BIT(8)
  38. #define EXYNOS5_SATA_PHSATA_CTRLM 0xe0
  39. #define PHCTRLM_REF_RATE BIT(1)
  40. #define PHCTRLM_HIGH_SPEED BIT(0)
  41. #define EXYNOS5_SATA_PHSATA_STATM 0xf0
  42. #define PHSTATM_PLL_LOCKED BIT(0)
  43. #define PHY_PLL_TIMEOUT (usecs_to_jiffies(1000))
  44. struct exynos_sata_phy {
  45. struct phy *phy;
  46. struct clk *phyclk;
  47. void __iomem *regs;
  48. struct regmap *pmureg;
  49. struct i2c_client *client;
  50. };
  51. static int wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
  52. u32 status)
  53. {
  54. unsigned long timeout = jiffies + PHY_PLL_TIMEOUT;
  55. while (time_before(jiffies, timeout)) {
  56. if ((readl(base + reg) & checkbit) == status)
  57. return 0;
  58. }
  59. return -EFAULT;
  60. }
  61. static int exynos_sata_phy_power_on(struct phy *phy)
  62. {
  63. struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
  64. return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
  65. EXYNOS5_SATAPHY_PMU_ENABLE, true);
  66. }
  67. static int exynos_sata_phy_power_off(struct phy *phy)
  68. {
  69. struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
  70. return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
  71. EXYNOS5_SATAPHY_PMU_ENABLE, false);
  72. }
  73. static int exynos_sata_phy_init(struct phy *phy)
  74. {
  75. u32 val = 0;
  76. int ret = 0;
  77. u8 buf[] = { 0x3a, 0x0b };
  78. struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
  79. ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
  80. EXYNOS5_SATAPHY_PMU_ENABLE, true);
  81. if (ret != 0)
  82. dev_err(&sata_phy->phy->dev, "phy init failed\n");
  83. writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
  84. val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
  85. val |= RESET_GLOBAL_RST_N | RESET_CMN_RST_N | RESET_CMN_BLOCK_RST_N
  86. | RESET_CMN_I2C_RST_N | RESET_TX_RX_PIPE_RST_N
  87. | RESET_TX_RX_BLOCK_RST_N | RESET_TX_RX_I2C_RST_N;
  88. writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
  89. val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
  90. val |= LINK_RESET;
  91. writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
  92. val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
  93. val |= RESET_CMN_RST_N;
  94. writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
  95. val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
  96. val &= ~PHCTRLM_REF_RATE;
  97. writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
  98. /* High speed enable for Gen3 */
  99. val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
  100. val |= PHCTRLM_HIGH_SPEED;
  101. writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
  102. val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);
  103. val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
  104. writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
  105. val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0);
  106. val |= SATA_SPD_GEN3;
  107. writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0);
  108. ret = i2c_master_send(sata_phy->client, buf, sizeof(buf));
  109. if (ret < 0)
  110. return ret;
  111. /* release cmu reset */
  112. val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
  113. val &= ~RESET_CMN_RST_N;
  114. writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
  115. val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
  116. val |= RESET_CMN_RST_N;
  117. writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
  118. ret = wait_for_reg_status(sata_phy->regs,
  119. EXYNOS5_SATA_PHSATA_STATM,
  120. PHSTATM_PLL_LOCKED, 1);
  121. if (ret < 0)
  122. dev_err(&sata_phy->phy->dev,
  123. "PHY PLL locking failed\n");
  124. return ret;
  125. }
  126. static const struct phy_ops exynos_sata_phy_ops = {
  127. .init = exynos_sata_phy_init,
  128. .power_on = exynos_sata_phy_power_on,
  129. .power_off = exynos_sata_phy_power_off,
  130. .owner = THIS_MODULE,
  131. };
  132. static int exynos_sata_phy_probe(struct platform_device *pdev)
  133. {
  134. struct exynos_sata_phy *sata_phy;
  135. struct device *dev = &pdev->dev;
  136. struct resource *res;
  137. struct phy_provider *phy_provider;
  138. struct device_node *node;
  139. int ret = 0;
  140. sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
  141. if (!sata_phy)
  142. return -ENOMEM;
  143. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  144. sata_phy->regs = devm_ioremap_resource(dev, res);
  145. if (IS_ERR(sata_phy->regs))
  146. return PTR_ERR(sata_phy->regs);
  147. sata_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
  148. "samsung,syscon-phandle");
  149. if (IS_ERR(sata_phy->pmureg)) {
  150. dev_err(dev, "syscon regmap lookup failed.\n");
  151. return PTR_ERR(sata_phy->pmureg);
  152. }
  153. node = of_parse_phandle(dev->of_node,
  154. "samsung,exynos-sataphy-i2c-phandle", 0);
  155. if (!node)
  156. return -EINVAL;
  157. sata_phy->client = of_find_i2c_device_by_node(node);
  158. if (!sata_phy->client)
  159. return -EPROBE_DEFER;
  160. dev_set_drvdata(dev, sata_phy);
  161. sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl");
  162. if (IS_ERR(sata_phy->phyclk)) {
  163. dev_err(dev, "failed to get clk for PHY\n");
  164. return PTR_ERR(sata_phy->phyclk);
  165. }
  166. ret = clk_prepare_enable(sata_phy->phyclk);
  167. if (ret < 0) {
  168. dev_err(dev, "failed to enable source clk\n");
  169. return ret;
  170. }
  171. sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops);
  172. if (IS_ERR(sata_phy->phy)) {
  173. clk_disable_unprepare(sata_phy->phyclk);
  174. dev_err(dev, "failed to create PHY\n");
  175. return PTR_ERR(sata_phy->phy);
  176. }
  177. phy_set_drvdata(sata_phy->phy, sata_phy);
  178. phy_provider = devm_of_phy_provider_register(dev,
  179. of_phy_simple_xlate);
  180. if (IS_ERR(phy_provider)) {
  181. clk_disable_unprepare(sata_phy->phyclk);
  182. return PTR_ERR(phy_provider);
  183. }
  184. return 0;
  185. }
  186. static const struct of_device_id exynos_sata_phy_of_match[] = {
  187. { .compatible = "samsung,exynos5250-sata-phy" },
  188. { },
  189. };
  190. MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
  191. static struct platform_driver exynos_sata_phy_driver = {
  192. .probe = exynos_sata_phy_probe,
  193. .driver = {
  194. .of_match_table = exynos_sata_phy_of_match,
  195. .name = "samsung,sata-phy",
  196. .suppress_bind_attrs = true,
  197. }
  198. };
  199. module_platform_driver(exynos_sata_phy_driver);
  200. MODULE_DESCRIPTION("Samsung SerDes PHY driver");
  201. MODULE_LICENSE("GPL v2");
  202. MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
  203. MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");