phy-exynos4210-usb2.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. * Author: Kamil Debski <k.debski@samsung.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/phy/phy.h>
  11. #include <linux/regmap.h>
  12. #include "phy-samsung-usb2.h"
  13. /* Exynos USB PHY registers */
  14. /* PHY power control */
  15. #define EXYNOS_4210_UPHYPWR 0x0
  16. #define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0)
  17. #define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3)
  18. #define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4)
  19. #define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5)
  20. #define EXYNOS_4210_UPHYPWR_PHY0 ( \
  21. EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \
  22. EXYNOS_4210_UPHYPWR_PHY0_PWR | \
  23. EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \
  24. EXYNOS_4210_UPHYPWR_PHY0_SLEEP)
  25. #define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6)
  26. #define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7)
  27. #define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8)
  28. #define EXYNOS_4210_UPHYPWR_PHY1 ( \
  29. EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \
  30. EXYNOS_4210_UPHYPWR_PHY1_PWR | \
  31. EXYNOS_4210_UPHYPWR_PHY1_SLEEP)
  32. #define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9)
  33. #define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10)
  34. #define EXYNOS_4210_UPHYPWR_HSIC0 ( \
  35. EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND | \
  36. EXYNOS_4210_UPHYPWR_HSIC0_SLEEP)
  37. #define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11)
  38. #define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP BIT(12)
  39. #define EXYNOS_4210_UPHYPWR_HSIC1 ( \
  40. EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND | \
  41. EXYNOS_4210_UPHYPWR_HSIC1_SLEEP)
  42. /* PHY clock control */
  43. #define EXYNOS_4210_UPHYCLK 0x4
  44. #define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
  45. #define EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET 0
  46. #define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
  47. #define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
  48. #define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
  49. #define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
  50. #define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON BIT(4)
  51. #define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON BIT(7)
  52. /* PHY reset control */
  53. #define EXYNOS_4210_UPHYRST 0x8
  54. #define EXYNOS_4210_URSTCON_PHY0 BIT(0)
  55. #define EXYNOS_4210_URSTCON_OTG_HLINK BIT(1)
  56. #define EXYNOS_4210_URSTCON_OTG_PHYLINK BIT(2)
  57. #define EXYNOS_4210_URSTCON_PHY1_ALL BIT(3)
  58. #define EXYNOS_4210_URSTCON_PHY1_P0 BIT(4)
  59. #define EXYNOS_4210_URSTCON_PHY1_P1P2 BIT(5)
  60. #define EXYNOS_4210_URSTCON_HOST_LINK_ALL BIT(6)
  61. #define EXYNOS_4210_URSTCON_HOST_LINK_P0 BIT(7)
  62. #define EXYNOS_4210_URSTCON_HOST_LINK_P1 BIT(8)
  63. #define EXYNOS_4210_URSTCON_HOST_LINK_P2 BIT(9)
  64. /* Isolation, configured in the power management unit */
  65. #define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET 0x704
  66. #define EXYNOS_4210_USB_ISOL_DEVICE BIT(0)
  67. #define EXYNOS_4210_USB_ISOL_HOST_OFFSET 0x708
  68. #define EXYNOS_4210_USB_ISOL_HOST BIT(0)
  69. /* USBYPHY1 Floating prevention */
  70. #define EXYNOS_4210_UPHY1CON 0x34
  71. #define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION 0x1
  72. /* Mode switching SUB Device <-> Host */
  73. #define EXYNOS_4210_MODE_SWITCH_OFFSET 0x21c
  74. #define EXYNOS_4210_MODE_SWITCH_MASK 1
  75. #define EXYNOS_4210_MODE_SWITCH_DEVICE 0
  76. #define EXYNOS_4210_MODE_SWITCH_HOST 1
  77. enum exynos4210_phy_id {
  78. EXYNOS4210_DEVICE,
  79. EXYNOS4210_HOST,
  80. EXYNOS4210_HSIC0,
  81. EXYNOS4210_HSIC1,
  82. EXYNOS4210_NUM_PHYS,
  83. };
  84. /*
  85. * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
  86. * can be written to the phy register.
  87. */
  88. static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
  89. {
  90. switch (rate) {
  91. case 12 * MHZ:
  92. *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
  93. break;
  94. case 24 * MHZ:
  95. *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
  96. break;
  97. case 48 * MHZ:
  98. *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
  99. break;
  100. default:
  101. return -EINVAL;
  102. }
  103. return 0;
  104. }
  105. static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on)
  106. {
  107. struct samsung_usb2_phy_driver *drv = inst->drv;
  108. u32 offset;
  109. u32 mask;
  110. switch (inst->cfg->id) {
  111. case EXYNOS4210_DEVICE:
  112. offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
  113. mask = EXYNOS_4210_USB_ISOL_DEVICE;
  114. break;
  115. case EXYNOS4210_HOST:
  116. offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
  117. mask = EXYNOS_4210_USB_ISOL_HOST;
  118. break;
  119. default:
  120. return;
  121. }
  122. regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
  123. }
  124. static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
  125. {
  126. struct samsung_usb2_phy_driver *drv = inst->drv;
  127. u32 rstbits = 0;
  128. u32 phypwr = 0;
  129. u32 rst;
  130. u32 pwr;
  131. u32 clk;
  132. switch (inst->cfg->id) {
  133. case EXYNOS4210_DEVICE:
  134. phypwr = EXYNOS_4210_UPHYPWR_PHY0;
  135. rstbits = EXYNOS_4210_URSTCON_PHY0;
  136. break;
  137. case EXYNOS4210_HOST:
  138. phypwr = EXYNOS_4210_UPHYPWR_PHY1;
  139. rstbits = EXYNOS_4210_URSTCON_PHY1_ALL |
  140. EXYNOS_4210_URSTCON_PHY1_P0 |
  141. EXYNOS_4210_URSTCON_PHY1_P1P2 |
  142. EXYNOS_4210_URSTCON_HOST_LINK_ALL |
  143. EXYNOS_4210_URSTCON_HOST_LINK_P0;
  144. writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
  145. break;
  146. case EXYNOS4210_HSIC0:
  147. phypwr = EXYNOS_4210_UPHYPWR_HSIC0;
  148. rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 |
  149. EXYNOS_4210_URSTCON_HOST_LINK_P1;
  150. break;
  151. case EXYNOS4210_HSIC1:
  152. phypwr = EXYNOS_4210_UPHYPWR_HSIC1;
  153. rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 |
  154. EXYNOS_4210_URSTCON_HOST_LINK_P2;
  155. break;
  156. }
  157. if (on) {
  158. clk = readl(drv->reg_phy + EXYNOS_4210_UPHYCLK);
  159. clk &= ~EXYNOS_4210_UPHYCLK_PHYFSEL_MASK;
  160. clk |= drv->ref_reg_val << EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET;
  161. writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK);
  162. pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
  163. pwr &= ~phypwr;
  164. writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
  165. rst = readl(drv->reg_phy + EXYNOS_4210_UPHYRST);
  166. rst |= rstbits;
  167. writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
  168. udelay(10);
  169. rst &= ~rstbits;
  170. writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
  171. /* The following delay is necessary for the reset sequence to be
  172. * completed */
  173. udelay(80);
  174. } else {
  175. pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
  176. pwr |= phypwr;
  177. writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
  178. }
  179. }
  180. static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst)
  181. {
  182. /* Order of initialisation is important - first power then isolation */
  183. exynos4210_phy_pwr(inst, 1);
  184. exynos4210_isol(inst, 0);
  185. return 0;
  186. }
  187. static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst)
  188. {
  189. exynos4210_isol(inst, 1);
  190. exynos4210_phy_pwr(inst, 0);
  191. return 0;
  192. }
  193. static const struct samsung_usb2_common_phy exynos4210_phys[] = {
  194. {
  195. .label = "device",
  196. .id = EXYNOS4210_DEVICE,
  197. .power_on = exynos4210_power_on,
  198. .power_off = exynos4210_power_off,
  199. },
  200. {
  201. .label = "host",
  202. .id = EXYNOS4210_HOST,
  203. .power_on = exynos4210_power_on,
  204. .power_off = exynos4210_power_off,
  205. },
  206. {
  207. .label = "hsic0",
  208. .id = EXYNOS4210_HSIC0,
  209. .power_on = exynos4210_power_on,
  210. .power_off = exynos4210_power_off,
  211. },
  212. {
  213. .label = "hsic1",
  214. .id = EXYNOS4210_HSIC1,
  215. .power_on = exynos4210_power_on,
  216. .power_off = exynos4210_power_off,
  217. },
  218. };
  219. const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
  220. .has_mode_switch = 0,
  221. .num_phys = EXYNOS4210_NUM_PHYS,
  222. .phys = exynos4210_phys,
  223. .rate_to_clk = exynos4210_rate_to_clk,
  224. };