phy-exynos-mipi-video.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
  4. *
  5. * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
  6. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  7. */
  8. #include <linux/err.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/regmap.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/soc/samsung/exynos-regs-pmu.h>
  19. #include <linux/mfd/syscon.h>
  20. enum exynos_mipi_phy_id {
  21. EXYNOS_MIPI_PHY_ID_NONE = -1,
  22. EXYNOS_MIPI_PHY_ID_CSIS0,
  23. EXYNOS_MIPI_PHY_ID_DSIM0,
  24. EXYNOS_MIPI_PHY_ID_CSIS1,
  25. EXYNOS_MIPI_PHY_ID_DSIM1,
  26. EXYNOS_MIPI_PHY_ID_CSIS2,
  27. EXYNOS_MIPI_PHYS_NUM
  28. };
  29. enum exynos_mipi_phy_regmap_id {
  30. EXYNOS_MIPI_REGMAP_PMU,
  31. EXYNOS_MIPI_REGMAP_DISP,
  32. EXYNOS_MIPI_REGMAP_CAM0,
  33. EXYNOS_MIPI_REGMAP_CAM1,
  34. EXYNOS_MIPI_REGMAPS_NUM
  35. };
  36. struct mipi_phy_device_desc {
  37. int num_phys;
  38. int num_regmaps;
  39. const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
  40. struct exynos_mipi_phy_desc {
  41. enum exynos_mipi_phy_id coupled_phy_id;
  42. u32 enable_val;
  43. unsigned int enable_reg;
  44. enum exynos_mipi_phy_regmap_id enable_map;
  45. u32 resetn_val;
  46. unsigned int resetn_reg;
  47. enum exynos_mipi_phy_regmap_id resetn_map;
  48. } phys[EXYNOS_MIPI_PHYS_NUM];
  49. };
  50. static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
  51. .num_regmaps = 1,
  52. .regmap_names = {"syscon"},
  53. .num_phys = 4,
  54. .phys = {
  55. {
  56. /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  57. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  58. .enable_val = EXYNOS4_PHY_ENABLE,
  59. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  60. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  61. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  62. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  63. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  64. }, {
  65. /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  66. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  67. .enable_val = EXYNOS4_PHY_ENABLE,
  68. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  69. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  70. .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  71. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  72. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  73. }, {
  74. /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  75. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
  76. .enable_val = EXYNOS4_PHY_ENABLE,
  77. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  78. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  79. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  80. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  81. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  82. }, {
  83. /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  84. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
  85. .enable_val = EXYNOS4_PHY_ENABLE,
  86. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  87. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  88. .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  89. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  90. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  91. },
  92. },
  93. };
  94. static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
  95. .num_regmaps = 1,
  96. .regmap_names = {"syscon"},
  97. .num_phys = 5,
  98. .phys = {
  99. {
  100. /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  101. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  102. .enable_val = EXYNOS4_PHY_ENABLE,
  103. .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
  104. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  105. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  106. .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
  107. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  108. }, {
  109. /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  110. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  111. .enable_val = EXYNOS4_PHY_ENABLE,
  112. .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
  113. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  114. .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  115. .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
  116. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  117. }, {
  118. /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  119. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
  120. .enable_val = EXYNOS4_PHY_ENABLE,
  121. .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
  122. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  123. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  124. .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
  125. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  126. }, {
  127. /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  128. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
  129. .enable_val = EXYNOS4_PHY_ENABLE,
  130. .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
  131. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  132. .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  133. .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
  134. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  135. }, {
  136. /* EXYNOS_MIPI_PHY_ID_CSIS2 */
  137. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  138. .enable_val = EXYNOS4_PHY_ENABLE,
  139. .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
  140. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  141. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  142. .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
  143. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  144. },
  145. },
  146. };
  147. #define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
  148. #define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
  149. #define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
  150. static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
  151. .num_regmaps = 4,
  152. .regmap_names = {
  153. "samsung,pmu-syscon",
  154. "samsung,disp-sysreg",
  155. "samsung,cam0-sysreg",
  156. "samsung,cam1-sysreg"
  157. },
  158. .num_phys = 5,
  159. .phys = {
  160. {
  161. /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  162. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  163. .enable_val = EXYNOS4_PHY_ENABLE,
  164. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  165. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  166. .resetn_val = BIT(0),
  167. .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
  168. .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
  169. }, {
  170. /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  171. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  172. .enable_val = EXYNOS4_PHY_ENABLE,
  173. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  174. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  175. .resetn_val = BIT(0),
  176. .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
  177. .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
  178. }, {
  179. /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  180. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  181. .enable_val = EXYNOS4_PHY_ENABLE,
  182. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  183. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  184. .resetn_val = BIT(1),
  185. .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
  186. .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
  187. }, {
  188. /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  189. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  190. .enable_val = EXYNOS4_PHY_ENABLE,
  191. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  192. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  193. .resetn_val = BIT(1),
  194. .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
  195. .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
  196. }, {
  197. /* EXYNOS_MIPI_PHY_ID_CSIS2 */
  198. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  199. .enable_val = EXYNOS4_PHY_ENABLE,
  200. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
  201. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  202. .resetn_val = BIT(0),
  203. .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
  204. .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
  205. },
  206. },
  207. };
  208. struct exynos_mipi_video_phy {
  209. struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
  210. int num_phys;
  211. struct video_phy_desc {
  212. struct phy *phy;
  213. unsigned int index;
  214. const struct exynos_mipi_phy_desc *data;
  215. } phys[EXYNOS_MIPI_PHYS_NUM];
  216. spinlock_t slock;
  217. };
  218. static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
  219. struct exynos_mipi_video_phy *state, unsigned int on)
  220. {
  221. struct regmap *enable_map = state->regmaps[data->enable_map];
  222. struct regmap *resetn_map = state->regmaps[data->resetn_map];
  223. spin_lock(&state->slock);
  224. /* disable in PMU sysreg */
  225. if (!on && data->coupled_phy_id >= 0 &&
  226. state->phys[data->coupled_phy_id].phy->power_count == 0)
  227. regmap_update_bits(enable_map, data->enable_reg,
  228. data->enable_val, 0);
  229. /* PHY reset */
  230. if (on)
  231. regmap_update_bits(resetn_map, data->resetn_reg,
  232. data->resetn_val, data->resetn_val);
  233. else
  234. regmap_update_bits(resetn_map, data->resetn_reg,
  235. data->resetn_val, 0);
  236. /* enable in PMU sysreg */
  237. if (on)
  238. regmap_update_bits(enable_map, data->enable_reg,
  239. data->enable_val, data->enable_val);
  240. spin_unlock(&state->slock);
  241. return 0;
  242. }
  243. #define to_mipi_video_phy(desc) \
  244. container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
  245. static int exynos_mipi_video_phy_power_on(struct phy *phy)
  246. {
  247. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  248. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  249. return __set_phy_state(phy_desc->data, state, 1);
  250. }
  251. static int exynos_mipi_video_phy_power_off(struct phy *phy)
  252. {
  253. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  254. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  255. return __set_phy_state(phy_desc->data, state, 0);
  256. }
  257. static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
  258. struct of_phandle_args *args)
  259. {
  260. struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
  261. if (WARN_ON(args->args[0] >= state->num_phys))
  262. return ERR_PTR(-ENODEV);
  263. return state->phys[args->args[0]].phy;
  264. }
  265. static const struct phy_ops exynos_mipi_video_phy_ops = {
  266. .power_on = exynos_mipi_video_phy_power_on,
  267. .power_off = exynos_mipi_video_phy_power_off,
  268. .owner = THIS_MODULE,
  269. };
  270. static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
  271. {
  272. const struct mipi_phy_device_desc *phy_dev;
  273. struct exynos_mipi_video_phy *state;
  274. struct device *dev = &pdev->dev;
  275. struct device_node *np = dev->of_node;
  276. struct phy_provider *phy_provider;
  277. unsigned int i;
  278. phy_dev = of_device_get_match_data(dev);
  279. if (!phy_dev)
  280. return -ENODEV;
  281. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  282. if (!state)
  283. return -ENOMEM;
  284. for (i = 0; i < phy_dev->num_regmaps; i++) {
  285. state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
  286. phy_dev->regmap_names[i]);
  287. if (IS_ERR(state->regmaps[i]))
  288. return PTR_ERR(state->regmaps[i]);
  289. }
  290. state->num_phys = phy_dev->num_phys;
  291. spin_lock_init(&state->slock);
  292. dev_set_drvdata(dev, state);
  293. for (i = 0; i < state->num_phys; i++) {
  294. struct phy *phy = devm_phy_create(dev, NULL,
  295. &exynos_mipi_video_phy_ops);
  296. if (IS_ERR(phy)) {
  297. dev_err(dev, "failed to create PHY %d\n", i);
  298. return PTR_ERR(phy);
  299. }
  300. state->phys[i].phy = phy;
  301. state->phys[i].index = i;
  302. state->phys[i].data = &phy_dev->phys[i];
  303. phy_set_drvdata(phy, &state->phys[i]);
  304. }
  305. phy_provider = devm_of_phy_provider_register(dev,
  306. exynos_mipi_video_phy_xlate);
  307. return PTR_ERR_OR_ZERO(phy_provider);
  308. }
  309. static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
  310. {
  311. .compatible = "samsung,s5pv210-mipi-video-phy",
  312. .data = &s5pv210_mipi_phy,
  313. }, {
  314. .compatible = "samsung,exynos5420-mipi-video-phy",
  315. .data = &exynos5420_mipi_phy,
  316. }, {
  317. .compatible = "samsung,exynos5433-mipi-video-phy",
  318. .data = &exynos5433_mipi_phy,
  319. },
  320. { /* sentinel */ },
  321. };
  322. MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
  323. static struct platform_driver exynos_mipi_video_phy_driver = {
  324. .probe = exynos_mipi_video_phy_probe,
  325. .driver = {
  326. .of_match_table = exynos_mipi_video_phy_of_match,
  327. .name = "exynos-mipi-video-phy",
  328. .suppress_bind_attrs = true,
  329. }
  330. };
  331. module_platform_driver(exynos_mipi_video_phy_driver);
  332. MODULE_DESCRIPTION("Samsung S5P/Exynos SoC MIPI CSI-2/DSI PHY driver");
  333. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  334. MODULE_LICENSE("GPL v2");