phy-ralink-usb.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2017 John Crispin <john@phrozen.org>
  4. *
  5. * Based on code from
  6. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/module.h>
  14. #include <linux/mutex.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regmap.h>
  19. #include <linux/reset.h>
  20. #define RT_SYSC_REG_SYSCFG1 0x014
  21. #define RT_SYSC_REG_CLKCFG1 0x030
  22. #define RT_SYSC_REG_USB_PHY_CFG 0x05c
  23. #define OFS_U2_PHY_AC0 0x800
  24. #define OFS_U2_PHY_AC1 0x804
  25. #define OFS_U2_PHY_AC2 0x808
  26. #define OFS_U2_PHY_ACR0 0x810
  27. #define OFS_U2_PHY_ACR1 0x814
  28. #define OFS_U2_PHY_ACR2 0x818
  29. #define OFS_U2_PHY_ACR3 0x81C
  30. #define OFS_U2_PHY_ACR4 0x820
  31. #define OFS_U2_PHY_AMON0 0x824
  32. #define OFS_U2_PHY_DCR0 0x860
  33. #define OFS_U2_PHY_DCR1 0x864
  34. #define OFS_U2_PHY_DTM0 0x868
  35. #define OFS_U2_PHY_DTM1 0x86C
  36. #define RT_RSTCTRL_UDEV BIT(25)
  37. #define RT_RSTCTRL_UHST BIT(22)
  38. #define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
  39. #define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
  40. #define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
  41. #define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
  42. #define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
  43. #define USB_PHY_UTMI_8B60M BIT(1)
  44. #define UDEV_WAKEUP BIT(0)
  45. struct ralink_usb_phy {
  46. struct reset_control *rstdev;
  47. struct reset_control *rsthost;
  48. u32 clk;
  49. struct phy *phy;
  50. void __iomem *base;
  51. struct regmap *sysctl;
  52. };
  53. static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
  54. {
  55. writel(val, phy->base + reg);
  56. }
  57. static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
  58. {
  59. return readl(phy->base + reg);
  60. }
  61. static void ralink_usb_phy_init(struct ralink_usb_phy *phy)
  62. {
  63. u2_phy_r32(phy, OFS_U2_PHY_AC2);
  64. u2_phy_r32(phy, OFS_U2_PHY_ACR0);
  65. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  66. u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
  67. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  68. u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
  69. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  70. u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
  71. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  72. u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
  73. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  74. u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
  75. u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
  76. u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
  77. u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
  78. }
  79. static int ralink_usb_phy_power_on(struct phy *_phy)
  80. {
  81. struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
  82. u32 t;
  83. /* enable the phy */
  84. regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
  85. phy->clk, phy->clk);
  86. /* setup host mode */
  87. regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
  88. RT_SYSCFG1_USB0_HOST_MODE,
  89. RT_SYSCFG1_USB0_HOST_MODE);
  90. /* deassert the reset lines */
  91. reset_control_deassert(phy->rsthost);
  92. reset_control_deassert(phy->rstdev);
  93. /*
  94. * The SDK kernel had a delay of 100ms. however on device
  95. * testing showed that 10ms is enough
  96. */
  97. mdelay(10);
  98. if (phy->base)
  99. ralink_usb_phy_init(phy);
  100. /* print some status info */
  101. regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
  102. dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
  103. (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
  104. if (t & USB_PHY_UTMI_8B60M)
  105. dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
  106. else
  107. dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
  108. return 0;
  109. }
  110. static int ralink_usb_phy_power_off(struct phy *_phy)
  111. {
  112. struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
  113. /* disable the phy */
  114. regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
  115. phy->clk, 0);
  116. /* assert the reset lines */
  117. reset_control_assert(phy->rstdev);
  118. reset_control_assert(phy->rsthost);
  119. return 0;
  120. }
  121. static const struct phy_ops ralink_usb_phy_ops = {
  122. .power_on = ralink_usb_phy_power_on,
  123. .power_off = ralink_usb_phy_power_off,
  124. .owner = THIS_MODULE,
  125. };
  126. static const struct of_device_id ralink_usb_phy_of_match[] = {
  127. {
  128. .compatible = "ralink,rt3352-usbphy",
  129. .data = (void *)(uintptr_t)(RT_CLKCFG1_UPHY1_CLK_EN |
  130. RT_CLKCFG1_UPHY0_CLK_EN)
  131. },
  132. {
  133. .compatible = "mediatek,mt7620-usbphy",
  134. .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
  135. MT7620_CLKCFG1_UPHY0_CLK_EN)
  136. },
  137. {
  138. .compatible = "mediatek,mt7628-usbphy",
  139. .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
  140. MT7620_CLKCFG1_UPHY0_CLK_EN) },
  141. { },
  142. };
  143. MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
  144. static int ralink_usb_phy_probe(struct platform_device *pdev)
  145. {
  146. struct device *dev = &pdev->dev;
  147. struct resource *res;
  148. struct phy_provider *phy_provider;
  149. const struct of_device_id *match;
  150. struct ralink_usb_phy *phy;
  151. match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
  152. if (!match)
  153. return -ENODEV;
  154. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  155. if (!phy)
  156. return -ENOMEM;
  157. phy->clk = (uintptr_t)match->data;
  158. phy->base = NULL;
  159. phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");
  160. if (IS_ERR(phy->sysctl)) {
  161. dev_err(dev, "failed to get sysctl registers\n");
  162. return PTR_ERR(phy->sysctl);
  163. }
  164. /* The MT7628 and MT7688 require extra setup of PHY registers. */
  165. if (of_device_is_compatible(dev->of_node, "mediatek,mt7628-usbphy")) {
  166. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  167. phy->base = devm_ioremap_resource(&pdev->dev, res);
  168. if (IS_ERR(phy->base)) {
  169. dev_err(dev, "failed to remap register memory\n");
  170. return PTR_ERR(phy->base);
  171. }
  172. }
  173. phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
  174. if (IS_ERR(phy->rsthost)) {
  175. dev_err(dev, "host reset is missing\n");
  176. return PTR_ERR(phy->rsthost);
  177. }
  178. phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
  179. if (IS_ERR(phy->rstdev)) {
  180. dev_err(dev, "device reset is missing\n");
  181. return PTR_ERR(phy->rstdev);
  182. }
  183. phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
  184. if (IS_ERR(phy->phy)) {
  185. dev_err(dev, "failed to create PHY\n");
  186. return PTR_ERR(phy->phy);
  187. }
  188. phy_set_drvdata(phy->phy, phy);
  189. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  190. return PTR_ERR_OR_ZERO(phy_provider);
  191. }
  192. static struct platform_driver ralink_usb_phy_driver = {
  193. .probe = ralink_usb_phy_probe,
  194. .driver = {
  195. .of_match_table = ralink_usb_phy_of_match,
  196. .name = "ralink-usb-phy",
  197. }
  198. };
  199. module_platform_driver(ralink_usb_phy_driver);
  200. MODULE_DESCRIPTION("Ralink USB phy driver");
  201. MODULE_AUTHOR("John Crispin <john@phrozen.org>");
  202. MODULE_LICENSE("GPL v2");