phy-pxa-28nm-usb2.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Linaro, Ltd.
  4. * Rob Herring <robh@kernel.org>
  5. *
  6. * Based on vendor driver:
  7. * Copyright (C) 2013 Marvell Inc.
  8. * Author: Chao Xie <xiechao.mail@gmail.com>
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/slab.h>
  12. #include <linux/of.h>
  13. #include <linux/of_device.h>
  14. #include <linux/io.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/err.h>
  17. #include <linux/clk.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/phy/phy.h>
  21. /* USB PXA1928 PHY mapping */
  22. #define PHY_28NM_PLL_REG0 0x0
  23. #define PHY_28NM_PLL_REG1 0x4
  24. #define PHY_28NM_CAL_REG 0x8
  25. #define PHY_28NM_TX_REG0 0x0c
  26. #define PHY_28NM_TX_REG1 0x10
  27. #define PHY_28NM_RX_REG0 0x14
  28. #define PHY_28NM_RX_REG1 0x18
  29. #define PHY_28NM_DIG_REG0 0x1c
  30. #define PHY_28NM_DIG_REG1 0x20
  31. #define PHY_28NM_TEST_REG0 0x24
  32. #define PHY_28NM_TEST_REG1 0x28
  33. #define PHY_28NM_MOC_REG 0x2c
  34. #define PHY_28NM_PHY_RESERVE 0x30
  35. #define PHY_28NM_OTG_REG 0x34
  36. #define PHY_28NM_CHRG_DET 0x38
  37. #define PHY_28NM_CTRL_REG0 0xc4
  38. #define PHY_28NM_CTRL_REG1 0xc8
  39. #define PHY_28NM_CTRL_REG2 0xd4
  40. #define PHY_28NM_CTRL_REG3 0xdc
  41. /* PHY_28NM_PLL_REG0 */
  42. #define PHY_28NM_PLL_READY BIT(31)
  43. #define PHY_28NM_PLL_SELLPFR_SHIFT 28
  44. #define PHY_28NM_PLL_SELLPFR_MASK (0x3 << 28)
  45. #define PHY_28NM_PLL_FBDIV_SHIFT 16
  46. #define PHY_28NM_PLL_FBDIV_MASK (0x1ff << 16)
  47. #define PHY_28NM_PLL_ICP_SHIFT 8
  48. #define PHY_28NM_PLL_ICP_MASK (0x7 << 8)
  49. #define PHY_28NM_PLL_REFDIV_SHIFT 0
  50. #define PHY_28NM_PLL_REFDIV_MASK 0x7f
  51. /* PHY_28NM_PLL_REG1 */
  52. #define PHY_28NM_PLL_PU_BY_REG BIT(1)
  53. #define PHY_28NM_PLL_PU_PLL BIT(0)
  54. /* PHY_28NM_CAL_REG */
  55. #define PHY_28NM_PLL_PLLCAL_DONE BIT(31)
  56. #define PHY_28NM_PLL_IMPCAL_DONE BIT(23)
  57. #define PHY_28NM_PLL_KVCO_SHIFT 16
  58. #define PHY_28NM_PLL_KVCO_MASK (0x7 << 16)
  59. #define PHY_28NM_PLL_CAL12_SHIFT 20
  60. #define PHY_28NM_PLL_CAL12_MASK (0x3 << 20)
  61. #define PHY_28NM_IMPCAL_VTH_SHIFT 8
  62. #define PHY_28NM_IMPCAL_VTH_MASK (0x7 << 8)
  63. #define PHY_28NM_PLLCAL_START_SHIFT 22
  64. #define PHY_28NM_IMPCAL_START_SHIFT 13
  65. /* PHY_28NM_TX_REG0 */
  66. #define PHY_28NM_TX_PU_BY_REG BIT(25)
  67. #define PHY_28NM_TX_PU_ANA BIT(24)
  68. #define PHY_28NM_TX_AMP_SHIFT 20
  69. #define PHY_28NM_TX_AMP_MASK (0x7 << 20)
  70. /* PHY_28NM_RX_REG0 */
  71. #define PHY_28NM_RX_SQ_THRESH_SHIFT 0
  72. #define PHY_28NM_RX_SQ_THRESH_MASK (0xf << 0)
  73. /* PHY_28NM_RX_REG1 */
  74. #define PHY_28NM_RX_SQCAL_DONE BIT(31)
  75. /* PHY_28NM_DIG_REG0 */
  76. #define PHY_28NM_DIG_BITSTAFFING_ERR BIT(31)
  77. #define PHY_28NM_DIG_SYNC_ERR BIT(30)
  78. #define PHY_28NM_DIG_SQ_FILT_SHIFT 16
  79. #define PHY_28NM_DIG_SQ_FILT_MASK (0x7 << 16)
  80. #define PHY_28NM_DIG_SQ_BLK_SHIFT 12
  81. #define PHY_28NM_DIG_SQ_BLK_MASK (0x7 << 12)
  82. #define PHY_28NM_DIG_SYNC_NUM_SHIFT 0
  83. #define PHY_28NM_DIG_SYNC_NUM_MASK (0x3 << 0)
  84. #define PHY_28NM_PLL_LOCK_BYPASS BIT(7)
  85. /* PHY_28NM_OTG_REG */
  86. #define PHY_28NM_OTG_CONTROL_BY_PIN BIT(5)
  87. #define PHY_28NM_OTG_PU_OTG BIT(4)
  88. #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 13
  89. #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 12
  90. #define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28 10
  91. #define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28 8
  92. #define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 7
  93. #define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28 6
  94. #define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28 5
  95. #define PHY_28NM_CHGDTC_PD_EN_SHIFT_28 4
  96. #define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28 3
  97. #define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28 2
  98. #define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 0
  99. #define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28 4
  100. #define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28 2
  101. #define PHY_28NM_CTRL3_OVERWRITE BIT(0)
  102. #define PHY_28NM_CTRL3_VBUS_VALID BIT(4)
  103. #define PHY_28NM_CTRL3_AVALID BIT(5)
  104. #define PHY_28NM_CTRL3_BVALID BIT(6)
  105. struct mv_usb2_phy {
  106. struct phy *phy;
  107. struct platform_device *pdev;
  108. void __iomem *base;
  109. struct clk *clk;
  110. };
  111. static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
  112. {
  113. u32 val;
  114. return readl_poll_timeout(reg, val, ((val & mask) == mask),
  115. 1000, 1000 * ms);
  116. }
  117. static int mv_usb2_phy_28nm_init(struct phy *phy)
  118. {
  119. struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
  120. struct platform_device *pdev = mv_phy->pdev;
  121. void __iomem *base = mv_phy->base;
  122. u32 reg;
  123. int ret;
  124. clk_prepare_enable(mv_phy->clk);
  125. /* PHY_28NM_PLL_REG0 */
  126. reg = readl(base + PHY_28NM_PLL_REG0) &
  127. ~(PHY_28NM_PLL_SELLPFR_MASK | PHY_28NM_PLL_FBDIV_MASK
  128. | PHY_28NM_PLL_ICP_MASK | PHY_28NM_PLL_REFDIV_MASK);
  129. writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT
  130. | 0xf0 << PHY_28NM_PLL_FBDIV_SHIFT
  131. | 0x3 << PHY_28NM_PLL_ICP_SHIFT
  132. | 0xd << PHY_28NM_PLL_REFDIV_SHIFT),
  133. base + PHY_28NM_PLL_REG0);
  134. /* PHY_28NM_PLL_REG1 */
  135. reg = readl(base + PHY_28NM_PLL_REG1);
  136. writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG,
  137. base + PHY_28NM_PLL_REG1);
  138. /* PHY_28NM_TX_REG0 */
  139. reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK;
  140. writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT |
  141. PHY_28NM_TX_PU_ANA,
  142. base + PHY_28NM_TX_REG0);
  143. /* PHY_28NM_RX_REG0 */
  144. reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK;
  145. writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT,
  146. base + PHY_28NM_RX_REG0);
  147. /* PHY_28NM_DIG_REG0 */
  148. reg = readl(base + PHY_28NM_DIG_REG0) &
  149. ~(PHY_28NM_DIG_BITSTAFFING_ERR | PHY_28NM_DIG_SYNC_ERR |
  150. PHY_28NM_DIG_SQ_FILT_MASK | PHY_28NM_DIG_SQ_BLK_MASK |
  151. PHY_28NM_DIG_SYNC_NUM_MASK);
  152. writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT |
  153. PHY_28NM_PLL_LOCK_BYPASS),
  154. base + PHY_28NM_DIG_REG0);
  155. /* PHY_28NM_OTG_REG */
  156. reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG;
  157. writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG);
  158. /*
  159. * Calibration Timing
  160. * ____________________________
  161. * CAL START ___|
  162. * ____________________
  163. * CAL_DONE ___________|
  164. * | 400us |
  165. */
  166. /* Make sure PHY Calibration is ready */
  167. ret = wait_for_reg(base + PHY_28NM_CAL_REG,
  168. PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
  169. 100);
  170. if (ret) {
  171. dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");
  172. goto err_clk;
  173. }
  174. ret = wait_for_reg(base + PHY_28NM_RX_REG1,
  175. PHY_28NM_RX_SQCAL_DONE, 100);
  176. if (ret) {
  177. dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");
  178. goto err_clk;
  179. }
  180. /* Make sure PHY PLL is ready */
  181. ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);
  182. if (ret) {
  183. dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");
  184. goto err_clk;
  185. }
  186. return 0;
  187. err_clk:
  188. clk_disable_unprepare(mv_phy->clk);
  189. return ret;
  190. }
  191. static int mv_usb2_phy_28nm_power_on(struct phy *phy)
  192. {
  193. struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
  194. void __iomem *base = mv_phy->base;
  195. writel(readl(base + PHY_28NM_CTRL_REG3) |
  196. (PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID |
  197. PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
  198. base + PHY_28NM_CTRL_REG3);
  199. return 0;
  200. }
  201. static int mv_usb2_phy_28nm_power_off(struct phy *phy)
  202. {
  203. struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
  204. void __iomem *base = mv_phy->base;
  205. writel(readl(base + PHY_28NM_CTRL_REG3) |
  206. ~(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID
  207. | PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
  208. base + PHY_28NM_CTRL_REG3);
  209. return 0;
  210. }
  211. static int mv_usb2_phy_28nm_exit(struct phy *phy)
  212. {
  213. struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
  214. void __iomem *base = mv_phy->base;
  215. unsigned int val;
  216. val = readw(base + PHY_28NM_PLL_REG1);
  217. val &= ~PHY_28NM_PLL_PU_PLL;
  218. writew(val, base + PHY_28NM_PLL_REG1);
  219. /* power down PHY Analog part */
  220. val = readw(base + PHY_28NM_TX_REG0);
  221. val &= ~PHY_28NM_TX_PU_ANA;
  222. writew(val, base + PHY_28NM_TX_REG0);
  223. /* power down PHY OTG part */
  224. val = readw(base + PHY_28NM_OTG_REG);
  225. val &= ~PHY_28NM_OTG_PU_OTG;
  226. writew(val, base + PHY_28NM_OTG_REG);
  227. clk_disable_unprepare(mv_phy->clk);
  228. return 0;
  229. }
  230. static const struct phy_ops usb_ops = {
  231. .init = mv_usb2_phy_28nm_init,
  232. .power_on = mv_usb2_phy_28nm_power_on,
  233. .power_off = mv_usb2_phy_28nm_power_off,
  234. .exit = mv_usb2_phy_28nm_exit,
  235. .owner = THIS_MODULE,
  236. };
  237. static int mv_usb2_phy_probe(struct platform_device *pdev)
  238. {
  239. struct phy_provider *phy_provider;
  240. struct mv_usb2_phy *mv_phy;
  241. struct resource *r;
  242. mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
  243. if (!mv_phy)
  244. return -ENOMEM;
  245. mv_phy->pdev = pdev;
  246. mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
  247. if (IS_ERR(mv_phy->clk)) {
  248. dev_err(&pdev->dev, "failed to get clock.\n");
  249. return PTR_ERR(mv_phy->clk);
  250. }
  251. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  252. mv_phy->base = devm_ioremap_resource(&pdev->dev, r);
  253. if (IS_ERR(mv_phy->base))
  254. return PTR_ERR(mv_phy->base);
  255. mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &usb_ops);
  256. if (IS_ERR(mv_phy->phy))
  257. return PTR_ERR(mv_phy->phy);
  258. phy_set_drvdata(mv_phy->phy, mv_phy);
  259. phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
  260. return PTR_ERR_OR_ZERO(phy_provider);
  261. }
  262. static const struct of_device_id mv_usbphy_dt_match[] = {
  263. { .compatible = "marvell,pxa1928-usb-phy", },
  264. {},
  265. };
  266. MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match);
  267. static struct platform_driver mv_usb2_phy_driver = {
  268. .probe = mv_usb2_phy_probe,
  269. .driver = {
  270. .name = "mv-usb2-phy",
  271. .of_match_table = of_match_ptr(mv_usbphy_dt_match),
  272. },
  273. };
  274. module_platform_driver(mv_usb2_phy_driver);
  275. MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
  276. MODULE_DESCRIPTION("Marvell USB2 phy driver");
  277. MODULE_LICENSE("GPL v2");