phy-mvebu-cp110-comphy.c 36 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 Marvell
  4. *
  5. * Antoine Tenart <antoine.tenart@free-electrons.com>
  6. */
  7. #include <linux/arm-smccc.h>
  8. #include <linux/clk.h>
  9. #include <linux/io.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <linux/phy.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. /* Relative to priv->base */
  18. #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000)
  19. #define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
  20. #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3)
  21. #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7)
  22. #define MVEBU_COMPHY_SERDES_CFG0_PU_RX BIT(11)
  23. #define MVEBU_COMPHY_SERDES_CFG0_PU_TX BIT(12)
  24. #define MVEBU_COMPHY_SERDES_CFG0_HALF_BUS BIT(14)
  25. #define MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE BIT(15)
  26. #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000)
  27. #define MVEBU_COMPHY_SERDES_CFG1_RESET BIT(3)
  28. #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
  29. #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5)
  30. #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6)
  31. #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000)
  32. #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
  33. #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000)
  34. #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
  35. #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3)
  36. #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
  37. #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000)
  38. #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0)
  39. #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
  40. #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000)
  41. #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10)
  42. #define MVEBU_COMPHY_IMP_CAL_TX_EXT_EN BIT(15)
  43. #define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000)
  44. #define MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL BIT(15)
  45. #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000)
  46. #define MVEBU_COMPHY_COEF_DFE_EN BIT(14)
  47. #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15)
  48. #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000)
  49. #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
  50. #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7)
  51. #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000)
  52. #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0)
  53. #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3)
  54. #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6)
  55. #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8)
  56. #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10)
  57. #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11)
  58. #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000)
  59. #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0)
  60. #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
  61. #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000)
  62. #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
  63. #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000)
  64. #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15)
  65. #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000)
  66. #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
  67. #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000)
  68. #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5)
  69. #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10)
  70. #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000)
  71. #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11)
  72. #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12)
  73. #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000)
  74. #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7)
  75. #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000)
  76. #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8)
  77. #define MVEBU_SP_CALIB_SAMPLER_EN BIT(12)
  78. #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000)
  79. #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
  80. #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10)
  81. #define MVEBU_COMPHY_DTL_CTRL(n) (0x984 + (n) * 0x1000)
  82. #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
  83. #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000)
  84. #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7)
  85. #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000)
  86. #define MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN BIT(12)
  87. #define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000)
  88. #define MVEBU_COMPHY_DME_ETH_MODE BIT(7)
  89. #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000)
  90. #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15)
  91. #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000)
  92. #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0)
  93. #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000)
  94. #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8)
  95. #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9)
  96. #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000)
  97. #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9)
  98. #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000)
  99. #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8)
  100. #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000)
  101. #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0)
  102. #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000)
  103. #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0)
  104. /* Relative to priv->regmap */
  105. #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28)
  106. #define MVEBU_COMPHY_CONF1_PWRUP BIT(1)
  107. #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
  108. #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28)
  109. #define MVEBU_COMPHY_CONF6_40B BIT(18)
  110. #define MVEBU_COMPHY_SELECTOR 0x1140
  111. #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4)
  112. #define MVEBU_COMPHY_PIPE_SELECTOR 0x1144
  113. #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4)
  114. #define MVEBU_COMPHY_SD1_CTRL1 0x1148
  115. #define MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN BIT(26)
  116. #define MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN BIT(27)
  117. #define MVEBU_COMPHY_LANES 6
  118. #define MVEBU_COMPHY_PORTS 3
  119. #define COMPHY_SIP_POWER_ON 0x82000001
  120. #define COMPHY_SIP_POWER_OFF 0x82000002
  121. /*
  122. * A lane is described by the following bitfields:
  123. * [ 1- 0]: COMPHY polarity invertion
  124. * [ 2- 7]: COMPHY speed
  125. * [ 5-11]: COMPHY port index
  126. * [12-16]: COMPHY mode
  127. * [17]: Clock source
  128. * [18-20]: PCIe width (x1, x2, x4)
  129. */
  130. #define COMPHY_FW_POL_OFFSET 0
  131. #define COMPHY_FW_POL_MASK GENMASK(1, 0)
  132. #define COMPHY_FW_SPEED_OFFSET 2
  133. #define COMPHY_FW_SPEED_MASK GENMASK(7, 2)
  134. #define COMPHY_FW_SPEED_MAX COMPHY_FW_SPEED_MASK
  135. #define COMPHY_FW_SPEED_1250 0
  136. #define COMPHY_FW_SPEED_3125 2
  137. #define COMPHY_FW_SPEED_5000 3
  138. #define COMPHY_FW_SPEED_103125 6
  139. #define COMPHY_FW_PORT_OFFSET 8
  140. #define COMPHY_FW_PORT_MASK GENMASK(11, 8)
  141. #define COMPHY_FW_MODE_OFFSET 12
  142. #define COMPHY_FW_MODE_MASK GENMASK(16, 12)
  143. #define COMPHY_FW_WIDTH_OFFSET 18
  144. #define COMPHY_FW_WIDTH_MASK GENMASK(20, 18)
  145. #define COMPHY_FW_PARAM_FULL(mode, port, speed, pol, width) \
  146. ((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
  147. (((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
  148. (((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
  149. (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK) | \
  150. (((width) << COMPHY_FW_WIDTH_OFFSET) & COMPHY_FW_WIDTH_MASK))
  151. #define COMPHY_FW_PARAM(mode, port) \
  152. COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_MAX, 0, 0)
  153. #define COMPHY_FW_PARAM_ETH(mode, port, speed) \
  154. COMPHY_FW_PARAM_FULL(mode, port, speed, 0, 0)
  155. #define COMPHY_FW_PARAM_PCIE(mode, port, width) \
  156. COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_5000, 0, width)
  157. #define COMPHY_FW_MODE_SATA 0x1
  158. #define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
  159. #define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
  160. #define COMPHY_FW_MODE_USB3H 0x4
  161. #define COMPHY_FW_MODE_USB3D 0x5
  162. #define COMPHY_FW_MODE_PCIE 0x6
  163. #define COMPHY_FW_MODE_RXAUI 0x7
  164. #define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
  165. struct mvebu_comphy_conf {
  166. enum phy_mode mode;
  167. int submode;
  168. unsigned lane;
  169. unsigned port;
  170. u32 mux;
  171. u32 fw_mode;
  172. };
  173. #define ETH_CONF(_lane, _port, _submode, _mux, _fw) \
  174. { \
  175. .lane = _lane, \
  176. .port = _port, \
  177. .mode = PHY_MODE_ETHERNET, \
  178. .submode = _submode, \
  179. .mux = _mux, \
  180. .fw_mode = _fw, \
  181. }
  182. #define GEN_CONF(_lane, _port, _mode, _fw) \
  183. { \
  184. .lane = _lane, \
  185. .port = _port, \
  186. .mode = _mode, \
  187. .submode = PHY_INTERFACE_MODE_NA, \
  188. .mux = -1, \
  189. .fw_mode = _fw, \
  190. }
  191. static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
  192. /* lane 0 */
  193. GEN_CONF(0, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
  194. ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
  195. ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
  196. GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
  197. /* lane 1 */
  198. GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
  199. GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
  200. GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
  201. GEN_CONF(1, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
  202. ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
  203. ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
  204. /* lane 2 */
  205. ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
  206. ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
  207. ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
  208. ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
  209. GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
  210. GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
  211. GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
  212. /* lane 3 */
  213. GEN_CONF(3, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
  214. ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
  215. ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
  216. ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
  217. GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
  218. GEN_CONF(3, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
  219. /* lane 4 */
  220. ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
  221. ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
  222. ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),
  223. ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
  224. GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
  225. GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
  226. GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
  227. ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
  228. ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
  229. ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
  230. /* lane 5 */
  231. ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
  232. GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
  233. ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
  234. ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
  235. GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
  236. };
  237. struct mvebu_comphy_priv {
  238. void __iomem *base;
  239. struct regmap *regmap;
  240. struct device *dev;
  241. struct clk *mg_domain_clk;
  242. struct clk *mg_core_clk;
  243. struct clk *axi_clk;
  244. unsigned long cp_phys;
  245. };
  246. struct mvebu_comphy_lane {
  247. struct mvebu_comphy_priv *priv;
  248. unsigned id;
  249. enum phy_mode mode;
  250. int submode;
  251. int port;
  252. };
  253. static int mvebu_comphy_smc(unsigned long function, unsigned long phys,
  254. unsigned long lane, unsigned long mode)
  255. {
  256. struct arm_smccc_res res;
  257. s32 ret;
  258. arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
  259. ret = res.a0;
  260. switch (ret) {
  261. case SMCCC_RET_SUCCESS:
  262. return 0;
  263. case SMCCC_RET_NOT_SUPPORTED:
  264. return -EOPNOTSUPP;
  265. default:
  266. return -EINVAL;
  267. }
  268. }
  269. static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
  270. enum phy_mode mode, int submode)
  271. {
  272. int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
  273. /* Ignore PCIe submode: it represents the width */
  274. bool ignore_submode = (mode == PHY_MODE_PCIE);
  275. const struct mvebu_comphy_conf *conf;
  276. /* Unused PHY mux value is 0x0 */
  277. if (mode == PHY_MODE_INVALID)
  278. return 0;
  279. for (i = 0; i < n; i++) {
  280. conf = &mvebu_comphy_cp110_modes[i];
  281. if (conf->lane == lane &&
  282. conf->port == port &&
  283. conf->mode == mode &&
  284. (conf->submode == submode || ignore_submode))
  285. break;
  286. }
  287. if (i == n)
  288. return -EINVAL;
  289. if (fw_mode)
  290. return conf->fw_mode;
  291. else
  292. return conf->mux;
  293. }
  294. static inline int mvebu_comphy_get_mux(int lane, int port,
  295. enum phy_mode mode, int submode)
  296. {
  297. return mvebu_comphy_get_mode(false, lane, port, mode, submode);
  298. }
  299. static inline int mvebu_comphy_get_fw_mode(int lane, int port,
  300. enum phy_mode mode, int submode)
  301. {
  302. return mvebu_comphy_get_mode(true, lane, port, mode, submode);
  303. }
  304. static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
  305. {
  306. struct mvebu_comphy_priv *priv = lane->priv;
  307. u32 val;
  308. regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
  309. val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
  310. val |= MVEBU_COMPHY_CONF1_PWRUP;
  311. regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
  312. /* Select baud rates and PLLs */
  313. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
  314. val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL |
  315. MVEBU_COMPHY_SERDES_CFG0_PU_RX |
  316. MVEBU_COMPHY_SERDES_CFG0_PU_TX |
  317. MVEBU_COMPHY_SERDES_CFG0_HALF_BUS |
  318. MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) |
  319. MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf) |
  320. MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE);
  321. switch (lane->submode) {
  322. case PHY_INTERFACE_MODE_10GBASER:
  323. val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
  324. MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
  325. break;
  326. case PHY_INTERFACE_MODE_RXAUI:
  327. val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xb) |
  328. MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xb) |
  329. MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE;
  330. break;
  331. case PHY_INTERFACE_MODE_2500BASEX:
  332. val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
  333. MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) |
  334. MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
  335. break;
  336. case PHY_INTERFACE_MODE_SGMII:
  337. val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
  338. MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
  339. MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
  340. break;
  341. default:
  342. dev_err(priv->dev,
  343. "unsupported comphy submode (%d) on lane %d\n",
  344. lane->submode,
  345. lane->id);
  346. return -ENOTSUPP;
  347. }
  348. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
  349. if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {
  350. regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val);
  351. switch (lane->id) {
  352. case 2:
  353. case 3:
  354. val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN;
  355. break;
  356. case 4:
  357. case 5:
  358. val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN;
  359. break;
  360. default:
  361. dev_err(priv->dev,
  362. "RXAUI is not supported on comphy lane %d\n",
  363. lane->id);
  364. return -EINVAL;
  365. }
  366. regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val);
  367. }
  368. /* reset */
  369. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  370. val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
  371. MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
  372. MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
  373. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  374. /* de-assert reset */
  375. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  376. val |= MVEBU_COMPHY_SERDES_CFG1_RESET |
  377. MVEBU_COMPHY_SERDES_CFG1_CORE_RESET;
  378. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  379. /* wait until clocks are ready */
  380. mdelay(1);
  381. /* exlicitly disable 40B, the bits isn't clear on reset */
  382. regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);
  383. val &= ~MVEBU_COMPHY_CONF6_40B;
  384. regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);
  385. /* refclk selection */
  386. val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
  387. val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL;
  388. if (lane->submode == PHY_INTERFACE_MODE_10GBASER)
  389. val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE;
  390. writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
  391. /* power and pll selection */
  392. val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
  393. val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) |
  394. MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7));
  395. val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) |
  396. MVEBU_COMPHY_PWRPLL_PHY_MODE(0x4);
  397. writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
  398. val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
  399. val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7);
  400. val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1);
  401. writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
  402. return 0;
  403. }
  404. static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)
  405. {
  406. struct mvebu_comphy_priv *priv = lane->priv;
  407. u32 val;
  408. /* SERDES external config */
  409. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
  410. val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL |
  411. MVEBU_COMPHY_SERDES_CFG0_PU_RX |
  412. MVEBU_COMPHY_SERDES_CFG0_PU_TX;
  413. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
  414. /* check rx/tx pll */
  415. readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
  416. val,
  417. val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY |
  418. MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY),
  419. 1000, 150000);
  420. if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY |
  421. MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY)))
  422. return -ETIMEDOUT;
  423. /* rx init */
  424. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  425. val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT;
  426. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  427. /* check rx */
  428. readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
  429. val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT,
  430. 1000, 10000);
  431. if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT))
  432. return -ETIMEDOUT;
  433. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  434. val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT;
  435. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  436. return 0;
  437. }
  438. static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
  439. {
  440. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  441. struct mvebu_comphy_priv *priv = lane->priv;
  442. u32 val;
  443. int err;
  444. err = mvebu_comphy_ethernet_init_reset(lane);
  445. if (err)
  446. return err;
  447. val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
  448. val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
  449. val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL;
  450. writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
  451. val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
  452. val &= ~MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
  453. writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
  454. regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
  455. val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
  456. val |= MVEBU_COMPHY_CONF1_PWRUP;
  457. regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
  458. val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
  459. val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
  460. val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1);
  461. writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
  462. return mvebu_comphy_init_plls(lane);
  463. }
  464. static int mvebu_comphy_set_mode_rxaui(struct phy *phy)
  465. {
  466. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  467. struct mvebu_comphy_priv *priv = lane->priv;
  468. u32 val;
  469. int err;
  470. err = mvebu_comphy_ethernet_init_reset(lane);
  471. if (err)
  472. return err;
  473. val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
  474. val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
  475. MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
  476. writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
  477. val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
  478. val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
  479. writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
  480. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
  481. val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN;
  482. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
  483. val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
  484. val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL;
  485. writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
  486. val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
  487. val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
  488. val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xd);
  489. writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
  490. val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
  491. val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
  492. MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7));
  493. val |= MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x1) |
  494. MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x1) |
  495. MVEBU_COMPHY_GEN1_S1_RX_DFE_EN;
  496. writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
  497. val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
  498. val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL);
  499. writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
  500. val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
  501. val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
  502. val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
  503. writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
  504. return mvebu_comphy_init_plls(lane);
  505. }
  506. static int mvebu_comphy_set_mode_10gbaser(struct phy *phy)
  507. {
  508. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  509. struct mvebu_comphy_priv *priv = lane->priv;
  510. u32 val;
  511. int err;
  512. err = mvebu_comphy_ethernet_init_reset(lane);
  513. if (err)
  514. return err;
  515. val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
  516. val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
  517. MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
  518. writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
  519. val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
  520. val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
  521. writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
  522. /* Speed divider */
  523. val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
  524. val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE;
  525. writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
  526. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
  527. val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN;
  528. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
  529. /* DFE resolution */
  530. val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
  531. val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL;
  532. writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
  533. val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
  534. val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) |
  535. MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf));
  536. val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) |
  537. MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe);
  538. writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
  539. val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
  540. val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf);
  541. val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN;
  542. writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
  543. val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
  544. val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) |
  545. MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f);
  546. writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
  547. /* Impedance calibration */
  548. val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
  549. val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f);
  550. val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) |
  551. MVEBU_COMPHY_IMP_CAL_TX_EXT_EN;
  552. writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
  553. val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
  554. val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf);
  555. writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
  556. val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
  557. val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
  558. MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) |
  559. MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) |
  560. MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3));
  561. val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN |
  562. MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x2) |
  563. MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x2) |
  564. MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x1) |
  565. MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3);
  566. writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
  567. val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
  568. val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL);
  569. writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
  570. val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
  571. val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
  572. val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
  573. writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
  574. val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
  575. val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL;
  576. writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
  577. /* rx training timer */
  578. val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
  579. val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff);
  580. val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13);
  581. writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
  582. /* tx train peak to peak hold */
  583. val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
  584. val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD;
  585. writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
  586. val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
  587. val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf);
  588. val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2); /* preset coeff */
  589. writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
  590. val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
  591. val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN;
  592. writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
  593. val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
  594. val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN |
  595. MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11;
  596. writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
  597. val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
  598. val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff);
  599. val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88);
  600. writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
  601. val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));
  602. val |= MVEBU_COMPHY_DME_ETH_MODE;
  603. writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));
  604. val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
  605. val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE;
  606. writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
  607. val = readl(priv->base + MVEBU_SP_CALIB(lane->id));
  608. val &= ~MVEBU_SP_CALIB_SAMPLER(0x3);
  609. val |= MVEBU_SP_CALIB_SAMPLER(0x3) |
  610. MVEBU_SP_CALIB_SAMPLER_EN;
  611. writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
  612. val &= ~MVEBU_SP_CALIB_SAMPLER_EN;
  613. writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
  614. /* External rx regulator */
  615. val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
  616. val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f);
  617. val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a);
  618. writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
  619. return mvebu_comphy_init_plls(lane);
  620. }
  621. static int mvebu_comphy_power_on_legacy(struct phy *phy)
  622. {
  623. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  624. struct mvebu_comphy_priv *priv = lane->priv;
  625. int ret, mux;
  626. u32 val;
  627. mux = mvebu_comphy_get_mux(lane->id, lane->port,
  628. lane->mode, lane->submode);
  629. if (mux < 0)
  630. return -ENOTSUPP;
  631. regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
  632. val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
  633. regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
  634. regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
  635. val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
  636. val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);
  637. regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
  638. switch (lane->submode) {
  639. case PHY_INTERFACE_MODE_SGMII:
  640. case PHY_INTERFACE_MODE_2500BASEX:
  641. ret = mvebu_comphy_set_mode_sgmii(phy);
  642. break;
  643. case PHY_INTERFACE_MODE_RXAUI:
  644. ret = mvebu_comphy_set_mode_rxaui(phy);
  645. break;
  646. case PHY_INTERFACE_MODE_10GBASER:
  647. ret = mvebu_comphy_set_mode_10gbaser(phy);
  648. break;
  649. default:
  650. return -ENOTSUPP;
  651. }
  652. /* digital reset */
  653. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  654. val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET;
  655. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  656. return ret;
  657. }
  658. static int mvebu_comphy_power_on(struct phy *phy)
  659. {
  660. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  661. struct mvebu_comphy_priv *priv = lane->priv;
  662. int fw_mode, fw_speed;
  663. u32 fw_param = 0;
  664. int ret;
  665. fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
  666. lane->mode, lane->submode);
  667. if (fw_mode < 0)
  668. goto try_legacy;
  669. /* Try SMC flow first */
  670. switch (lane->mode) {
  671. case PHY_MODE_ETHERNET:
  672. switch (lane->submode) {
  673. case PHY_INTERFACE_MODE_RXAUI:
  674. dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
  675. lane->id);
  676. fw_speed = 0;
  677. break;
  678. case PHY_INTERFACE_MODE_SGMII:
  679. dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
  680. lane->id);
  681. fw_speed = COMPHY_FW_SPEED_1250;
  682. break;
  683. case PHY_INTERFACE_MODE_2500BASEX:
  684. dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
  685. lane->id);
  686. fw_speed = COMPHY_FW_SPEED_3125;
  687. break;
  688. case PHY_INTERFACE_MODE_10GBASER:
  689. dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
  690. lane->id);
  691. fw_speed = COMPHY_FW_SPEED_103125;
  692. break;
  693. default:
  694. dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",
  695. lane->submode);
  696. return -ENOTSUPP;
  697. }
  698. fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
  699. break;
  700. case PHY_MODE_USB_HOST_SS:
  701. case PHY_MODE_USB_DEVICE_SS:
  702. dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
  703. fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
  704. break;
  705. case PHY_MODE_SATA:
  706. dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
  707. fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
  708. break;
  709. case PHY_MODE_PCIE:
  710. dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
  711. lane->submode);
  712. fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,
  713. lane->submode);
  714. break;
  715. default:
  716. dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
  717. return -ENOTSUPP;
  718. }
  719. ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
  720. fw_param);
  721. if (!ret)
  722. return ret;
  723. if (ret == -EOPNOTSUPP)
  724. dev_err(priv->dev,
  725. "unsupported SMC call, try updating your firmware\n");
  726. dev_warn(priv->dev,
  727. "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
  728. lane->id, lane->mode, ret);
  729. try_legacy:
  730. /* Fallback to Linux's implementation */
  731. return mvebu_comphy_power_on_legacy(phy);
  732. }
  733. static int mvebu_comphy_set_mode(struct phy *phy,
  734. enum phy_mode mode, int submode)
  735. {
  736. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  737. if (submode == PHY_INTERFACE_MODE_1000BASEX)
  738. submode = PHY_INTERFACE_MODE_SGMII;
  739. if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
  740. return -EINVAL;
  741. lane->mode = mode;
  742. lane->submode = submode;
  743. /* PCIe submode represents the width */
  744. if (mode == PHY_MODE_PCIE && !lane->submode)
  745. lane->submode = 1;
  746. return 0;
  747. }
  748. static int mvebu_comphy_power_off_legacy(struct phy *phy)
  749. {
  750. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  751. struct mvebu_comphy_priv *priv = lane->priv;
  752. u32 val;
  753. val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  754. val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
  755. MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
  756. MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
  757. writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
  758. regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
  759. val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
  760. regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
  761. regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
  762. val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
  763. regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
  764. return 0;
  765. }
  766. static int mvebu_comphy_power_off(struct phy *phy)
  767. {
  768. struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
  769. struct mvebu_comphy_priv *priv = lane->priv;
  770. int ret;
  771. ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,
  772. lane->id, 0);
  773. if (!ret)
  774. return ret;
  775. /* Fallback to Linux's implementation */
  776. return mvebu_comphy_power_off_legacy(phy);
  777. }
  778. static const struct phy_ops mvebu_comphy_ops = {
  779. .power_on = mvebu_comphy_power_on,
  780. .power_off = mvebu_comphy_power_off,
  781. .set_mode = mvebu_comphy_set_mode,
  782. .owner = THIS_MODULE,
  783. };
  784. static struct phy *mvebu_comphy_xlate(struct device *dev,
  785. struct of_phandle_args *args)
  786. {
  787. struct mvebu_comphy_lane *lane;
  788. struct phy *phy;
  789. if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS))
  790. return ERR_PTR(-EINVAL);
  791. phy = of_phy_simple_xlate(dev, args);
  792. if (IS_ERR(phy))
  793. return phy;
  794. lane = phy_get_drvdata(phy);
  795. lane->port = args->args[0];
  796. return phy;
  797. }
  798. static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv)
  799. {
  800. int ret;
  801. priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");
  802. if (IS_ERR(priv->mg_domain_clk))
  803. return PTR_ERR(priv->mg_domain_clk);
  804. ret = clk_prepare_enable(priv->mg_domain_clk);
  805. if (ret < 0)
  806. return ret;
  807. priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");
  808. if (IS_ERR(priv->mg_core_clk)) {
  809. ret = PTR_ERR(priv->mg_core_clk);
  810. goto dis_mg_domain_clk;
  811. }
  812. ret = clk_prepare_enable(priv->mg_core_clk);
  813. if (ret < 0)
  814. goto dis_mg_domain_clk;
  815. priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");
  816. if (IS_ERR(priv->axi_clk)) {
  817. ret = PTR_ERR(priv->axi_clk);
  818. goto dis_mg_core_clk;
  819. }
  820. ret = clk_prepare_enable(priv->axi_clk);
  821. if (ret < 0)
  822. goto dis_mg_core_clk;
  823. return 0;
  824. dis_mg_core_clk:
  825. clk_disable_unprepare(priv->mg_core_clk);
  826. dis_mg_domain_clk:
  827. clk_disable_unprepare(priv->mg_domain_clk);
  828. priv->mg_domain_clk = NULL;
  829. priv->mg_core_clk = NULL;
  830. priv->axi_clk = NULL;
  831. return ret;
  832. };
  833. static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv *priv)
  834. {
  835. if (priv->axi_clk)
  836. clk_disable_unprepare(priv->axi_clk);
  837. if (priv->mg_core_clk)
  838. clk_disable_unprepare(priv->mg_core_clk);
  839. if (priv->mg_domain_clk)
  840. clk_disable_unprepare(priv->mg_domain_clk);
  841. }
  842. static int mvebu_comphy_probe(struct platform_device *pdev)
  843. {
  844. struct mvebu_comphy_priv *priv;
  845. struct phy_provider *provider;
  846. struct device_node *child;
  847. struct resource *res;
  848. int ret;
  849. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  850. if (!priv)
  851. return -ENOMEM;
  852. priv->dev = &pdev->dev;
  853. priv->regmap =
  854. syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  855. "marvell,system-controller");
  856. if (IS_ERR(priv->regmap))
  857. return PTR_ERR(priv->regmap);
  858. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  859. priv->base = devm_ioremap_resource(&pdev->dev, res);
  860. if (IS_ERR(priv->base))
  861. return PTR_ERR(priv->base);
  862. /*
  863. * Ignore error if clocks have not been initialized properly for DT
  864. * compatibility reasons.
  865. */
  866. ret = mvebu_comphy_init_clks(priv);
  867. if (ret) {
  868. if (ret == -EPROBE_DEFER)
  869. return ret;
  870. dev_warn(&pdev->dev, "cannot initialize clocks\n");
  871. }
  872. /*
  873. * Hack to retrieve a physical offset relative to this CP that will be
  874. * given to the firmware
  875. */
  876. priv->cp_phys = res->start;
  877. for_each_available_child_of_node(pdev->dev.of_node, child) {
  878. struct mvebu_comphy_lane *lane;
  879. struct phy *phy;
  880. u32 val;
  881. ret = of_property_read_u32(child, "reg", &val);
  882. if (ret < 0) {
  883. dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
  884. ret);
  885. continue;
  886. }
  887. if (val >= MVEBU_COMPHY_LANES) {
  888. dev_err(&pdev->dev, "invalid 'reg' property\n");
  889. continue;
  890. }
  891. lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
  892. if (!lane) {
  893. of_node_put(child);
  894. ret = -ENOMEM;
  895. goto disable_clks;
  896. }
  897. phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);
  898. if (IS_ERR(phy)) {
  899. of_node_put(child);
  900. ret = PTR_ERR(phy);
  901. goto disable_clks;
  902. }
  903. lane->priv = priv;
  904. lane->mode = PHY_MODE_INVALID;
  905. lane->submode = PHY_INTERFACE_MODE_NA;
  906. lane->id = val;
  907. lane->port = -1;
  908. phy_set_drvdata(phy, lane);
  909. /*
  910. * All modes are supported in this driver so we could call
  911. * mvebu_comphy_power_off(phy) here to avoid relying on the
  912. * bootloader/firmware configuration, but for compatibility
  913. * reasons we cannot de-configure the COMPHY without being sure
  914. * that the firmware is up-to-date and fully-featured.
  915. */
  916. }
  917. dev_set_drvdata(&pdev->dev, priv);
  918. provider = devm_of_phy_provider_register(&pdev->dev,
  919. mvebu_comphy_xlate);
  920. return PTR_ERR_OR_ZERO(provider);
  921. disable_clks:
  922. mvebu_comphy_disable_unprepare_clks(priv);
  923. return ret;
  924. }
  925. static const struct of_device_id mvebu_comphy_of_match_table[] = {
  926. { .compatible = "marvell,comphy-cp110" },
  927. { },
  928. };
  929. MODULE_DEVICE_TABLE(of, mvebu_comphy_of_match_table);
  930. static struct platform_driver mvebu_comphy_driver = {
  931. .probe = mvebu_comphy_probe,
  932. .driver = {
  933. .name = "mvebu-comphy",
  934. .of_match_table = mvebu_comphy_of_match_table,
  935. },
  936. };
  937. module_platform_driver(mvebu_comphy_driver);
  938. MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
  939. MODULE_DESCRIPTION("Common PHY driver for mvebu SoCs");
  940. MODULE_LICENSE("GPL v2");