phy-mvebu-a3700-utmi.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell
  4. *
  5. * Authors:
  6. * Igal Liberman <igall@marvell.com>
  7. * Miquèl Raynal <miquel.raynal@bootlin.com>
  8. *
  9. * Marvell A3700 UTMI PHY driver
  10. */
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regmap.h>
  19. /* Armada 3700 UTMI PHY registers */
  20. #define USB2_PHY_PLL_CTRL_REG0 0x0
  21. #define PLL_REF_DIV_OFF 0
  22. #define PLL_REF_DIV_MASK GENMASK(6, 0)
  23. #define PLL_REF_DIV_5 5
  24. #define PLL_FB_DIV_OFF 16
  25. #define PLL_FB_DIV_MASK GENMASK(24, 16)
  26. #define PLL_FB_DIV_96 96
  27. #define PLL_SEL_LPFR_OFF 28
  28. #define PLL_SEL_LPFR_MASK GENMASK(29, 28)
  29. #define PLL_READY BIT(31)
  30. #define USB2_PHY_CAL_CTRL 0x8
  31. #define PHY_PLLCAL_DONE BIT(31)
  32. #define PHY_IMPCAL_DONE BIT(23)
  33. #define USB2_RX_CHAN_CTRL1 0x18
  34. #define USB2PHY_SQCAL_DONE BIT(31)
  35. #define USB2_PHY_OTG_CTRL 0x34
  36. #define PHY_PU_OTG BIT(4)
  37. #define USB2_PHY_CHRGR_DETECT 0x38
  38. #define PHY_CDP_EN BIT(2)
  39. #define PHY_DCP_EN BIT(3)
  40. #define PHY_PD_EN BIT(4)
  41. #define PHY_PU_CHRG_DTC BIT(5)
  42. #define PHY_CDP_DM_AUTO BIT(7)
  43. #define PHY_ENSWITCH_DP BIT(12)
  44. #define PHY_ENSWITCH_DM BIT(13)
  45. /* Armada 3700 USB miscellaneous registers */
  46. #define USB2_PHY_CTRL(usb32) (usb32 ? 0x20 : 0x4)
  47. #define RB_USB2PHY_PU BIT(0)
  48. #define USB2_DP_PULLDN_DEV_MODE BIT(5)
  49. #define USB2_DM_PULLDN_DEV_MODE BIT(6)
  50. #define RB_USB2PHY_SUSPM(usb32) (usb32 ? BIT(14) : BIT(7))
  51. #define PLL_LOCK_DELAY_US 10000
  52. #define PLL_LOCK_TIMEOUT_US 1000000
  53. /**
  54. * struct mvebu_a3700_utmi_caps - PHY capabilities
  55. *
  56. * @usb32: Flag indicating which PHY is in use (impacts the register map):
  57. * - The UTMI PHY wired to the USB3/USB2 controller (otg)
  58. * - The UTMI PHY wired to the USB2 controller (host only)
  59. * @ops: PHY operations
  60. */
  61. struct mvebu_a3700_utmi_caps {
  62. int usb32;
  63. const struct phy_ops *ops;
  64. };
  65. /**
  66. * struct mvebu_a3700_utmi - PHY driver data
  67. *
  68. * @regs: PHY registers
  69. * @usb_misc: Regmap with USB miscellaneous registers including PHY ones
  70. * @caps: PHY capabilities
  71. * @phy: PHY handle
  72. */
  73. struct mvebu_a3700_utmi {
  74. void __iomem *regs;
  75. struct regmap *usb_misc;
  76. const struct mvebu_a3700_utmi_caps *caps;
  77. struct phy *phy;
  78. };
  79. static int mvebu_a3700_utmi_phy_power_on(struct phy *phy)
  80. {
  81. struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
  82. struct device *dev = &phy->dev;
  83. int usb32 = utmi->caps->usb32;
  84. int ret = 0;
  85. u32 reg;
  86. /*
  87. * Setup PLL. 40MHz clock used to be the default, being 25MHz now.
  88. * See "PLL Settings for Typical REFCLK" table.
  89. */
  90. reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0);
  91. reg &= ~(PLL_REF_DIV_MASK | PLL_FB_DIV_MASK | PLL_SEL_LPFR_MASK);
  92. reg |= (PLL_REF_DIV_5 << PLL_REF_DIV_OFF) |
  93. (PLL_FB_DIV_96 << PLL_FB_DIV_OFF);
  94. writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0);
  95. /* Enable PHY pull up and disable USB2 suspend */
  96. regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),
  97. RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU,
  98. RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU);
  99. if (usb32) {
  100. /* Power up OTG module */
  101. reg = readl(utmi->regs + USB2_PHY_OTG_CTRL);
  102. reg |= PHY_PU_OTG;
  103. writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
  104. /* Disable PHY charger detection */
  105. reg = readl(utmi->regs + USB2_PHY_CHRGR_DETECT);
  106. reg &= ~(PHY_CDP_EN | PHY_DCP_EN | PHY_PD_EN | PHY_PU_CHRG_DTC |
  107. PHY_CDP_DM_AUTO | PHY_ENSWITCH_DP | PHY_ENSWITCH_DM);
  108. writel(reg, utmi->regs + USB2_PHY_CHRGR_DETECT);
  109. /* Disable PHY DP/DM pull-down (used for device mode) */
  110. regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),
  111. USB2_DP_PULLDN_DEV_MODE |
  112. USB2_DM_PULLDN_DEV_MODE, 0);
  113. }
  114. /* Wait for PLL calibration */
  115. ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg,
  116. reg & PHY_PLLCAL_DONE,
  117. PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
  118. if (ret) {
  119. dev_err(dev, "Failed to end USB2 PLL calibration\n");
  120. return ret;
  121. }
  122. /* Wait for impedance calibration */
  123. ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg,
  124. reg & PHY_IMPCAL_DONE,
  125. PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
  126. if (ret) {
  127. dev_err(dev, "Failed to end USB2 impedance calibration\n");
  128. return ret;
  129. }
  130. /* Wait for squelch calibration */
  131. ret = readl_poll_timeout(utmi->regs + USB2_RX_CHAN_CTRL1, reg,
  132. reg & USB2PHY_SQCAL_DONE,
  133. PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
  134. if (ret) {
  135. dev_err(dev, "Failed to end USB2 unknown calibration\n");
  136. return ret;
  137. }
  138. /* Wait for PLL to be locked */
  139. ret = readl_poll_timeout(utmi->regs + USB2_PHY_PLL_CTRL_REG0, reg,
  140. reg & PLL_READY,
  141. PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
  142. if (ret)
  143. dev_err(dev, "Failed to lock USB2 PLL\n");
  144. return ret;
  145. }
  146. static int mvebu_a3700_utmi_phy_power_off(struct phy *phy)
  147. {
  148. struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
  149. int usb32 = utmi->caps->usb32;
  150. u32 reg;
  151. /* Disable PHY pull-up and enable USB2 suspend */
  152. reg = readl(utmi->regs + USB2_PHY_CTRL(usb32));
  153. reg &= ~(RB_USB2PHY_PU | RB_USB2PHY_SUSPM(usb32));
  154. writel(reg, utmi->regs + USB2_PHY_CTRL(usb32));
  155. /* Power down OTG module */
  156. if (usb32) {
  157. reg = readl(utmi->regs + USB2_PHY_OTG_CTRL);
  158. reg &= ~PHY_PU_OTG;
  159. writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
  160. }
  161. return 0;
  162. }
  163. static const struct phy_ops mvebu_a3700_utmi_phy_ops = {
  164. .power_on = mvebu_a3700_utmi_phy_power_on,
  165. .power_off = mvebu_a3700_utmi_phy_power_off,
  166. .owner = THIS_MODULE,
  167. };
  168. static const struct mvebu_a3700_utmi_caps mvebu_a3700_utmi_otg_phy_caps = {
  169. .usb32 = true,
  170. .ops = &mvebu_a3700_utmi_phy_ops,
  171. };
  172. static const struct mvebu_a3700_utmi_caps mvebu_a3700_utmi_host_phy_caps = {
  173. .usb32 = false,
  174. .ops = &mvebu_a3700_utmi_phy_ops,
  175. };
  176. static const struct of_device_id mvebu_a3700_utmi_of_match[] = {
  177. {
  178. .compatible = "marvell,a3700-utmi-otg-phy",
  179. .data = &mvebu_a3700_utmi_otg_phy_caps,
  180. },
  181. {
  182. .compatible = "marvell,a3700-utmi-host-phy",
  183. .data = &mvebu_a3700_utmi_host_phy_caps,
  184. },
  185. {},
  186. };
  187. MODULE_DEVICE_TABLE(of, mvebu_a3700_utmi_of_match);
  188. static int mvebu_a3700_utmi_phy_probe(struct platform_device *pdev)
  189. {
  190. struct device *dev = &pdev->dev;
  191. struct mvebu_a3700_utmi *utmi;
  192. struct phy_provider *provider;
  193. utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
  194. if (!utmi)
  195. return -ENOMEM;
  196. /* Get UTMI memory region */
  197. utmi->regs = devm_platform_ioremap_resource(pdev, 0);
  198. if (IS_ERR(utmi->regs))
  199. return PTR_ERR(utmi->regs);
  200. /* Get miscellaneous Host/PHY region */
  201. utmi->usb_misc = syscon_regmap_lookup_by_phandle(dev->of_node,
  202. "marvell,usb-misc-reg");
  203. if (IS_ERR(utmi->usb_misc)) {
  204. dev_err(dev,
  205. "Missing USB misc purpose system controller\n");
  206. return PTR_ERR(utmi->usb_misc);
  207. }
  208. /* Retrieve PHY capabilities */
  209. utmi->caps = of_device_get_match_data(dev);
  210. /* Instantiate the PHY */
  211. utmi->phy = devm_phy_create(dev, NULL, utmi->caps->ops);
  212. if (IS_ERR(utmi->phy)) {
  213. dev_err(dev, "Failed to create the UTMI PHY\n");
  214. return PTR_ERR(utmi->phy);
  215. }
  216. phy_set_drvdata(utmi->phy, utmi);
  217. /* Ensure the PHY is powered off */
  218. utmi->caps->ops->power_off(utmi->phy);
  219. provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  220. return PTR_ERR_OR_ZERO(provider);
  221. }
  222. static struct platform_driver mvebu_a3700_utmi_driver = {
  223. .probe = mvebu_a3700_utmi_phy_probe,
  224. .driver = {
  225. .name = "mvebu-a3700-utmi-phy",
  226. .of_match_table = mvebu_a3700_utmi_of_match,
  227. },
  228. };
  229. module_platform_driver(mvebu_a3700_utmi_driver);
  230. MODULE_AUTHOR("Igal Liberman <igall@marvell.com>");
  231. MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
  232. MODULE_DESCRIPTION("Marvell EBU A3700 UTMI PHY driver");
  233. MODULE_LICENSE("GPL v2");