phy-berlin-usb.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2014 Marvell Technology Group Ltd.
  4. *
  5. * Antoine Tenart <antoine.tenart@free-electrons.com>
  6. * Jisheng Zhang <jszhang@marvell.com>
  7. */
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/phy/phy.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/reset.h>
  14. #define USB_PHY_PLL 0x04
  15. #define USB_PHY_PLL_CONTROL 0x08
  16. #define USB_PHY_TX_CTRL0 0x10
  17. #define USB_PHY_TX_CTRL1 0x14
  18. #define USB_PHY_TX_CTRL2 0x18
  19. #define USB_PHY_RX_CTRL 0x20
  20. #define USB_PHY_ANALOG 0x34
  21. /* USB_PHY_PLL */
  22. #define CLK_REF_DIV(x) ((x) << 4)
  23. #define FEEDBACK_CLK_DIV(x) ((x) << 8)
  24. /* USB_PHY_PLL_CONTROL */
  25. #define CLK_STABLE BIT(0)
  26. #define PLL_CTRL_PIN BIT(1)
  27. #define PLL_CTRL_REG BIT(2)
  28. #define PLL_ON BIT(3)
  29. #define PHASE_OFF_TOL_125 (0x0 << 5)
  30. #define PHASE_OFF_TOL_250 BIT(5)
  31. #define KVC0_CALIB (0x0 << 9)
  32. #define KVC0_REG_CTRL BIT(9)
  33. #define KVC0_HIGH (0x0 << 10)
  34. #define KVC0_LOW (0x3 << 10)
  35. #define CLK_BLK_EN BIT(13)
  36. /* USB_PHY_TX_CTRL0 */
  37. #define EXT_HS_RCAL_EN BIT(3)
  38. #define EXT_FS_RCAL_EN BIT(4)
  39. #define IMPCAL_VTH_DIV(x) ((x) << 5)
  40. #define EXT_RS_RCAL_DIV(x) ((x) << 8)
  41. #define EXT_FS_RCAL_DIV(x) ((x) << 12)
  42. /* USB_PHY_TX_CTRL1 */
  43. #define TX_VDD15_14 (0x0 << 4)
  44. #define TX_VDD15_15 BIT(4)
  45. #define TX_VDD15_16 (0x2 << 4)
  46. #define TX_VDD15_17 (0x3 << 4)
  47. #define TX_VDD12_VDD (0x0 << 6)
  48. #define TX_VDD12_11 BIT(6)
  49. #define TX_VDD12_12 (0x2 << 6)
  50. #define TX_VDD12_13 (0x3 << 6)
  51. #define LOW_VDD_EN BIT(8)
  52. #define TX_OUT_AMP(x) ((x) << 9)
  53. /* USB_PHY_TX_CTRL2 */
  54. #define TX_CHAN_CTRL_REG(x) ((x) << 0)
  55. #define DRV_SLEWRATE(x) ((x) << 4)
  56. #define IMP_CAL_FS_HS_DLY_0 (0x0 << 6)
  57. #define IMP_CAL_FS_HS_DLY_1 BIT(6)
  58. #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
  59. #define IMP_CAL_FS_HS_DLY_3 (0x3 << 6)
  60. #define FS_DRV_EN_MASK(x) ((x) << 8)
  61. #define HS_DRV_EN_MASK(x) ((x) << 12)
  62. /* USB_PHY_RX_CTRL */
  63. #define PHASE_FREEZE_DLY_2_CL (0x0 << 0)
  64. #define PHASE_FREEZE_DLY_4_CL BIT(0)
  65. #define ACK_LENGTH_8_CL (0x0 << 2)
  66. #define ACK_LENGTH_12_CL BIT(2)
  67. #define ACK_LENGTH_16_CL (0x2 << 2)
  68. #define ACK_LENGTH_20_CL (0x3 << 2)
  69. #define SQ_LENGTH_3 (0x0 << 4)
  70. #define SQ_LENGTH_6 BIT(4)
  71. #define SQ_LENGTH_9 (0x2 << 4)
  72. #define SQ_LENGTH_12 (0x3 << 4)
  73. #define DISCON_THRESHOLD_260 (0x0 << 6)
  74. #define DISCON_THRESHOLD_270 BIT(6)
  75. #define DISCON_THRESHOLD_280 (0x2 << 6)
  76. #define DISCON_THRESHOLD_290 (0x3 << 6)
  77. #define SQ_THRESHOLD(x) ((x) << 8)
  78. #define LPF_COEF(x) ((x) << 12)
  79. #define INTPL_CUR_10 (0x0 << 14)
  80. #define INTPL_CUR_20 BIT(14)
  81. #define INTPL_CUR_30 (0x2 << 14)
  82. #define INTPL_CUR_40 (0x3 << 14)
  83. /* USB_PHY_ANALOG */
  84. #define ANA_PWR_UP BIT(1)
  85. #define ANA_PWR_DOWN BIT(2)
  86. #define V2I_VCO_RATIO(x) ((x) << 7)
  87. #define R_ROTATE_90 (0x0 << 10)
  88. #define R_ROTATE_0 BIT(10)
  89. #define MODE_TEST_EN BIT(11)
  90. #define ANA_TEST_DC_CTRL(x) ((x) << 12)
  91. static const u32 phy_berlin_pll_dividers[] = {
  92. /* Berlin 2 */
  93. CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
  94. /* Berlin 2CD/Q */
  95. CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
  96. };
  97. struct phy_berlin_usb_priv {
  98. void __iomem *base;
  99. struct reset_control *rst_ctrl;
  100. u32 pll_divider;
  101. };
  102. static int phy_berlin_usb_power_on(struct phy *phy)
  103. {
  104. struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
  105. reset_control_reset(priv->rst_ctrl);
  106. writel(priv->pll_divider,
  107. priv->base + USB_PHY_PLL);
  108. writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
  109. CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
  110. writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
  111. priv->base + USB_PHY_ANALOG);
  112. writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
  113. DISCON_THRESHOLD_270 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
  114. INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
  115. writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
  116. writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
  117. priv->base + USB_PHY_TX_CTRL0);
  118. writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
  119. EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
  120. writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
  121. priv->base + USB_PHY_TX_CTRL0);
  122. writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
  123. FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
  124. return 0;
  125. }
  126. static const struct phy_ops phy_berlin_usb_ops = {
  127. .power_on = phy_berlin_usb_power_on,
  128. .owner = THIS_MODULE,
  129. };
  130. static const struct of_device_id phy_berlin_usb_of_match[] = {
  131. {
  132. .compatible = "marvell,berlin2-usb-phy",
  133. .data = &phy_berlin_pll_dividers[0],
  134. },
  135. {
  136. .compatible = "marvell,berlin2cd-usb-phy",
  137. .data = &phy_berlin_pll_dividers[1],
  138. },
  139. { },
  140. };
  141. MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match);
  142. static int phy_berlin_usb_probe(struct platform_device *pdev)
  143. {
  144. const struct of_device_id *match =
  145. of_match_device(phy_berlin_usb_of_match, &pdev->dev);
  146. struct phy_berlin_usb_priv *priv;
  147. struct resource *res;
  148. struct phy *phy;
  149. struct phy_provider *phy_provider;
  150. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  151. if (!priv)
  152. return -ENOMEM;
  153. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  154. priv->base = devm_ioremap_resource(&pdev->dev, res);
  155. if (IS_ERR(priv->base))
  156. return PTR_ERR(priv->base);
  157. priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
  158. if (IS_ERR(priv->rst_ctrl))
  159. return PTR_ERR(priv->rst_ctrl);
  160. priv->pll_divider = *((u32 *)match->data);
  161. phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
  162. if (IS_ERR(phy)) {
  163. dev_err(&pdev->dev, "failed to create PHY\n");
  164. return PTR_ERR(phy);
  165. }
  166. phy_set_drvdata(phy, priv);
  167. phy_provider =
  168. devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
  169. return PTR_ERR_OR_ZERO(phy_provider);
  170. }
  171. static struct platform_driver phy_berlin_usb_driver = {
  172. .probe = phy_berlin_usb_probe,
  173. .driver = {
  174. .name = "phy-berlin-usb",
  175. .of_match_table = phy_berlin_usb_of_match,
  176. },
  177. };
  178. module_platform_driver(phy_berlin_usb_driver);
  179. MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
  180. MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
  181. MODULE_LICENSE("GPL");