phy-lantiq-vrx200-pcie.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
  4. *
  5. * Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. *
  7. * Based on the BSP (called "UGW") driver:
  8. * Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
  9. * Copyright (C) 2016 Intel Corporation
  10. *
  11. * TODO: PHY modes other than 36MHz (without "SSC")
  12. */
  13. #include <linux/bitfield.h>
  14. #include <linux/bits.h>
  15. #include <linux/clk.h>
  16. #include <linux/delay.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/phy/phy.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/property.h>
  23. #include <linux/regmap.h>
  24. #include <linux/reset.h>
  25. #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
  26. #define PCIE_PHY_PLL_CTRL1 0x44
  27. #define PCIE_PHY_PLL_CTRL2 0x46
  28. #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
  29. #define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN BIT(8)
  30. #define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN BIT(9)
  31. #define PCIE_PHY_PLL_CTRL3 0x48
  32. #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN BIT(1)
  33. #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK GENMASK(6, 4)
  34. #define PCIE_PHY_PLL_CTRL4 0x4a
  35. #define PCIE_PHY_PLL_CTRL5 0x4c
  36. #define PCIE_PHY_PLL_CTRL6 0x4e
  37. #define PCIE_PHY_PLL_CTRL7 0x50
  38. #define PCIE_PHY_PLL_A_CTRL1 0x52
  39. #define PCIE_PHY_PLL_A_CTRL2 0x54
  40. #define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN BIT(14)
  41. #define PCIE_PHY_PLL_A_CTRL3 0x56
  42. #define PCIE_PHY_PLL_A_CTRL3_MMD_MASK GENMASK(15, 13)
  43. #define PCIE_PHY_PLL_STATUS 0x58
  44. #define PCIE_PHY_TX1_CTRL1 0x60
  45. #define PCIE_PHY_TX1_CTRL1_FORCE_EN BIT(3)
  46. #define PCIE_PHY_TX1_CTRL1_LOAD_EN BIT(4)
  47. #define PCIE_PHY_TX1_CTRL2 0x62
  48. #define PCIE_PHY_TX1_CTRL3 0x64
  49. #define PCIE_PHY_TX1_A_CTRL1 0x66
  50. #define PCIE_PHY_TX1_A_CTRL2 0x68
  51. #define PCIE_PHY_TX1_MOD1 0x6a
  52. #define PCIE_PHY_TX1_MOD2 0x6c
  53. #define PCIE_PHY_TX1_MOD3 0x6e
  54. #define PCIE_PHY_TX2_CTRL1 0x70
  55. #define PCIE_PHY_TX2_CTRL1_LOAD_EN BIT(4)
  56. #define PCIE_PHY_TX2_CTRL2 0x72
  57. #define PCIE_PHY_TX2_A_CTRL1 0x76
  58. #define PCIE_PHY_TX2_A_CTRL2 0x78
  59. #define PCIE_PHY_TX2_MOD1 0x7a
  60. #define PCIE_PHY_TX2_MOD2 0x7c
  61. #define PCIE_PHY_TX2_MOD3 0x7e
  62. #define PCIE_PHY_RX1_CTRL1 0xa0
  63. #define PCIE_PHY_RX1_CTRL1_LOAD_EN BIT(1)
  64. #define PCIE_PHY_RX1_CTRL2 0xa2
  65. #define PCIE_PHY_RX1_CDR 0xa4
  66. #define PCIE_PHY_RX1_EI 0xa6
  67. #define PCIE_PHY_RX1_A_CTRL 0xaa
  68. struct ltq_vrx200_pcie_phy_priv {
  69. struct phy *phy;
  70. unsigned int mode;
  71. struct device *dev;
  72. struct regmap *phy_regmap;
  73. struct regmap *rcu_regmap;
  74. struct clk *pdi_clk;
  75. struct clk *phy_clk;
  76. struct reset_control *phy_reset;
  77. struct reset_control *pcie_reset;
  78. u32 rcu_ahb_endian_offset;
  79. u32 rcu_ahb_endian_big_endian_mask;
  80. };
  81. static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
  82. {
  83. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  84. /* PLL Setting */
  85. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
  86. /* increase the bias reference voltage */
  87. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
  88. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
  89. /* Endcnt */
  90. regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
  91. regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
  92. regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
  93. PCIE_PHY_TX1_CTRL1_FORCE_EN,
  94. PCIE_PHY_TX1_CTRL1_FORCE_EN);
  95. /* predrv_ser_en */
  96. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
  97. /* ctrl_lim */
  98. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
  99. /* ctrl */
  100. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
  101. /* predrv_ser_en */
  102. regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
  103. 0x4700);
  104. /* RTERM */
  105. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
  106. /* Improved 100MHz clock output */
  107. regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
  108. regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
  109. /* Reduced CDR BW to avoid glitches */
  110. regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
  111. }
  112. static void pcie_phy_36mhz_mode_setup(struct phy *phy)
  113. {
  114. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  115. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
  116. PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);
  117. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
  118. PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);
  119. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
  120. PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
  121. PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);
  122. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
  123. PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
  124. PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);
  125. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
  126. PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
  127. FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));
  128. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
  129. PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);
  130. /* const_sdm */
  131. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
  132. regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
  133. PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
  134. FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
  135. 0xee));
  136. /* pllmod */
  137. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
  138. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
  139. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
  140. regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
  141. }
  142. static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy)
  143. {
  144. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  145. unsigned int tmp;
  146. int ret;
  147. ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
  148. tmp, ((tmp & 0x0070) == 0x0070), 10,
  149. 10000);
  150. if (ret) {
  151. dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",
  152. tmp);
  153. return ret;
  154. }
  155. return 0;
  156. }
  157. static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy)
  158. {
  159. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  160. static const struct reg_default slices[] = {
  161. {
  162. .reg = PCIE_PHY_TX1_CTRL1,
  163. .def = PCIE_PHY_TX1_CTRL1_LOAD_EN,
  164. },
  165. {
  166. .reg = PCIE_PHY_TX2_CTRL1,
  167. .def = PCIE_PHY_TX2_CTRL1_LOAD_EN,
  168. },
  169. {
  170. .reg = PCIE_PHY_RX1_CTRL1,
  171. .def = PCIE_PHY_RX1_CTRL1_LOAD_EN,
  172. }
  173. };
  174. int i;
  175. for (i = 0; i < ARRAY_SIZE(slices); i++) {
  176. /* enable load_en */
  177. regmap_update_bits(priv->phy_regmap, slices[i].reg,
  178. slices[i].def, slices[i].def);
  179. udelay(1);
  180. /* disable load_en */
  181. regmap_update_bits(priv->phy_regmap, slices[i].reg,
  182. slices[i].def, 0x0);
  183. }
  184. for (i = 0; i < 5; i++) {
  185. /* TX2 modulation */
  186. regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
  187. regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
  188. regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
  189. usleep_range(1000, 2000);
  190. regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
  191. /* TX1 modulation */
  192. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
  193. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
  194. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
  195. usleep_range(1000, 2000);
  196. regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
  197. }
  198. }
  199. static int ltq_vrx200_pcie_phy_init(struct phy *phy)
  200. {
  201. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  202. int ret;
  203. if (of_device_is_big_endian(priv->dev->of_node))
  204. regmap_update_bits(priv->rcu_regmap,
  205. priv->rcu_ahb_endian_offset,
  206. priv->rcu_ahb_endian_big_endian_mask,
  207. priv->rcu_ahb_endian_big_endian_mask);
  208. else
  209. regmap_update_bits(priv->rcu_regmap,
  210. priv->rcu_ahb_endian_offset,
  211. priv->rcu_ahb_endian_big_endian_mask, 0x0);
  212. ret = reset_control_assert(priv->phy_reset);
  213. if (ret)
  214. goto err;
  215. udelay(1);
  216. ret = reset_control_deassert(priv->phy_reset);
  217. if (ret)
  218. goto err;
  219. udelay(1);
  220. ret = reset_control_deassert(priv->pcie_reset);
  221. if (ret)
  222. goto err_assert_phy_reset;
  223. /* Make sure PHY PLL is stable */
  224. usleep_range(20, 40);
  225. return 0;
  226. err_assert_phy_reset:
  227. reset_control_assert(priv->phy_reset);
  228. err:
  229. return ret;
  230. }
  231. static int ltq_vrx200_pcie_phy_exit(struct phy *phy)
  232. {
  233. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  234. int ret;
  235. ret = reset_control_assert(priv->pcie_reset);
  236. if (ret)
  237. return ret;
  238. ret = reset_control_assert(priv->phy_reset);
  239. if (ret)
  240. return ret;
  241. return 0;
  242. }
  243. static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
  244. {
  245. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  246. int ret;
  247. /* Enable PDI to access PCIe PHY register */
  248. ret = clk_prepare_enable(priv->pdi_clk);
  249. if (ret)
  250. goto err;
  251. /* Configure PLL and PHY clock */
  252. ltq_vrx200_pcie_phy_common_setup(phy);
  253. pcie_phy_36mhz_mode_setup(phy);
  254. /* Enable the PCIe PHY and make PLL setting take effect */
  255. ret = clk_prepare_enable(priv->phy_clk);
  256. if (ret)
  257. goto err_disable_pdi_clk;
  258. /* Check if we are in "startup ready" status */
  259. ret = ltq_vrx200_pcie_phy_wait_for_pll(phy);
  260. if (ret)
  261. goto err_disable_phy_clk;
  262. ltq_vrx200_pcie_phy_apply_workarounds(phy);
  263. return 0;
  264. err_disable_phy_clk:
  265. clk_disable_unprepare(priv->phy_clk);
  266. err_disable_pdi_clk:
  267. clk_disable_unprepare(priv->pdi_clk);
  268. err:
  269. return ret;
  270. }
  271. static int ltq_vrx200_pcie_phy_power_off(struct phy *phy)
  272. {
  273. struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
  274. clk_disable_unprepare(priv->phy_clk);
  275. clk_disable_unprepare(priv->pdi_clk);
  276. return 0;
  277. }
  278. static const struct phy_ops ltq_vrx200_pcie_phy_ops = {
  279. .init = ltq_vrx200_pcie_phy_init,
  280. .exit = ltq_vrx200_pcie_phy_exit,
  281. .power_on = ltq_vrx200_pcie_phy_power_on,
  282. .power_off = ltq_vrx200_pcie_phy_power_off,
  283. .owner = THIS_MODULE,
  284. };
  285. static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev,
  286. struct of_phandle_args *args)
  287. {
  288. struct ltq_vrx200_pcie_phy_priv *priv = dev_get_drvdata(dev);
  289. unsigned int mode;
  290. if (args->args_count != 1) {
  291. dev_err(dev, "invalid number of arguments\n");
  292. return ERR_PTR(-EINVAL);
  293. }
  294. mode = args->args[0];
  295. switch (mode) {
  296. case LANTIQ_PCIE_PHY_MODE_36MHZ:
  297. priv->mode = mode;
  298. break;
  299. case LANTIQ_PCIE_PHY_MODE_25MHZ:
  300. case LANTIQ_PCIE_PHY_MODE_25MHZ_SSC:
  301. case LANTIQ_PCIE_PHY_MODE_36MHZ_SSC:
  302. case LANTIQ_PCIE_PHY_MODE_100MHZ:
  303. case LANTIQ_PCIE_PHY_MODE_100MHZ_SSC:
  304. dev_err(dev, "PHY mode not implemented yet: %u\n", mode);
  305. return ERR_PTR(-EINVAL);
  306. default:
  307. dev_err(dev, "invalid PHY mode %u\n", mode);
  308. return ERR_PTR(-EINVAL);
  309. }
  310. return priv->phy;
  311. }
  312. static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev)
  313. {
  314. static const struct regmap_config regmap_config = {
  315. .reg_bits = 8,
  316. .val_bits = 16,
  317. .reg_stride = 2,
  318. .max_register = PCIE_PHY_RX1_A_CTRL,
  319. };
  320. struct ltq_vrx200_pcie_phy_priv *priv;
  321. struct device *dev = &pdev->dev;
  322. struct phy_provider *provider;
  323. struct resource *res;
  324. void __iomem *base;
  325. int ret;
  326. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  327. if (!priv)
  328. return -ENOMEM;
  329. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  330. base = devm_ioremap_resource(dev, res);
  331. if (IS_ERR(base))
  332. return PTR_ERR(base);
  333. priv->phy_regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
  334. if (IS_ERR(priv->phy_regmap))
  335. return PTR_ERR(priv->phy_regmap);
  336. priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
  337. "lantiq,rcu");
  338. if (IS_ERR(priv->rcu_regmap))
  339. return PTR_ERR(priv->rcu_regmap);
  340. ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset",
  341. &priv->rcu_ahb_endian_offset);
  342. if (ret) {
  343. dev_err(dev,
  344. "failed to parse the 'lantiq,rcu-endian-offset' property\n");
  345. return ret;
  346. }
  347. ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask",
  348. &priv->rcu_ahb_endian_big_endian_mask);
  349. if (ret) {
  350. dev_err(dev,
  351. "failed to parse the 'lantiq,rcu-big-endian-mask' property\n");
  352. return ret;
  353. }
  354. priv->pdi_clk = devm_clk_get(dev, "pdi");
  355. if (IS_ERR(priv->pdi_clk))
  356. return PTR_ERR(priv->pdi_clk);
  357. priv->phy_clk = devm_clk_get(dev, "phy");
  358. if (IS_ERR(priv->phy_clk))
  359. return PTR_ERR(priv->phy_clk);
  360. priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
  361. if (IS_ERR(priv->phy_reset))
  362. return PTR_ERR(priv->phy_reset);
  363. priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie");
  364. if (IS_ERR(priv->pcie_reset))
  365. return PTR_ERR(priv->pcie_reset);
  366. priv->dev = dev;
  367. priv->phy = devm_phy_create(dev, dev->of_node,
  368. &ltq_vrx200_pcie_phy_ops);
  369. if (IS_ERR(priv->phy)) {
  370. dev_err(dev, "failed to create PHY\n");
  371. return PTR_ERR(priv->phy);
  372. }
  373. phy_set_drvdata(priv->phy, priv);
  374. dev_set_drvdata(dev, priv);
  375. provider = devm_of_phy_provider_register(dev,
  376. ltq_vrx200_pcie_phy_xlate);
  377. return PTR_ERR_OR_ZERO(provider);
  378. }
  379. static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = {
  380. { .compatible = "lantiq,vrx200-pcie-phy", },
  381. { .compatible = "lantiq,arx300-pcie-phy", },
  382. { /* sentinel */ },
  383. };
  384. MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match);
  385. static struct platform_driver ltq_vrx200_pcie_phy_driver = {
  386. .probe = ltq_vrx200_pcie_phy_probe,
  387. .driver = {
  388. .name = "ltq-vrx200-pcie-phy",
  389. .of_match_table = ltq_vrx200_pcie_phy_of_match,
  390. }
  391. };
  392. module_platform_driver(ltq_vrx200_pcie_phy_driver);
  393. MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
  394. MODULE_DESCRIPTION("Lantiq VRX200 and ARX300 PCIe PHY driver");
  395. MODULE_LICENSE("GPL v2");