phy-brcm-sata.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Broadcom SATA3 AHCI Controller PHY Driver
  4. *
  5. * Copyright (C) 2016 Broadcom
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/device.h>
  9. #include <linux/init.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/platform_device.h>
  17. #define SATA_PCB_BANK_OFFSET 0x23c
  18. #define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
  19. #define MAX_PORTS 2
  20. /* Register offset between PHYs in PCB space */
  21. #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
  22. /* The older SATA PHY registers duplicated per port registers within the map,
  23. * rather than having a separate map per port.
  24. */
  25. #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
  26. /* Register offset between PHYs in PHY control space */
  27. #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
  28. enum brcm_sata_phy_version {
  29. BRCM_SATA_PHY_STB_16NM,
  30. BRCM_SATA_PHY_STB_28NM,
  31. BRCM_SATA_PHY_STB_40NM,
  32. BRCM_SATA_PHY_IPROC_NS2,
  33. BRCM_SATA_PHY_IPROC_NSP,
  34. BRCM_SATA_PHY_IPROC_SR,
  35. BRCM_SATA_PHY_DSL_28NM,
  36. };
  37. enum brcm_sata_phy_rxaeq_mode {
  38. RXAEQ_MODE_OFF = 0,
  39. RXAEQ_MODE_AUTO,
  40. RXAEQ_MODE_MANUAL,
  41. };
  42. static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m)
  43. {
  44. if (!strcmp(m, "auto"))
  45. return RXAEQ_MODE_AUTO;
  46. else if (!strcmp(m, "manual"))
  47. return RXAEQ_MODE_MANUAL;
  48. else
  49. return RXAEQ_MODE_OFF;
  50. }
  51. struct brcm_sata_port {
  52. int portnum;
  53. struct phy *phy;
  54. struct brcm_sata_phy *phy_priv;
  55. bool ssc_en;
  56. enum brcm_sata_phy_rxaeq_mode rxaeq_mode;
  57. u32 rxaeq_val;
  58. };
  59. struct brcm_sata_phy {
  60. struct device *dev;
  61. void __iomem *phy_base;
  62. void __iomem *ctrl_base;
  63. enum brcm_sata_phy_version version;
  64. struct brcm_sata_port phys[MAX_PORTS];
  65. };
  66. enum sata_phy_regs {
  67. BLOCK0_REG_BANK = 0x000,
  68. BLOCK0_XGXSSTATUS = 0x81,
  69. BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12),
  70. BLOCK0_SPARE = 0x8d,
  71. BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
  72. BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
  73. PLL_REG_BANK_0 = 0x050,
  74. PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
  75. PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
  76. PLLCONTROL_0_FREQ_MONITOR = BIT(12),
  77. PLLCONTROL_0_SEQ_START = BIT(15),
  78. PLL_CAP_CHARGE_TIME = 0x83,
  79. PLL_VCO_CAL_THRESH = 0x84,
  80. PLL_CAP_CONTROL = 0x85,
  81. PLL_FREQ_DET_TIME = 0x86,
  82. PLL_ACTRL2 = 0x8b,
  83. PLL_ACTRL2_SELDIV_MASK = 0x1f,
  84. PLL_ACTRL2_SELDIV_SHIFT = 9,
  85. PLL_ACTRL6 = 0x86,
  86. PLL1_REG_BANK = 0x060,
  87. PLL1_ACTRL2 = 0x82,
  88. PLL1_ACTRL3 = 0x83,
  89. PLL1_ACTRL4 = 0x84,
  90. PLL1_ACTRL5 = 0x85,
  91. PLL1_ACTRL6 = 0x86,
  92. PLL1_ACTRL7 = 0x87,
  93. PLL1_ACTRL8 = 0x88,
  94. TX_REG_BANK = 0x070,
  95. TX_ACTRL0 = 0x80,
  96. TX_ACTRL0_TXPOL_FLIP = BIT(6),
  97. TX_ACTRL5 = 0x85,
  98. TX_ACTRL5_SSC_EN = BIT(11),
  99. AEQRX_REG_BANK_0 = 0xd0,
  100. AEQ_CONTROL1 = 0x81,
  101. AEQ_CONTROL1_ENABLE = BIT(2),
  102. AEQ_CONTROL1_FREEZE = BIT(3),
  103. AEQ_FRC_EQ = 0x83,
  104. AEQ_FRC_EQ_FORCE = BIT(0),
  105. AEQ_FRC_EQ_FORCE_VAL = BIT(1),
  106. AEQ_RFZ_FRC_VAL = BIT(8),
  107. AEQRX_REG_BANK_1 = 0xe0,
  108. AEQRX_SLCAL0_CTRL0 = 0x82,
  109. AEQRX_SLCAL1_CTRL0 = 0x86,
  110. OOB_REG_BANK = 0x150,
  111. OOB1_REG_BANK = 0x160,
  112. OOB_CTRL1 = 0x80,
  113. OOB_CTRL1_BURST_MAX_MASK = 0xf,
  114. OOB_CTRL1_BURST_MAX_SHIFT = 12,
  115. OOB_CTRL1_BURST_MIN_MASK = 0xf,
  116. OOB_CTRL1_BURST_MIN_SHIFT = 8,
  117. OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
  118. OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,
  119. OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
  120. OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
  121. OOB_CTRL2 = 0x81,
  122. OOB_CTRL2_SEL_ENA_SHIFT = 15,
  123. OOB_CTRL2_SEL_ENA_RC_SHIFT = 14,
  124. OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
  125. OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,
  126. OOB_CTRL2_BURST_CNT_MASK = 0x3,
  127. OOB_CTRL2_BURST_CNT_SHIFT = 6,
  128. OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
  129. OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
  130. TXPMD_REG_BANK = 0x1a0,
  131. TXPMD_CONTROL1 = 0x81,
  132. TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
  133. TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
  134. TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
  135. TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
  136. TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
  137. TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
  138. TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
  139. RXPMD_REG_BANK = 0x1c0,
  140. RXPMD_RX_CDR_CONTROL1 = 0x81,
  141. RXPMD_RX_PPM_VAL_MASK = 0x1ff,
  142. RXPMD_RXPMD_EN_FRC = BIT(12),
  143. RXPMD_RXPMD_EN_FRC_VAL = BIT(13),
  144. RXPMD_RX_CDR_CDR_PROP_BW = 0x82,
  145. RXPMD_G_CDR_PROP_BW_MASK = 0x7,
  146. RXPMD_G1_CDR_PROP_BW_SHIFT = 0,
  147. RXPMD_G2_CDR_PROP_BW_SHIFT = 3,
  148. RXPMD_G3_CDR_PROB_BW_SHIFT = 6,
  149. RXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 0x83,
  150. RXPMD_G_CDR_ACQ_INT_BW_MASK = 0x7,
  151. RXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,
  152. RXPMD_G2_CDR_ACQ_INT_BW_SHIFT = 3,
  153. RXPMD_G3_CDR_ACQ_INT_BW_SHIFT = 6,
  154. RXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 0x84,
  155. RXPMD_G_CDR_LOCK_INT_BW_MASK = 0x7,
  156. RXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,
  157. RXPMD_G2_CDR_LOCK_INT_BW_SHIFT = 3,
  158. RXPMD_G3_CDR_LOCK_INT_BW_SHIFT = 6,
  159. RXPMD_RX_FREQ_MON_CONTROL1 = 0x87,
  160. RXPMD_MON_CORRECT_EN = BIT(8),
  161. RXPMD_MON_MARGIN_VAL_MASK = 0xff,
  162. };
  163. enum sata_phy_ctrl_regs {
  164. PHY_CTRL_1 = 0x0,
  165. PHY_CTRL_1_RESET = BIT(0),
  166. };
  167. static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
  168. {
  169. struct brcm_sata_phy *priv = port->phy_priv;
  170. u32 size = 0;
  171. switch (priv->version) {
  172. case BRCM_SATA_PHY_IPROC_NS2:
  173. size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
  174. break;
  175. default:
  176. dev_err(priv->dev, "invalid phy version\n");
  177. break;
  178. }
  179. return priv->ctrl_base + (port->portnum * size);
  180. }
  181. static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
  182. u32 ofs, u32 msk, u32 value)
  183. {
  184. struct brcm_sata_phy *priv = port->phy_priv;
  185. void __iomem *pcb_base = priv->phy_base;
  186. u32 tmp;
  187. if (priv->version == BRCM_SATA_PHY_STB_40NM)
  188. bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
  189. else
  190. pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
  191. writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
  192. tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
  193. tmp = (tmp & msk) | value;
  194. writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
  195. }
  196. static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
  197. {
  198. struct brcm_sata_phy *priv = port->phy_priv;
  199. void __iomem *pcb_base = priv->phy_base;
  200. if (priv->version == BRCM_SATA_PHY_STB_40NM)
  201. bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
  202. else
  203. pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
  204. writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
  205. return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
  206. }
  207. /* These defaults were characterized by H/W group */
  208. #define STB_FMIN_VAL_DEFAULT 0x3df
  209. #define STB_FMAX_VAL_DEFAULT 0x3df
  210. #define STB_FMAX_VAL_SSC 0x83
  211. static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
  212. {
  213. struct brcm_sata_phy *priv = port->phy_priv;
  214. u32 tmp;
  215. /* override the TX spread spectrum setting */
  216. tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
  217. brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
  218. /* set fixed min freq */
  219. brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
  220. ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
  221. STB_FMIN_VAL_DEFAULT);
  222. /* set fixed max freq depending on SSC config */
  223. if (port->ssc_en) {
  224. dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
  225. tmp = STB_FMAX_VAL_SSC;
  226. } else {
  227. tmp = STB_FMAX_VAL_DEFAULT;
  228. }
  229. brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
  230. ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
  231. }
  232. #define AEQ_FRC_EQ_VAL_SHIFT 2
  233. #define AEQ_FRC_EQ_VAL_MASK 0x3f
  234. static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
  235. {
  236. u32 tmp = 0, reg = 0;
  237. switch (port->rxaeq_mode) {
  238. case RXAEQ_MODE_OFF:
  239. return 0;
  240. case RXAEQ_MODE_AUTO:
  241. reg = AEQ_CONTROL1;
  242. tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE;
  243. break;
  244. case RXAEQ_MODE_MANUAL:
  245. reg = AEQ_FRC_EQ;
  246. tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL;
  247. if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK)
  248. return -EINVAL;
  249. tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT;
  250. break;
  251. }
  252. brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
  253. brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
  254. return 0;
  255. }
  256. static int brcm_stb_sata_init(struct brcm_sata_port *port)
  257. {
  258. brcm_stb_sata_ssc_init(port);
  259. return brcm_stb_sata_rxaeq_init(port);
  260. }
  261. static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
  262. {
  263. u32 tmp, value;
  264. /* Reduce CP tail current to 1/16th of its default value */
  265. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
  266. /* Turn off CP tail current boost */
  267. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
  268. /* Set a specific AEQ equalizer value */
  269. tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
  270. brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
  271. ~(tmp | AEQ_RFZ_FRC_VAL |
  272. AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
  273. tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
  274. /* Set RX PPM val center frequency */
  275. if (port->ssc_en)
  276. value = 0x52;
  277. else
  278. value = 0;
  279. brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
  280. ~RXPMD_RX_PPM_VAL_MASK, value);
  281. /* Set proportional loop bandwith Gen1/2/3 */
  282. tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
  283. RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G2_CDR_PROP_BW_SHIFT |
  284. RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G3_CDR_PROB_BW_SHIFT;
  285. if (port->ssc_en)
  286. value = 2 << RXPMD_G1_CDR_PROP_BW_SHIFT |
  287. 2 << RXPMD_G2_CDR_PROP_BW_SHIFT |
  288. 2 << RXPMD_G3_CDR_PROB_BW_SHIFT;
  289. else
  290. value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
  291. 1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
  292. 1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
  293. brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
  294. value);
  295. /* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
  296. tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
  297. RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
  298. RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
  299. if (port->ssc_en)
  300. value = 1 << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
  301. 1 << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
  302. 1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
  303. else
  304. value = 0;
  305. brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
  306. ~tmp, value);
  307. /* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
  308. tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
  309. RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
  310. RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
  311. if (port->ssc_en)
  312. value = 1 << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
  313. 1 << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
  314. 1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
  315. else
  316. value = 0;
  317. brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
  318. ~tmp, value);
  319. /* Set no guard band and clamp CDR */
  320. tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
  321. if (port->ssc_en)
  322. value = 0x51;
  323. else
  324. value = 0;
  325. brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
  326. ~tmp, RXPMD_MON_CORRECT_EN | value);
  327. /* Turn on/off SSC */
  328. brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
  329. port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
  330. return 0;
  331. }
  332. static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
  333. {
  334. return brcm_stb_sata_16nm_ssc_init(port);
  335. }
  336. /* NS2 SATA PLL1 defaults were characterized by H/W group */
  337. #define NS2_PLL1_ACTRL2_MAGIC 0x1df8
  338. #define NS2_PLL1_ACTRL3_MAGIC 0x2b00
  339. #define NS2_PLL1_ACTRL4_MAGIC 0x8824
  340. static int brcm_ns2_sata_init(struct brcm_sata_port *port)
  341. {
  342. int try;
  343. unsigned int val;
  344. void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
  345. struct device *dev = port->phy_priv->dev;
  346. /* Configure OOB control */
  347. val = 0x0;
  348. val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
  349. val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
  350. val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
  351. val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
  352. brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
  353. val = 0x0;
  354. val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
  355. val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
  356. val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
  357. brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
  358. /* Configure PHY PLL register bank 1 */
  359. val = NS2_PLL1_ACTRL2_MAGIC;
  360. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
  361. val = NS2_PLL1_ACTRL3_MAGIC;
  362. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
  363. val = NS2_PLL1_ACTRL4_MAGIC;
  364. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
  365. /* Configure PHY BLOCK0 register bank */
  366. /* Set oob_clk_sel to refclk/2 */
  367. brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
  368. ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
  369. BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
  370. /* Strobe PHY reset using PHY control register */
  371. writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
  372. mdelay(1);
  373. writel(0x0, ctrl_base + PHY_CTRL_1);
  374. mdelay(1);
  375. /* Wait for PHY PLL lock by polling pll_lock bit */
  376. try = 50;
  377. while (try) {
  378. val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
  379. BLOCK0_XGXSSTATUS);
  380. if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
  381. break;
  382. msleep(20);
  383. try--;
  384. }
  385. if (!try) {
  386. /* PLL did not lock; give up */
  387. dev_err(dev, "port%d PLL did not lock\n", port->portnum);
  388. return -ETIMEDOUT;
  389. }
  390. dev_dbg(dev, "port%d initialized\n", port->portnum);
  391. return 0;
  392. }
  393. static int brcm_nsp_sata_init(struct brcm_sata_port *port)
  394. {
  395. struct device *dev = port->phy_priv->dev;
  396. unsigned int oob_bank;
  397. unsigned int val, try;
  398. /* Configure OOB control */
  399. if (port->portnum == 0)
  400. oob_bank = OOB_REG_BANK;
  401. else if (port->portnum == 1)
  402. oob_bank = OOB1_REG_BANK;
  403. else
  404. return -EINVAL;
  405. val = 0x0;
  406. val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
  407. val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
  408. val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
  409. val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
  410. brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
  411. val = 0x0;
  412. val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
  413. val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
  414. val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
  415. brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
  416. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
  417. ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
  418. 0x0c << PLL_ACTRL2_SELDIV_SHIFT);
  419. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
  420. 0xff0, 0x4f0);
  421. val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
  422. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
  423. ~val, val);
  424. val = PLLCONTROL_0_SEQ_START;
  425. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
  426. ~val, 0);
  427. mdelay(10);
  428. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
  429. ~val, val);
  430. /* Wait for pll_seq_done bit */
  431. try = 50;
  432. while (--try) {
  433. val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
  434. BLOCK0_XGXSSTATUS);
  435. if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
  436. break;
  437. msleep(20);
  438. }
  439. if (!try) {
  440. /* PLL did not lock; give up */
  441. dev_err(dev, "port%d PLL did not lock\n", port->portnum);
  442. return -ETIMEDOUT;
  443. }
  444. dev_dbg(dev, "port%d initialized\n", port->portnum);
  445. return 0;
  446. }
  447. /* SR PHY PLL0 registers */
  448. #define SR_PLL0_ACTRL6_MAGIC 0xa
  449. /* SR PHY PLL1 registers */
  450. #define SR_PLL1_ACTRL2_MAGIC 0x32
  451. #define SR_PLL1_ACTRL3_MAGIC 0x2
  452. #define SR_PLL1_ACTRL4_MAGIC 0x3e8
  453. static int brcm_sr_sata_init(struct brcm_sata_port *port)
  454. {
  455. struct device *dev = port->phy_priv->dev;
  456. unsigned int val, try;
  457. /* Configure PHY PLL register bank 1 */
  458. val = SR_PLL1_ACTRL2_MAGIC;
  459. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
  460. val = SR_PLL1_ACTRL3_MAGIC;
  461. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
  462. val = SR_PLL1_ACTRL4_MAGIC;
  463. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
  464. /* Configure PHY PLL register bank 0 */
  465. val = SR_PLL0_ACTRL6_MAGIC;
  466. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
  467. /* Wait for PHY PLL lock by polling pll_lock bit */
  468. try = 50;
  469. do {
  470. val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
  471. BLOCK0_XGXSSTATUS);
  472. if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
  473. break;
  474. msleep(20);
  475. try--;
  476. } while (try);
  477. if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
  478. /* PLL did not lock; give up */
  479. dev_err(dev, "port%d PLL did not lock\n", port->portnum);
  480. return -ETIMEDOUT;
  481. }
  482. /* Invert Tx polarity */
  483. brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
  484. ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
  485. /* Configure OOB control to handle 100MHz reference clock */
  486. val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
  487. (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
  488. (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
  489. (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
  490. brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
  491. val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
  492. (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
  493. (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
  494. brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
  495. return 0;
  496. }
  497. static int brcm_dsl_sata_init(struct brcm_sata_port *port)
  498. {
  499. struct device *dev = port->phy_priv->dev;
  500. unsigned int try;
  501. u32 tmp;
  502. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
  503. brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
  504. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
  505. 0, 0x3089);
  506. usleep_range(1000, 2000);
  507. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
  508. 0, 0x3088);
  509. usleep_range(1000, 2000);
  510. brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
  511. 0, 0x3000);
  512. brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
  513. 0, 0x3000);
  514. usleep_range(1000, 2000);
  515. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
  516. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
  517. brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
  518. usleep_range(1000, 2000);
  519. /* Acquire PLL lock */
  520. try = 50;
  521. while (try) {
  522. tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
  523. BLOCK0_XGXSSTATUS);
  524. if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
  525. break;
  526. msleep(20);
  527. try--;
  528. };
  529. if (!try) {
  530. /* PLL did not lock; give up */
  531. dev_err(dev, "port%d PLL did not lock\n", port->portnum);
  532. return -ETIMEDOUT;
  533. }
  534. dev_dbg(dev, "port%d initialized\n", port->portnum);
  535. return 0;
  536. }
  537. static int brcm_sata_phy_init(struct phy *phy)
  538. {
  539. int rc;
  540. struct brcm_sata_port *port = phy_get_drvdata(phy);
  541. switch (port->phy_priv->version) {
  542. case BRCM_SATA_PHY_STB_16NM:
  543. rc = brcm_stb_sata_16nm_init(port);
  544. break;
  545. case BRCM_SATA_PHY_STB_28NM:
  546. case BRCM_SATA_PHY_STB_40NM:
  547. rc = brcm_stb_sata_init(port);
  548. break;
  549. case BRCM_SATA_PHY_IPROC_NS2:
  550. rc = brcm_ns2_sata_init(port);
  551. break;
  552. case BRCM_SATA_PHY_IPROC_NSP:
  553. rc = brcm_nsp_sata_init(port);
  554. break;
  555. case BRCM_SATA_PHY_IPROC_SR:
  556. rc = brcm_sr_sata_init(port);
  557. break;
  558. case BRCM_SATA_PHY_DSL_28NM:
  559. rc = brcm_dsl_sata_init(port);
  560. break;
  561. default:
  562. rc = -ENODEV;
  563. }
  564. return rc;
  565. }
  566. static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
  567. {
  568. u32 tmp = BIT(8);
  569. brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
  570. ~tmp, tmp);
  571. }
  572. static int brcm_sata_phy_calibrate(struct phy *phy)
  573. {
  574. struct brcm_sata_port *port = phy_get_drvdata(phy);
  575. int rc = -EOPNOTSUPP;
  576. switch (port->phy_priv->version) {
  577. case BRCM_SATA_PHY_STB_28NM:
  578. case BRCM_SATA_PHY_STB_40NM:
  579. brcm_stb_sata_calibrate(port);
  580. rc = 0;
  581. break;
  582. default:
  583. break;
  584. }
  585. return rc;
  586. }
  587. static const struct phy_ops phy_ops = {
  588. .init = brcm_sata_phy_init,
  589. .calibrate = brcm_sata_phy_calibrate,
  590. .owner = THIS_MODULE,
  591. };
  592. static const struct of_device_id brcm_sata_phy_of_match[] = {
  593. { .compatible = "brcm,bcm7216-sata-phy",
  594. .data = (void *)BRCM_SATA_PHY_STB_16NM },
  595. { .compatible = "brcm,bcm7445-sata-phy",
  596. .data = (void *)BRCM_SATA_PHY_STB_28NM },
  597. { .compatible = "brcm,bcm7425-sata-phy",
  598. .data = (void *)BRCM_SATA_PHY_STB_40NM },
  599. { .compatible = "brcm,iproc-ns2-sata-phy",
  600. .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
  601. { .compatible = "brcm,iproc-nsp-sata-phy",
  602. .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
  603. { .compatible = "brcm,iproc-sr-sata-phy",
  604. .data = (void *)BRCM_SATA_PHY_IPROC_SR },
  605. { .compatible = "brcm,bcm63138-sata-phy",
  606. .data = (void *)BRCM_SATA_PHY_DSL_28NM },
  607. {},
  608. };
  609. MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
  610. static int brcm_sata_phy_probe(struct platform_device *pdev)
  611. {
  612. const char *rxaeq_mode;
  613. struct device *dev = &pdev->dev;
  614. struct device_node *dn = dev->of_node, *child;
  615. const struct of_device_id *of_id;
  616. struct brcm_sata_phy *priv;
  617. struct resource *res;
  618. struct phy_provider *provider;
  619. int ret, count = 0;
  620. if (of_get_child_count(dn) == 0)
  621. return -ENODEV;
  622. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  623. if (!priv)
  624. return -ENOMEM;
  625. dev_set_drvdata(dev, priv);
  626. priv->dev = dev;
  627. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
  628. priv->phy_base = devm_ioremap_resource(dev, res);
  629. if (IS_ERR(priv->phy_base))
  630. return PTR_ERR(priv->phy_base);
  631. of_id = of_match_node(brcm_sata_phy_of_match, dn);
  632. if (of_id)
  633. priv->version = (enum brcm_sata_phy_version)of_id->data;
  634. else
  635. priv->version = BRCM_SATA_PHY_STB_28NM;
  636. if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
  637. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  638. "phy-ctrl");
  639. priv->ctrl_base = devm_ioremap_resource(dev, res);
  640. if (IS_ERR(priv->ctrl_base))
  641. return PTR_ERR(priv->ctrl_base);
  642. }
  643. for_each_available_child_of_node(dn, child) {
  644. unsigned int id;
  645. struct brcm_sata_port *port;
  646. if (of_property_read_u32(child, "reg", &id)) {
  647. dev_err(dev, "missing reg property in node %pOFn\n",
  648. child);
  649. ret = -EINVAL;
  650. goto put_child;
  651. }
  652. if (id >= MAX_PORTS) {
  653. dev_err(dev, "invalid reg: %u\n", id);
  654. ret = -EINVAL;
  655. goto put_child;
  656. }
  657. if (priv->phys[id].phy) {
  658. dev_err(dev, "already registered port %u\n", id);
  659. ret = -EINVAL;
  660. goto put_child;
  661. }
  662. port = &priv->phys[id];
  663. port->portnum = id;
  664. port->phy_priv = priv;
  665. port->phy = devm_phy_create(dev, child, &phy_ops);
  666. port->rxaeq_mode = RXAEQ_MODE_OFF;
  667. if (!of_property_read_string(child, "brcm,rxaeq-mode",
  668. &rxaeq_mode))
  669. port->rxaeq_mode = rxaeq_to_val(rxaeq_mode);
  670. if (port->rxaeq_mode == RXAEQ_MODE_MANUAL)
  671. of_property_read_u32(child, "brcm,rxaeq-value",
  672. &port->rxaeq_val);
  673. port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
  674. if (IS_ERR(port->phy)) {
  675. dev_err(dev, "failed to create PHY\n");
  676. ret = PTR_ERR(port->phy);
  677. goto put_child;
  678. }
  679. phy_set_drvdata(port->phy, port);
  680. count++;
  681. }
  682. provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  683. if (IS_ERR(provider)) {
  684. dev_err(dev, "could not register PHY provider\n");
  685. return PTR_ERR(provider);
  686. }
  687. dev_info(dev, "registered %d port(s)\n", count);
  688. return 0;
  689. put_child:
  690. of_node_put(child);
  691. return ret;
  692. }
  693. static struct platform_driver brcm_sata_phy_driver = {
  694. .probe = brcm_sata_phy_probe,
  695. .driver = {
  696. .of_match_table = brcm_sata_phy_of_match,
  697. .name = "brcm-sata-phy",
  698. }
  699. };
  700. module_platform_driver(brcm_sata_phy_driver);
  701. MODULE_DESCRIPTION("Broadcom SATA PHY driver");
  702. MODULE_LICENSE("GPL");
  703. MODULE_AUTHOR("Marc Carino");
  704. MODULE_AUTHOR("Brian Norris");
  705. MODULE_ALIAS("platform:phy-brcm-sata");