phy-bcm-cygnus-pcie.c 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221
  1. /*
  2. * Copyright (C) 2015 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/delay.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/platform_device.h>
  19. #define PCIE_CFG_OFFSET 0x00
  20. #define PCIE1_PHY_IDDQ_SHIFT 10
  21. #define PCIE0_PHY_IDDQ_SHIFT 2
  22. enum cygnus_pcie_phy_id {
  23. CYGNUS_PHY_PCIE0 = 0,
  24. CYGNUS_PHY_PCIE1,
  25. MAX_NUM_PHYS,
  26. };
  27. struct cygnus_pcie_phy_core;
  28. /**
  29. * struct cygnus_pcie_phy - Cygnus PCIe PHY device
  30. * @core: pointer to the Cygnus PCIe PHY core control
  31. * @id: internal ID to identify the Cygnus PCIe PHY
  32. * @phy: pointer to the kernel PHY device
  33. */
  34. struct cygnus_pcie_phy {
  35. struct cygnus_pcie_phy_core *core;
  36. enum cygnus_pcie_phy_id id;
  37. struct phy *phy;
  38. };
  39. /**
  40. * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
  41. * @dev: pointer to device
  42. * @base: base register
  43. * @lock: mutex to protect access to individual PHYs
  44. * @phys: pointer to Cygnus PHY device
  45. */
  46. struct cygnus_pcie_phy_core {
  47. struct device *dev;
  48. void __iomem *base;
  49. struct mutex lock;
  50. struct cygnus_pcie_phy phys[MAX_NUM_PHYS];
  51. };
  52. static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)
  53. {
  54. struct cygnus_pcie_phy_core *core = phy->core;
  55. unsigned shift;
  56. u32 val;
  57. mutex_lock(&core->lock);
  58. switch (phy->id) {
  59. case CYGNUS_PHY_PCIE0:
  60. shift = PCIE0_PHY_IDDQ_SHIFT;
  61. break;
  62. case CYGNUS_PHY_PCIE1:
  63. shift = PCIE1_PHY_IDDQ_SHIFT;
  64. break;
  65. default:
  66. mutex_unlock(&core->lock);
  67. dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);
  68. return -EINVAL;
  69. }
  70. if (enable) {
  71. val = readl(core->base + PCIE_CFG_OFFSET);
  72. val &= ~BIT(shift);
  73. writel(val, core->base + PCIE_CFG_OFFSET);
  74. /*
  75. * Wait 50 ms for the PCIe Serdes to stabilize after the analog
  76. * front end is brought up
  77. */
  78. msleep(50);
  79. } else {
  80. val = readl(core->base + PCIE_CFG_OFFSET);
  81. val |= BIT(shift);
  82. writel(val, core->base + PCIE_CFG_OFFSET);
  83. }
  84. mutex_unlock(&core->lock);
  85. dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,
  86. enable ? "enabled" : "disabled");
  87. return 0;
  88. }
  89. static int cygnus_pcie_phy_power_on(struct phy *p)
  90. {
  91. struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
  92. return cygnus_pcie_power_config(phy, true);
  93. }
  94. static int cygnus_pcie_phy_power_off(struct phy *p)
  95. {
  96. struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
  97. return cygnus_pcie_power_config(phy, false);
  98. }
  99. static const struct phy_ops cygnus_pcie_phy_ops = {
  100. .power_on = cygnus_pcie_phy_power_on,
  101. .power_off = cygnus_pcie_phy_power_off,
  102. .owner = THIS_MODULE,
  103. };
  104. static int cygnus_pcie_phy_probe(struct platform_device *pdev)
  105. {
  106. struct device *dev = &pdev->dev;
  107. struct device_node *node = dev->of_node, *child;
  108. struct cygnus_pcie_phy_core *core;
  109. struct phy_provider *provider;
  110. struct resource *res;
  111. unsigned cnt = 0;
  112. int ret;
  113. if (of_get_child_count(node) == 0) {
  114. dev_err(dev, "PHY no child node\n");
  115. return -ENODEV;
  116. }
  117. core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
  118. if (!core)
  119. return -ENOMEM;
  120. core->dev = dev;
  121. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  122. core->base = devm_ioremap_resource(dev, res);
  123. if (IS_ERR(core->base))
  124. return PTR_ERR(core->base);
  125. mutex_init(&core->lock);
  126. for_each_available_child_of_node(node, child) {
  127. unsigned int id;
  128. struct cygnus_pcie_phy *p;
  129. if (of_property_read_u32(child, "reg", &id)) {
  130. dev_err(dev, "missing reg property for %pOFn\n",
  131. child);
  132. ret = -EINVAL;
  133. goto put_child;
  134. }
  135. if (id >= MAX_NUM_PHYS) {
  136. dev_err(dev, "invalid PHY id: %u\n", id);
  137. ret = -EINVAL;
  138. goto put_child;
  139. }
  140. if (core->phys[id].phy) {
  141. dev_err(dev, "duplicated PHY id: %u\n", id);
  142. ret = -EINVAL;
  143. goto put_child;
  144. }
  145. p = &core->phys[id];
  146. p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);
  147. if (IS_ERR(p->phy)) {
  148. dev_err(dev, "failed to create PHY\n");
  149. ret = PTR_ERR(p->phy);
  150. goto put_child;
  151. }
  152. p->core = core;
  153. p->id = id;
  154. phy_set_drvdata(p->phy, p);
  155. cnt++;
  156. }
  157. dev_set_drvdata(dev, core);
  158. provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  159. if (IS_ERR(provider)) {
  160. dev_err(dev, "failed to register PHY provider\n");
  161. return PTR_ERR(provider);
  162. }
  163. dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);
  164. return 0;
  165. put_child:
  166. of_node_put(child);
  167. return ret;
  168. }
  169. static const struct of_device_id cygnus_pcie_phy_match_table[] = {
  170. { .compatible = "brcm,cygnus-pcie-phy" },
  171. { /* sentinel */ }
  172. };
  173. MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);
  174. static struct platform_driver cygnus_pcie_phy_driver = {
  175. .driver = {
  176. .name = "cygnus-pcie-phy",
  177. .of_match_table = cygnus_pcie_phy_match_table,
  178. },
  179. .probe = cygnus_pcie_phy_probe,
  180. };
  181. module_platform_driver(cygnus_pcie_phy_driver);
  182. MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
  183. MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");
  184. MODULE_LICENSE("GPL v2");