phy-meson-g12a-usb3-pcie.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic G12A USB3 + PCIE Combo PHY driver
  4. *
  5. * Copyright (C) 2017 Amlogic, Inc. All rights reserved
  6. * Copyright (C) 2019 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstrong@baylibre.com>
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/bitops.h>
  11. #include <linux/clk.h>
  12. #include <linux/module.h>
  13. #include <linux/of_device.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/regmap.h>
  16. #include <linux/reset.h>
  17. #include <linux/platform_device.h>
  18. #include <dt-bindings/phy/phy.h>
  19. #define PHY_R0 0x00
  20. #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
  21. #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
  22. #define PHY_R1 0x04
  23. #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
  24. #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
  25. #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
  26. #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
  27. #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
  28. #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
  29. #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
  30. #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
  31. #define PHY_R2 0x08
  32. #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
  33. #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
  34. #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
  35. #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
  36. #define PHY_R4 0x10
  37. #define PHY_R4_PHY_CR_WRITE BIT(0)
  38. #define PHY_R4_PHY_CR_READ BIT(1)
  39. #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
  40. #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
  41. #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
  42. #define PHY_R5 0x14
  43. #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
  44. #define PHY_R5_PHY_CR_ACK BIT(16)
  45. #define PHY_R5_PHY_BS_OUT BIT(17)
  46. #define PCIE_RESET_DELAY 500
  47. struct phy_g12a_usb3_pcie_priv {
  48. struct regmap *regmap;
  49. struct regmap *regmap_cr;
  50. struct clk *clk_ref;
  51. struct reset_control *reset;
  52. struct phy *phy;
  53. unsigned int mode;
  54. };
  55. static const struct regmap_config phy_g12a_usb3_pcie_regmap_conf = {
  56. .reg_bits = 8,
  57. .val_bits = 32,
  58. .reg_stride = 4,
  59. .max_register = PHY_R5,
  60. };
  61. static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
  62. unsigned int addr)
  63. {
  64. unsigned int val, reg;
  65. int ret;
  66. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
  67. regmap_write(priv->regmap, PHY_R4, reg);
  68. regmap_write(priv->regmap, PHY_R4, reg);
  69. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
  70. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  71. (val & PHY_R5_PHY_CR_ACK),
  72. 5, 1000);
  73. if (ret)
  74. return ret;
  75. regmap_write(priv->regmap, PHY_R4, reg);
  76. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  77. !(val & PHY_R5_PHY_CR_ACK),
  78. 5, 1000);
  79. if (ret)
  80. return ret;
  81. return 0;
  82. }
  83. static int phy_g12a_usb3_pcie_cr_bus_read(void *context, unsigned int addr,
  84. unsigned int *data)
  85. {
  86. struct phy_g12a_usb3_pcie_priv *priv = context;
  87. unsigned int val;
  88. int ret;
  89. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  90. if (ret)
  91. return ret;
  92. regmap_write(priv->regmap, PHY_R4, 0);
  93. regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
  94. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  95. (val & PHY_R5_PHY_CR_ACK),
  96. 5, 1000);
  97. if (ret)
  98. return ret;
  99. *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
  100. regmap_write(priv->regmap, PHY_R4, 0);
  101. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  102. !(val & PHY_R5_PHY_CR_ACK),
  103. 5, 1000);
  104. if (ret)
  105. return ret;
  106. return 0;
  107. }
  108. static int phy_g12a_usb3_pcie_cr_bus_write(void *context, unsigned int addr,
  109. unsigned int data)
  110. {
  111. struct phy_g12a_usb3_pcie_priv *priv = context;
  112. unsigned int val, reg;
  113. int ret;
  114. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  115. if (ret)
  116. return ret;
  117. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
  118. regmap_write(priv->regmap, PHY_R4, reg);
  119. regmap_write(priv->regmap, PHY_R4, reg);
  120. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
  121. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  122. (val & PHY_R5_PHY_CR_ACK),
  123. 5, 1000);
  124. if (ret)
  125. return ret;
  126. regmap_write(priv->regmap, PHY_R4, reg);
  127. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  128. (val & PHY_R5_PHY_CR_ACK) == 0,
  129. 5, 1000);
  130. if (ret)
  131. return ret;
  132. regmap_write(priv->regmap, PHY_R4, reg);
  133. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
  134. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  135. (val & PHY_R5_PHY_CR_ACK),
  136. 5, 1000);
  137. if (ret)
  138. return ret;
  139. regmap_write(priv->regmap, PHY_R4, reg);
  140. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  141. (val & PHY_R5_PHY_CR_ACK) == 0,
  142. 5, 1000);
  143. if (ret)
  144. return ret;
  145. return 0;
  146. }
  147. static const struct regmap_config phy_g12a_usb3_pcie_cr_regmap_conf = {
  148. .reg_bits = 16,
  149. .val_bits = 16,
  150. .reg_read = phy_g12a_usb3_pcie_cr_bus_read,
  151. .reg_write = phy_g12a_usb3_pcie_cr_bus_write,
  152. .max_register = 0xffff,
  153. .disable_locking = true,
  154. };
  155. static int phy_g12a_usb3_init(struct phy *phy)
  156. {
  157. struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
  158. int data, ret;
  159. ret = reset_control_reset(priv->reset);
  160. if (ret)
  161. return ret;
  162. /* Switch PHY to USB3 */
  163. /* TODO figure out how to handle when PCIe was set in the bootloader */
  164. regmap_update_bits(priv->regmap, PHY_R0,
  165. PHY_R0_PCIE_USB3_SWITCH,
  166. PHY_R0_PCIE_USB3_SWITCH);
  167. /*
  168. * WORKAROUND: There is SSPHY suspend bug due to
  169. * which USB enumerates
  170. * in HS mode instead of SS mode. Workaround it by asserting
  171. * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
  172. * mode
  173. */
  174. ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7));
  175. if (ret)
  176. return ret;
  177. ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20);
  178. if (ret)
  179. return ret;
  180. /*
  181. * Fix RX Equalization setting as follows
  182. * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
  183. * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
  184. * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
  185. * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
  186. */
  187. ret = regmap_read(priv->regmap_cr, 0x1006, &data);
  188. if (ret)
  189. return ret;
  190. data &= ~BIT(6);
  191. data |= BIT(7);
  192. data &= ~(0x7 << 8);
  193. data |= (0x3 << 8);
  194. data |= (1 << 11);
  195. ret = regmap_write(priv->regmap_cr, 0x1006, data);
  196. if (ret)
  197. return ret;
  198. /*
  199. * Set EQ and TX launch amplitudes as follows
  200. * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
  201. * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
  202. * LANE0.TX_OVRD_DRV_LO.EN set to 1.
  203. */
  204. ret = regmap_read(priv->regmap_cr, 0x1002, &data);
  205. if (ret)
  206. return ret;
  207. data &= ~0x3f80;
  208. data |= (0x16 << 7);
  209. data &= ~0x7f;
  210. data |= (0x7f | BIT(14));
  211. ret = regmap_write(priv->regmap_cr, 0x1002, data);
  212. if (ret)
  213. return ret;
  214. /* MPLL_LOOP_CTL.PROP_CNTRL = 8 */
  215. ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4);
  216. if (ret)
  217. return ret;
  218. regmap_update_bits(priv->regmap, PHY_R2,
  219. PHY_R2_PHY_TX_VBOOST_LVL,
  220. FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
  221. regmap_update_bits(priv->regmap, PHY_R1,
  222. PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
  223. FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
  224. FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
  225. return 0;
  226. }
  227. static int phy_g12a_usb3_pcie_power_on(struct phy *phy)
  228. {
  229. struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
  230. if (priv->mode == PHY_TYPE_USB3)
  231. return 0;
  232. regmap_update_bits(priv->regmap, PHY_R0,
  233. PHY_R0_PCIE_POWER_STATE,
  234. FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
  235. return 0;
  236. }
  237. static int phy_g12a_usb3_pcie_power_off(struct phy *phy)
  238. {
  239. struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
  240. if (priv->mode == PHY_TYPE_USB3)
  241. return 0;
  242. regmap_update_bits(priv->regmap, PHY_R0,
  243. PHY_R0_PCIE_POWER_STATE,
  244. FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
  245. return 0;
  246. }
  247. static int phy_g12a_usb3_pcie_reset(struct phy *phy)
  248. {
  249. struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
  250. int ret;
  251. if (priv->mode == PHY_TYPE_USB3)
  252. return 0;
  253. ret = reset_control_assert(priv->reset);
  254. if (ret)
  255. return ret;
  256. udelay(PCIE_RESET_DELAY);
  257. ret = reset_control_deassert(priv->reset);
  258. if (ret)
  259. return ret;
  260. udelay(PCIE_RESET_DELAY);
  261. return 0;
  262. }
  263. static int phy_g12a_usb3_pcie_init(struct phy *phy)
  264. {
  265. struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
  266. if (priv->mode == PHY_TYPE_USB3)
  267. return phy_g12a_usb3_init(phy);
  268. return 0;
  269. }
  270. static int phy_g12a_usb3_pcie_exit(struct phy *phy)
  271. {
  272. struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
  273. if (priv->mode == PHY_TYPE_USB3)
  274. return reset_control_reset(priv->reset);
  275. return 0;
  276. }
  277. static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
  278. struct of_phandle_args *args)
  279. {
  280. struct phy_g12a_usb3_pcie_priv *priv = dev_get_drvdata(dev);
  281. unsigned int mode;
  282. if (args->args_count < 1) {
  283. dev_err(dev, "invalid number of arguments\n");
  284. return ERR_PTR(-EINVAL);
  285. }
  286. mode = args->args[0];
  287. if (mode != PHY_TYPE_USB3 && mode != PHY_TYPE_PCIE) {
  288. dev_err(dev, "invalid phy mode select argument\n");
  289. return ERR_PTR(-EINVAL);
  290. }
  291. priv->mode = mode;
  292. return priv->phy;
  293. }
  294. static const struct phy_ops phy_g12a_usb3_pcie_ops = {
  295. .init = phy_g12a_usb3_pcie_init,
  296. .exit = phy_g12a_usb3_pcie_exit,
  297. .power_on = phy_g12a_usb3_pcie_power_on,
  298. .power_off = phy_g12a_usb3_pcie_power_off,
  299. .reset = phy_g12a_usb3_pcie_reset,
  300. .owner = THIS_MODULE,
  301. };
  302. static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev)
  303. {
  304. struct device *dev = &pdev->dev;
  305. struct device_node *np = dev->of_node;
  306. struct phy_g12a_usb3_pcie_priv *priv;
  307. struct resource *res;
  308. struct phy_provider *phy_provider;
  309. void __iomem *base;
  310. int ret;
  311. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  312. if (!priv)
  313. return -ENOMEM;
  314. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  315. base = devm_ioremap_resource(dev, res);
  316. if (IS_ERR(base))
  317. return PTR_ERR(base);
  318. priv->regmap = devm_regmap_init_mmio(dev, base,
  319. &phy_g12a_usb3_pcie_regmap_conf);
  320. if (IS_ERR(priv->regmap))
  321. return PTR_ERR(priv->regmap);
  322. priv->regmap_cr = devm_regmap_init(dev, NULL, priv,
  323. &phy_g12a_usb3_pcie_cr_regmap_conf);
  324. if (IS_ERR(priv->regmap_cr))
  325. return PTR_ERR(priv->regmap_cr);
  326. priv->clk_ref = devm_clk_get(dev, "ref_clk");
  327. if (IS_ERR(priv->clk_ref))
  328. return PTR_ERR(priv->clk_ref);
  329. ret = clk_prepare_enable(priv->clk_ref);
  330. if (ret)
  331. goto err_disable_clk_ref;
  332. priv->reset = devm_reset_control_array_get(dev, false, false);
  333. if (IS_ERR(priv->reset))
  334. return PTR_ERR(priv->reset);
  335. priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops);
  336. if (IS_ERR(priv->phy)) {
  337. ret = PTR_ERR(priv->phy);
  338. if (ret != -EPROBE_DEFER)
  339. dev_err(dev, "failed to create PHY\n");
  340. return ret;
  341. }
  342. phy_set_drvdata(priv->phy, priv);
  343. dev_set_drvdata(dev, priv);
  344. phy_provider = devm_of_phy_provider_register(dev,
  345. phy_g12a_usb3_pcie_xlate);
  346. return PTR_ERR_OR_ZERO(phy_provider);
  347. err_disable_clk_ref:
  348. clk_disable_unprepare(priv->clk_ref);
  349. return ret;
  350. }
  351. static const struct of_device_id phy_g12a_usb3_pcie_of_match[] = {
  352. { .compatible = "amlogic,g12a-usb3-pcie-phy", },
  353. { },
  354. };
  355. MODULE_DEVICE_TABLE(of, phy_g12a_usb3_pcie_of_match);
  356. static struct platform_driver phy_g12a_usb3_pcie_driver = {
  357. .probe = phy_g12a_usb3_pcie_probe,
  358. .driver = {
  359. .name = "phy-g12a-usb3-pcie",
  360. .of_match_table = phy_g12a_usb3_pcie_of_match,
  361. },
  362. };
  363. module_platform_driver(phy_g12a_usb3_pcie_driver);
  364. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
  365. MODULE_DESCRIPTION("Amlogic G12A USB3 + PCIE Combo PHY driver");
  366. MODULE_LICENSE("GPL v2");