phy-meson-axg-mipi-pcie-analog.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic AXG MIPI + PCIE analog PHY driver
  4. *
  5. * Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt>
  6. */
  7. #include <linux/module.h>
  8. #include <linux/phy/phy.h>
  9. #include <linux/regmap.h>
  10. #include <linux/platform_device.h>
  11. #include <dt-bindings/phy/phy.h>
  12. #define HHI_MIPI_CNTL0 0x00
  13. #define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
  14. #define HHI_MIPI_CNTL0_ENABLE BIT(29)
  15. #define HHI_MIPI_CNTL0_BANDGAP BIT(26)
  16. #define HHI_MIPI_CNTL0_DECODE_TO_RTERM GENMASK(15, 12)
  17. #define HHI_MIPI_CNTL0_OUTPUT_EN BIT(3)
  18. #define HHI_MIPI_CNTL1 0x01
  19. #define HHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12)
  20. #define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)
  21. #define HHI_MIPI_CNTL1_LP_RESISTER BIT(3)
  22. #define HHI_MIPI_CNTL1_INPUT_SETTING BIT(2)
  23. #define HHI_MIPI_CNTL1_INPUT_SEL BIT(1)
  24. #define HHI_MIPI_CNTL1_PRBS7_EN BIT(0)
  25. #define HHI_MIPI_CNTL2 0x02
  26. #define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25)
  27. #define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)
  28. #define HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
  29. #define HHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17)
  30. #define HHI_MIPI_CNTL2_LPULPS_EN BIT(16)
  31. #define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n))
  32. #define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)
  33. struct phy_axg_mipi_pcie_analog_priv {
  34. struct phy *phy;
  35. unsigned int mode;
  36. struct regmap *regmap;
  37. };
  38. static const struct regmap_config phy_axg_mipi_pcie_analog_regmap_conf = {
  39. .reg_bits = 8,
  40. .val_bits = 32,
  41. .reg_stride = 4,
  42. .max_register = HHI_MIPI_CNTL2,
  43. };
  44. static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy)
  45. {
  46. struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
  47. /* MIPI not supported yet */
  48. if (priv->mode != PHY_TYPE_PCIE)
  49. return -EINVAL;
  50. regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
  51. HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
  52. regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
  53. HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
  54. return 0;
  55. }
  56. static int phy_axg_mipi_pcie_analog_power_off(struct phy *phy)
  57. {
  58. struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
  59. /* MIPI not supported yet */
  60. if (priv->mode != PHY_TYPE_PCIE)
  61. return -EINVAL;
  62. regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
  63. HHI_MIPI_CNTL0_BANDGAP, 0);
  64. regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
  65. HHI_MIPI_CNTL0_ENABLE, 0);
  66. return 0;
  67. }
  68. static int phy_axg_mipi_pcie_analog_init(struct phy *phy)
  69. {
  70. return 0;
  71. }
  72. static int phy_axg_mipi_pcie_analog_exit(struct phy *phy)
  73. {
  74. return 0;
  75. }
  76. static const struct phy_ops phy_axg_mipi_pcie_analog_ops = {
  77. .init = phy_axg_mipi_pcie_analog_init,
  78. .exit = phy_axg_mipi_pcie_analog_exit,
  79. .power_on = phy_axg_mipi_pcie_analog_power_on,
  80. .power_off = phy_axg_mipi_pcie_analog_power_off,
  81. .owner = THIS_MODULE,
  82. };
  83. static struct phy *phy_axg_mipi_pcie_analog_xlate(struct device *dev,
  84. struct of_phandle_args *args)
  85. {
  86. struct phy_axg_mipi_pcie_analog_priv *priv = dev_get_drvdata(dev);
  87. unsigned int mode;
  88. if (args->args_count != 1) {
  89. dev_err(dev, "invalid number of arguments\n");
  90. return ERR_PTR(-EINVAL);
  91. }
  92. mode = args->args[0];
  93. /* MIPI mode is not supported yet */
  94. if (mode != PHY_TYPE_PCIE) {
  95. dev_err(dev, "invalid phy mode select argument\n");
  96. return ERR_PTR(-EINVAL);
  97. }
  98. priv->mode = mode;
  99. return priv->phy;
  100. }
  101. static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev)
  102. {
  103. struct phy_provider *phy;
  104. struct device *dev = &pdev->dev;
  105. struct phy_axg_mipi_pcie_analog_priv *priv;
  106. struct device_node *np = dev->of_node;
  107. struct regmap *map;
  108. struct resource *res;
  109. void __iomem *base;
  110. int ret;
  111. priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
  112. if (!priv)
  113. return -ENOMEM;
  114. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  115. base = devm_ioremap_resource(dev, res);
  116. if (IS_ERR(base)) {
  117. dev_err(dev, "failed to get regmap base\n");
  118. return PTR_ERR(base);
  119. }
  120. map = devm_regmap_init_mmio(dev, base,
  121. &phy_axg_mipi_pcie_analog_regmap_conf);
  122. if (IS_ERR(map)) {
  123. dev_err(dev, "failed to get HHI regmap\n");
  124. return PTR_ERR(map);
  125. }
  126. priv->regmap = map;
  127. priv->phy = devm_phy_create(dev, np, &phy_axg_mipi_pcie_analog_ops);
  128. if (IS_ERR(priv->phy)) {
  129. ret = PTR_ERR(priv->phy);
  130. if (ret != -EPROBE_DEFER)
  131. dev_err(dev, "failed to create PHY\n");
  132. return ret;
  133. }
  134. phy_set_drvdata(priv->phy, priv);
  135. dev_set_drvdata(dev, priv);
  136. phy = devm_of_phy_provider_register(dev,
  137. phy_axg_mipi_pcie_analog_xlate);
  138. return PTR_ERR_OR_ZERO(phy);
  139. }
  140. static const struct of_device_id phy_axg_mipi_pcie_analog_of_match[] = {
  141. {
  142. .compatible = "amlogic,axg-mipi-pcie-analog-phy",
  143. },
  144. { },
  145. };
  146. MODULE_DEVICE_TABLE(of, phy_axg_mipi_pcie_analog_of_match);
  147. static struct platform_driver phy_axg_mipi_pcie_analog_driver = {
  148. .probe = phy_axg_mipi_pcie_analog_probe,
  149. .driver = {
  150. .name = "phy-axg-mipi-pcie-analog",
  151. .of_match_table = phy_axg_mipi_pcie_analog_of_match,
  152. },
  153. };
  154. module_platform_driver(phy_axg_mipi_pcie_analog_driver);
  155. MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
  156. MODULE_DESCRIPTION("Amlogic AXG MIPI + PCIE analog PHY driver");
  157. MODULE_LICENSE("GPL v2");