arm_pmu.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #undef DEBUG
  3. /*
  4. * ARM performance counter support.
  5. *
  6. * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
  7. * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
  8. *
  9. * This code is based on the sparc64 perf event code, which is in turn based
  10. * on the x86 code.
  11. */
  12. #define pr_fmt(fmt) "hw perfevents: " fmt
  13. #include <linux/bitmap.h>
  14. #include <linux/cpumask.h>
  15. #include <linux/cpu_pm.h>
  16. #include <linux/export.h>
  17. #include <linux/kernel.h>
  18. #include <linux/perf/arm_pmu.h>
  19. #include <linux/slab.h>
  20. #include <linux/sched/clock.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/irq.h>
  23. #include <linux/irqdesc.h>
  24. #include <asm/irq_regs.h>
  25. static int armpmu_count_irq_users(const int irq);
  26. struct pmu_irq_ops {
  27. void (*enable_pmuirq)(unsigned int irq);
  28. void (*disable_pmuirq)(unsigned int irq);
  29. void (*free_pmuirq)(unsigned int irq, int cpu, void __percpu *devid);
  30. };
  31. static void armpmu_free_pmuirq(unsigned int irq, int cpu, void __percpu *devid)
  32. {
  33. free_irq(irq, per_cpu_ptr(devid, cpu));
  34. }
  35. static const struct pmu_irq_ops pmuirq_ops = {
  36. .enable_pmuirq = enable_irq,
  37. .disable_pmuirq = disable_irq_nosync,
  38. .free_pmuirq = armpmu_free_pmuirq
  39. };
  40. static void armpmu_free_pmunmi(unsigned int irq, int cpu, void __percpu *devid)
  41. {
  42. free_nmi(irq, per_cpu_ptr(devid, cpu));
  43. }
  44. static const struct pmu_irq_ops pmunmi_ops = {
  45. .enable_pmuirq = enable_nmi,
  46. .disable_pmuirq = disable_nmi_nosync,
  47. .free_pmuirq = armpmu_free_pmunmi
  48. };
  49. static void armpmu_enable_percpu_pmuirq(unsigned int irq)
  50. {
  51. enable_percpu_irq(irq, IRQ_TYPE_NONE);
  52. }
  53. static void armpmu_free_percpu_pmuirq(unsigned int irq, int cpu,
  54. void __percpu *devid)
  55. {
  56. if (armpmu_count_irq_users(irq) == 1)
  57. free_percpu_irq(irq, devid);
  58. }
  59. static const struct pmu_irq_ops percpu_pmuirq_ops = {
  60. .enable_pmuirq = armpmu_enable_percpu_pmuirq,
  61. .disable_pmuirq = disable_percpu_irq,
  62. .free_pmuirq = armpmu_free_percpu_pmuirq
  63. };
  64. static void armpmu_enable_percpu_pmunmi(unsigned int irq)
  65. {
  66. if (!prepare_percpu_nmi(irq))
  67. enable_percpu_nmi(irq, IRQ_TYPE_NONE);
  68. }
  69. static void armpmu_disable_percpu_pmunmi(unsigned int irq)
  70. {
  71. disable_percpu_nmi(irq);
  72. teardown_percpu_nmi(irq);
  73. }
  74. static void armpmu_free_percpu_pmunmi(unsigned int irq, int cpu,
  75. void __percpu *devid)
  76. {
  77. if (armpmu_count_irq_users(irq) == 1)
  78. free_percpu_nmi(irq, devid);
  79. }
  80. static const struct pmu_irq_ops percpu_pmunmi_ops = {
  81. .enable_pmuirq = armpmu_enable_percpu_pmunmi,
  82. .disable_pmuirq = armpmu_disable_percpu_pmunmi,
  83. .free_pmuirq = armpmu_free_percpu_pmunmi
  84. };
  85. static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
  86. static DEFINE_PER_CPU(int, cpu_irq);
  87. static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops);
  88. static bool has_nmi;
  89. static inline u64 arm_pmu_event_max_period(struct perf_event *event)
  90. {
  91. if (event->hw.flags & ARMPMU_EVT_64BIT)
  92. return GENMASK_ULL(63, 0);
  93. else
  94. return GENMASK_ULL(31, 0);
  95. }
  96. static int
  97. armpmu_map_cache_event(const unsigned (*cache_map)
  98. [PERF_COUNT_HW_CACHE_MAX]
  99. [PERF_COUNT_HW_CACHE_OP_MAX]
  100. [PERF_COUNT_HW_CACHE_RESULT_MAX],
  101. u64 config)
  102. {
  103. unsigned int cache_type, cache_op, cache_result, ret;
  104. cache_type = (config >> 0) & 0xff;
  105. if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  106. return -EINVAL;
  107. cache_op = (config >> 8) & 0xff;
  108. if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  109. return -EINVAL;
  110. cache_result = (config >> 16) & 0xff;
  111. if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  112. return -EINVAL;
  113. if (!cache_map)
  114. return -ENOENT;
  115. ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  116. if (ret == CACHE_OP_UNSUPPORTED)
  117. return -ENOENT;
  118. return ret;
  119. }
  120. static int
  121. armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  122. {
  123. int mapping;
  124. if (config >= PERF_COUNT_HW_MAX)
  125. return -EINVAL;
  126. if (!event_map)
  127. return -ENOENT;
  128. mapping = (*event_map)[config];
  129. return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  130. }
  131. static int
  132. armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  133. {
  134. return (int)(config & raw_event_mask);
  135. }
  136. int
  137. armpmu_map_event(struct perf_event *event,
  138. const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  139. const unsigned (*cache_map)
  140. [PERF_COUNT_HW_CACHE_MAX]
  141. [PERF_COUNT_HW_CACHE_OP_MAX]
  142. [PERF_COUNT_HW_CACHE_RESULT_MAX],
  143. u32 raw_event_mask)
  144. {
  145. u64 config = event->attr.config;
  146. int type = event->attr.type;
  147. if (type == event->pmu->type)
  148. return armpmu_map_raw_event(raw_event_mask, config);
  149. switch (type) {
  150. case PERF_TYPE_HARDWARE:
  151. return armpmu_map_hw_event(event_map, config);
  152. case PERF_TYPE_HW_CACHE:
  153. return armpmu_map_cache_event(cache_map, config);
  154. case PERF_TYPE_RAW:
  155. return armpmu_map_raw_event(raw_event_mask, config);
  156. }
  157. return -ENOENT;
  158. }
  159. int armpmu_event_set_period(struct perf_event *event)
  160. {
  161. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  162. struct hw_perf_event *hwc = &event->hw;
  163. s64 left = local64_read(&hwc->period_left);
  164. s64 period = hwc->sample_period;
  165. u64 max_period;
  166. int ret = 0;
  167. max_period = arm_pmu_event_max_period(event);
  168. if (unlikely(left <= -period)) {
  169. left = period;
  170. local64_set(&hwc->period_left, left);
  171. hwc->last_period = period;
  172. ret = 1;
  173. }
  174. if (unlikely(left <= 0)) {
  175. left += period;
  176. local64_set(&hwc->period_left, left);
  177. hwc->last_period = period;
  178. ret = 1;
  179. }
  180. /*
  181. * Limit the maximum period to prevent the counter value
  182. * from overtaking the one we are about to program. In
  183. * effect we are reducing max_period to account for
  184. * interrupt latency (and we are being very conservative).
  185. */
  186. if (left > (max_period >> 1))
  187. left = (max_period >> 1);
  188. local64_set(&hwc->prev_count, (u64)-left);
  189. armpmu->write_counter(event, (u64)(-left) & max_period);
  190. perf_event_update_userpage(event);
  191. return ret;
  192. }
  193. u64 armpmu_event_update(struct perf_event *event)
  194. {
  195. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  196. struct hw_perf_event *hwc = &event->hw;
  197. u64 delta, prev_raw_count, new_raw_count;
  198. u64 max_period = arm_pmu_event_max_period(event);
  199. again:
  200. prev_raw_count = local64_read(&hwc->prev_count);
  201. new_raw_count = armpmu->read_counter(event);
  202. if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  203. new_raw_count) != prev_raw_count)
  204. goto again;
  205. delta = (new_raw_count - prev_raw_count) & max_period;
  206. local64_add(delta, &event->count);
  207. local64_sub(delta, &hwc->period_left);
  208. return new_raw_count;
  209. }
  210. static void
  211. armpmu_read(struct perf_event *event)
  212. {
  213. armpmu_event_update(event);
  214. }
  215. static void
  216. armpmu_stop(struct perf_event *event, int flags)
  217. {
  218. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  219. struct hw_perf_event *hwc = &event->hw;
  220. /*
  221. * ARM pmu always has to update the counter, so ignore
  222. * PERF_EF_UPDATE, see comments in armpmu_start().
  223. */
  224. if (!(hwc->state & PERF_HES_STOPPED)) {
  225. armpmu->disable(event);
  226. armpmu_event_update(event);
  227. hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
  228. }
  229. }
  230. static void armpmu_start(struct perf_event *event, int flags)
  231. {
  232. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  233. struct hw_perf_event *hwc = &event->hw;
  234. /*
  235. * ARM pmu always has to reprogram the period, so ignore
  236. * PERF_EF_RELOAD, see the comment below.
  237. */
  238. if (flags & PERF_EF_RELOAD)
  239. WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
  240. hwc->state = 0;
  241. /*
  242. * Set the period again. Some counters can't be stopped, so when we
  243. * were stopped we simply disabled the IRQ source and the counter
  244. * may have been left counting. If we don't do this step then we may
  245. * get an interrupt too soon or *way* too late if the overflow has
  246. * happened since disabling.
  247. */
  248. armpmu_event_set_period(event);
  249. armpmu->enable(event);
  250. }
  251. static void
  252. armpmu_del(struct perf_event *event, int flags)
  253. {
  254. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  255. struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
  256. struct hw_perf_event *hwc = &event->hw;
  257. int idx = hwc->idx;
  258. armpmu_stop(event, PERF_EF_UPDATE);
  259. hw_events->events[idx] = NULL;
  260. armpmu->clear_event_idx(hw_events, event);
  261. perf_event_update_userpage(event);
  262. /* Clear the allocated counter */
  263. hwc->idx = -1;
  264. }
  265. static int
  266. armpmu_add(struct perf_event *event, int flags)
  267. {
  268. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  269. struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
  270. struct hw_perf_event *hwc = &event->hw;
  271. int idx;
  272. /* An event following a process won't be stopped earlier */
  273. if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
  274. return -ENOENT;
  275. /* If we don't have a space for the counter then finish early. */
  276. idx = armpmu->get_event_idx(hw_events, event);
  277. if (idx < 0)
  278. return idx;
  279. /*
  280. * If there is an event in the counter we are going to use then make
  281. * sure it is disabled.
  282. */
  283. event->hw.idx = idx;
  284. armpmu->disable(event);
  285. hw_events->events[idx] = event;
  286. hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
  287. if (flags & PERF_EF_START)
  288. armpmu_start(event, PERF_EF_RELOAD);
  289. /* Propagate our changes to the userspace mapping. */
  290. perf_event_update_userpage(event);
  291. return 0;
  292. }
  293. static int
  294. validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
  295. struct perf_event *event)
  296. {
  297. struct arm_pmu *armpmu;
  298. if (is_software_event(event))
  299. return 1;
  300. /*
  301. * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
  302. * core perf code won't check that the pmu->ctx == leader->ctx
  303. * until after pmu->event_init(event).
  304. */
  305. if (event->pmu != pmu)
  306. return 0;
  307. if (event->state < PERF_EVENT_STATE_OFF)
  308. return 1;
  309. if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
  310. return 1;
  311. armpmu = to_arm_pmu(event->pmu);
  312. return armpmu->get_event_idx(hw_events, event) >= 0;
  313. }
  314. static int
  315. validate_group(struct perf_event *event)
  316. {
  317. struct perf_event *sibling, *leader = event->group_leader;
  318. struct pmu_hw_events fake_pmu;
  319. /*
  320. * Initialise the fake PMU. We only need to populate the
  321. * used_mask for the purposes of validation.
  322. */
  323. memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
  324. if (!validate_event(event->pmu, &fake_pmu, leader))
  325. return -EINVAL;
  326. if (event == leader)
  327. return 0;
  328. for_each_sibling_event(sibling, leader) {
  329. if (!validate_event(event->pmu, &fake_pmu, sibling))
  330. return -EINVAL;
  331. }
  332. if (!validate_event(event->pmu, &fake_pmu, event))
  333. return -EINVAL;
  334. return 0;
  335. }
  336. static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
  337. {
  338. struct arm_pmu *armpmu;
  339. int ret;
  340. u64 start_clock, finish_clock;
  341. /*
  342. * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
  343. * the handlers expect a struct arm_pmu*. The percpu_irq framework will
  344. * do any necessary shifting, we just need to perform the first
  345. * dereference.
  346. */
  347. armpmu = *(void **)dev;
  348. if (WARN_ON_ONCE(!armpmu))
  349. return IRQ_NONE;
  350. start_clock = sched_clock();
  351. ret = armpmu->handle_irq(armpmu);
  352. finish_clock = sched_clock();
  353. perf_sample_event_took(finish_clock - start_clock);
  354. return ret;
  355. }
  356. static int
  357. __hw_perf_event_init(struct perf_event *event)
  358. {
  359. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  360. struct hw_perf_event *hwc = &event->hw;
  361. int mapping;
  362. hwc->flags = 0;
  363. mapping = armpmu->map_event(event);
  364. if (mapping < 0) {
  365. pr_debug("event %x:%llx not supported\n", event->attr.type,
  366. event->attr.config);
  367. return mapping;
  368. }
  369. /*
  370. * We don't assign an index until we actually place the event onto
  371. * hardware. Use -1 to signify that we haven't decided where to put it
  372. * yet. For SMP systems, each core has it's own PMU so we can't do any
  373. * clever allocation or constraints checking at this point.
  374. */
  375. hwc->idx = -1;
  376. hwc->config_base = 0;
  377. hwc->config = 0;
  378. hwc->event_base = 0;
  379. /*
  380. * Check whether we need to exclude the counter from certain modes.
  381. */
  382. if (armpmu->set_event_filter &&
  383. armpmu->set_event_filter(hwc, &event->attr)) {
  384. pr_debug("ARM performance counters do not support "
  385. "mode exclusion\n");
  386. return -EOPNOTSUPP;
  387. }
  388. /*
  389. * Store the event encoding into the config_base field.
  390. */
  391. hwc->config_base |= (unsigned long)mapping;
  392. if (!is_sampling_event(event)) {
  393. /*
  394. * For non-sampling runs, limit the sample_period to half
  395. * of the counter width. That way, the new counter value
  396. * is far less likely to overtake the previous one unless
  397. * you have some serious IRQ latency issues.
  398. */
  399. hwc->sample_period = arm_pmu_event_max_period(event) >> 1;
  400. hwc->last_period = hwc->sample_period;
  401. local64_set(&hwc->period_left, hwc->sample_period);
  402. }
  403. return validate_group(event);
  404. }
  405. static int armpmu_event_init(struct perf_event *event)
  406. {
  407. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  408. /*
  409. * Reject CPU-affine events for CPUs that are of a different class to
  410. * that which this PMU handles. Process-following events (where
  411. * event->cpu == -1) can be migrated between CPUs, and thus we have to
  412. * reject them later (in armpmu_add) if they're scheduled on a
  413. * different class of CPU.
  414. */
  415. if (event->cpu != -1 &&
  416. !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
  417. return -ENOENT;
  418. /* does not support taken branch sampling */
  419. if (has_branch_stack(event))
  420. return -EOPNOTSUPP;
  421. if (armpmu->map_event(event) == -ENOENT)
  422. return -ENOENT;
  423. return __hw_perf_event_init(event);
  424. }
  425. static void armpmu_enable(struct pmu *pmu)
  426. {
  427. struct arm_pmu *armpmu = to_arm_pmu(pmu);
  428. struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
  429. int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
  430. /* For task-bound events we may be called on other CPUs */
  431. if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
  432. return;
  433. if (enabled)
  434. armpmu->start(armpmu);
  435. }
  436. static void armpmu_disable(struct pmu *pmu)
  437. {
  438. struct arm_pmu *armpmu = to_arm_pmu(pmu);
  439. /* For task-bound events we may be called on other CPUs */
  440. if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
  441. return;
  442. armpmu->stop(armpmu);
  443. }
  444. /*
  445. * In heterogeneous systems, events are specific to a particular
  446. * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
  447. * the same microarchitecture.
  448. */
  449. static int armpmu_filter_match(struct perf_event *event)
  450. {
  451. struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  452. unsigned int cpu = smp_processor_id();
  453. int ret;
  454. ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
  455. if (ret && armpmu->filter_match)
  456. return armpmu->filter_match(event);
  457. return ret;
  458. }
  459. static ssize_t armpmu_cpumask_show(struct device *dev,
  460. struct device_attribute *attr, char *buf)
  461. {
  462. struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
  463. return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
  464. }
  465. static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
  466. static struct attribute *armpmu_common_attrs[] = {
  467. &dev_attr_cpus.attr,
  468. NULL,
  469. };
  470. static struct attribute_group armpmu_common_attr_group = {
  471. .attrs = armpmu_common_attrs,
  472. };
  473. /* Set at runtime when we know what CPU type we are. */
  474. static struct arm_pmu *__oprofile_cpu_pmu;
  475. /*
  476. * Despite the names, these two functions are CPU-specific and are used
  477. * by the OProfile/perf code.
  478. */
  479. const char *perf_pmu_name(void)
  480. {
  481. if (!__oprofile_cpu_pmu)
  482. return NULL;
  483. return __oprofile_cpu_pmu->name;
  484. }
  485. EXPORT_SYMBOL_GPL(perf_pmu_name);
  486. int perf_num_counters(void)
  487. {
  488. int max_events = 0;
  489. if (__oprofile_cpu_pmu != NULL)
  490. max_events = __oprofile_cpu_pmu->num_events;
  491. return max_events;
  492. }
  493. EXPORT_SYMBOL_GPL(perf_num_counters);
  494. static int armpmu_count_irq_users(const int irq)
  495. {
  496. int cpu, count = 0;
  497. for_each_possible_cpu(cpu) {
  498. if (per_cpu(cpu_irq, cpu) == irq)
  499. count++;
  500. }
  501. return count;
  502. }
  503. static const struct pmu_irq_ops *armpmu_find_irq_ops(int irq)
  504. {
  505. const struct pmu_irq_ops *ops = NULL;
  506. int cpu;
  507. for_each_possible_cpu(cpu) {
  508. if (per_cpu(cpu_irq, cpu) != irq)
  509. continue;
  510. ops = per_cpu(cpu_irq_ops, cpu);
  511. if (ops)
  512. break;
  513. }
  514. return ops;
  515. }
  516. void armpmu_free_irq(int irq, int cpu)
  517. {
  518. if (per_cpu(cpu_irq, cpu) == 0)
  519. return;
  520. if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
  521. return;
  522. per_cpu(cpu_irq_ops, cpu)->free_pmuirq(irq, cpu, &cpu_armpmu);
  523. per_cpu(cpu_irq, cpu) = 0;
  524. per_cpu(cpu_irq_ops, cpu) = NULL;
  525. }
  526. int armpmu_request_irq(int irq, int cpu)
  527. {
  528. int err = 0;
  529. const irq_handler_t handler = armpmu_dispatch_irq;
  530. const struct pmu_irq_ops *irq_ops;
  531. if (!irq)
  532. return 0;
  533. if (!irq_is_percpu_devid(irq)) {
  534. unsigned long irq_flags;
  535. err = irq_force_affinity(irq, cpumask_of(cpu));
  536. if (err && num_possible_cpus() > 1) {
  537. pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
  538. irq, cpu);
  539. goto err_out;
  540. }
  541. irq_flags = IRQF_PERCPU |
  542. IRQF_NOBALANCING |
  543. IRQF_NO_THREAD;
  544. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  545. err = request_nmi(irq, handler, irq_flags, "arm-pmu",
  546. per_cpu_ptr(&cpu_armpmu, cpu));
  547. /* If cannot get an NMI, get a normal interrupt */
  548. if (err) {
  549. err = request_irq(irq, handler, irq_flags, "arm-pmu",
  550. per_cpu_ptr(&cpu_armpmu, cpu));
  551. irq_ops = &pmuirq_ops;
  552. } else {
  553. has_nmi = true;
  554. irq_ops = &pmunmi_ops;
  555. }
  556. } else if (armpmu_count_irq_users(irq) == 0) {
  557. err = request_percpu_nmi(irq, handler, "arm-pmu", &cpu_armpmu);
  558. /* If cannot get an NMI, get a normal interrupt */
  559. if (err) {
  560. err = request_percpu_irq(irq, handler, "arm-pmu",
  561. &cpu_armpmu);
  562. irq_ops = &percpu_pmuirq_ops;
  563. } else {
  564. has_nmi= true;
  565. irq_ops = &percpu_pmunmi_ops;
  566. }
  567. } else {
  568. /* Per cpudevid irq was already requested by another CPU */
  569. irq_ops = armpmu_find_irq_ops(irq);
  570. if (WARN_ON(!irq_ops))
  571. err = -EINVAL;
  572. }
  573. if (err)
  574. goto err_out;
  575. per_cpu(cpu_irq, cpu) = irq;
  576. per_cpu(cpu_irq_ops, cpu) = irq_ops;
  577. return 0;
  578. err_out:
  579. pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
  580. return err;
  581. }
  582. static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
  583. {
  584. struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
  585. return per_cpu(hw_events->irq, cpu);
  586. }
  587. /*
  588. * PMU hardware loses all context when a CPU goes offline.
  589. * When a CPU is hotplugged back in, since some hardware registers are
  590. * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
  591. * junk values out of them.
  592. */
  593. static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
  594. {
  595. struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
  596. int irq;
  597. if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
  598. return 0;
  599. if (pmu->reset)
  600. pmu->reset(pmu);
  601. per_cpu(cpu_armpmu, cpu) = pmu;
  602. irq = armpmu_get_cpu_irq(pmu, cpu);
  603. if (irq)
  604. per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq);
  605. return 0;
  606. }
  607. static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
  608. {
  609. struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
  610. int irq;
  611. if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
  612. return 0;
  613. irq = armpmu_get_cpu_irq(pmu, cpu);
  614. if (irq)
  615. per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq);
  616. per_cpu(cpu_armpmu, cpu) = NULL;
  617. return 0;
  618. }
  619. #ifdef CONFIG_CPU_PM
  620. static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
  621. {
  622. struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
  623. struct perf_event *event;
  624. int idx;
  625. for (idx = 0; idx < armpmu->num_events; idx++) {
  626. event = hw_events->events[idx];
  627. if (!event)
  628. continue;
  629. switch (cmd) {
  630. case CPU_PM_ENTER:
  631. /*
  632. * Stop and update the counter
  633. */
  634. armpmu_stop(event, PERF_EF_UPDATE);
  635. break;
  636. case CPU_PM_EXIT:
  637. case CPU_PM_ENTER_FAILED:
  638. /*
  639. * Restore and enable the counter.
  640. * armpmu_start() indirectly calls
  641. *
  642. * perf_event_update_userpage()
  643. *
  644. * that requires RCU read locking to be functional,
  645. * wrap the call within RCU_NONIDLE to make the
  646. * RCU subsystem aware this cpu is not idle from
  647. * an RCU perspective for the armpmu_start() call
  648. * duration.
  649. */
  650. RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
  651. break;
  652. default:
  653. break;
  654. }
  655. }
  656. }
  657. static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
  658. void *v)
  659. {
  660. struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
  661. struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
  662. int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
  663. if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
  664. return NOTIFY_DONE;
  665. /*
  666. * Always reset the PMU registers on power-up even if
  667. * there are no events running.
  668. */
  669. if (cmd == CPU_PM_EXIT && armpmu->reset)
  670. armpmu->reset(armpmu);
  671. if (!enabled)
  672. return NOTIFY_OK;
  673. switch (cmd) {
  674. case CPU_PM_ENTER:
  675. armpmu->stop(armpmu);
  676. cpu_pm_pmu_setup(armpmu, cmd);
  677. break;
  678. case CPU_PM_EXIT:
  679. case CPU_PM_ENTER_FAILED:
  680. cpu_pm_pmu_setup(armpmu, cmd);
  681. armpmu->start(armpmu);
  682. break;
  683. default:
  684. return NOTIFY_DONE;
  685. }
  686. return NOTIFY_OK;
  687. }
  688. static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
  689. {
  690. cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
  691. return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
  692. }
  693. static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
  694. {
  695. cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
  696. }
  697. #else
  698. static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
  699. static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
  700. #endif
  701. static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
  702. {
  703. int err;
  704. err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
  705. &cpu_pmu->node);
  706. if (err)
  707. goto out;
  708. err = cpu_pm_pmu_register(cpu_pmu);
  709. if (err)
  710. goto out_unregister;
  711. return 0;
  712. out_unregister:
  713. cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
  714. &cpu_pmu->node);
  715. out:
  716. return err;
  717. }
  718. static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
  719. {
  720. cpu_pm_pmu_unregister(cpu_pmu);
  721. cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
  722. &cpu_pmu->node);
  723. }
  724. static struct arm_pmu *__armpmu_alloc(gfp_t flags)
  725. {
  726. struct arm_pmu *pmu;
  727. int cpu;
  728. pmu = kzalloc(sizeof(*pmu), flags);
  729. if (!pmu) {
  730. pr_info("failed to allocate PMU device!\n");
  731. goto out;
  732. }
  733. pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
  734. if (!pmu->hw_events) {
  735. pr_info("failed to allocate per-cpu PMU data.\n");
  736. goto out_free_pmu;
  737. }
  738. pmu->pmu = (struct pmu) {
  739. .pmu_enable = armpmu_enable,
  740. .pmu_disable = armpmu_disable,
  741. .event_init = armpmu_event_init,
  742. .add = armpmu_add,
  743. .del = armpmu_del,
  744. .start = armpmu_start,
  745. .stop = armpmu_stop,
  746. .read = armpmu_read,
  747. .filter_match = armpmu_filter_match,
  748. .attr_groups = pmu->attr_groups,
  749. /*
  750. * This is a CPU PMU potentially in a heterogeneous
  751. * configuration (e.g. big.LITTLE). This is not an uncore PMU,
  752. * and we have taken ctx sharing into account (e.g. with our
  753. * pmu::filter_match callback and pmu::event_init group
  754. * validation).
  755. */
  756. .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
  757. };
  758. pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
  759. &armpmu_common_attr_group;
  760. for_each_possible_cpu(cpu) {
  761. struct pmu_hw_events *events;
  762. events = per_cpu_ptr(pmu->hw_events, cpu);
  763. raw_spin_lock_init(&events->pmu_lock);
  764. events->percpu_pmu = pmu;
  765. }
  766. return pmu;
  767. out_free_pmu:
  768. kfree(pmu);
  769. out:
  770. return NULL;
  771. }
  772. struct arm_pmu *armpmu_alloc(void)
  773. {
  774. return __armpmu_alloc(GFP_KERNEL);
  775. }
  776. struct arm_pmu *armpmu_alloc_atomic(void)
  777. {
  778. return __armpmu_alloc(GFP_ATOMIC);
  779. }
  780. void armpmu_free(struct arm_pmu *pmu)
  781. {
  782. free_percpu(pmu->hw_events);
  783. kfree(pmu);
  784. }
  785. int armpmu_register(struct arm_pmu *pmu)
  786. {
  787. int ret;
  788. ret = cpu_pmu_init(pmu);
  789. if (ret)
  790. return ret;
  791. if (!pmu->set_event_filter)
  792. pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
  793. ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
  794. if (ret)
  795. goto out_destroy;
  796. if (!__oprofile_cpu_pmu)
  797. __oprofile_cpu_pmu = pmu;
  798. pr_info("enabled with %s PMU driver, %d counters available%s\n",
  799. pmu->name, pmu->num_events,
  800. has_nmi ? ", using NMIs" : "");
  801. return 0;
  802. out_destroy:
  803. cpu_pmu_destroy(pmu);
  804. return ret;
  805. }
  806. static int arm_pmu_hp_init(void)
  807. {
  808. int ret;
  809. ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
  810. "perf/arm/pmu:starting",
  811. arm_perf_starting_cpu,
  812. arm_perf_teardown_cpu);
  813. if (ret)
  814. pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
  815. ret);
  816. return ret;
  817. }
  818. subsys_initcall(arm_pmu_hp_init);