ricoh.h 7.6 KB

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  1. /*
  2. * ricoh.h 1.9 1999/10/25 20:03:34
  3. *
  4. * The contents of this file are subject to the Mozilla Public License
  5. * Version 1.1 (the "License"); you may not use this file except in
  6. * compliance with the License. You may obtain a copy of the License
  7. * at http://www.mozilla.org/MPL/
  8. *
  9. * Software distributed under the License is distributed on an "AS IS"
  10. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11. * the License for the specific language governing rights and
  12. * limitations under the License.
  13. *
  14. * The initial developer of the original code is David A. Hinds
  15. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  16. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  17. *
  18. * Alternatively, the contents of this file may be used under the
  19. * terms of the GNU General Public License version 2 (the "GPL"), in which
  20. * case the provisions of the GPL are applicable instead of the
  21. * above. If you wish to allow the use of your version of this file
  22. * only under the terms of the GPL and not to allow others to use
  23. * your version of this file under the MPL, indicate your decision by
  24. * deleting the provisions above and replace them with the notice and
  25. * other provisions required by the GPL. If you do not delete the
  26. * provisions above, a recipient may use your version of this file
  27. * under either the MPL or the GPL.
  28. */
  29. #ifndef _LINUX_RICOH_H
  30. #define _LINUX_RICOH_H
  31. #define RF5C_MODE_CTL 0x1f /* Mode control */
  32. #define RF5C_PWR_CTL 0x2f /* Mixed voltage control */
  33. #define RF5C_CHIP_ID 0x3a /* Chip identification */
  34. #define RF5C_MODE_CTL_3 0x3b /* Mode control 3 */
  35. /* I/O window address offset */
  36. #define RF5C_IO_OFF(w) (0x36+((w)<<1))
  37. /* Flags for RF5C_MODE_CTL */
  38. #define RF5C_MODE_ATA 0x01 /* ATA mode */
  39. #define RF5C_MODE_LED_ENA 0x02 /* IRQ 12 is LED */
  40. #define RF5C_MODE_CA21 0x04
  41. #define RF5C_MODE_CA22 0x08
  42. #define RF5C_MODE_CA23 0x10
  43. #define RF5C_MODE_CA24 0x20
  44. #define RF5C_MODE_CA25 0x40
  45. #define RF5C_MODE_3STATE_BIT7 0x80
  46. /* Flags for RF5C_PWR_CTL */
  47. #define RF5C_PWR_VCC_3V 0x01
  48. #define RF5C_PWR_IREQ_HIGH 0x02
  49. #define RF5C_PWR_INPACK_ENA 0x04
  50. #define RF5C_PWR_5V_DET 0x08
  51. #define RF5C_PWR_TC_SEL 0x10 /* Terminal Count: irq 11 or 15 */
  52. #define RF5C_PWR_DREQ_LOW 0x20
  53. #define RF5C_PWR_DREQ_OFF 0x00 /* DREQ steering control */
  54. #define RF5C_PWR_DREQ_INPACK 0x40
  55. #define RF5C_PWR_DREQ_SPKR 0x80
  56. #define RF5C_PWR_DREQ_IOIS16 0xc0
  57. /* Values for RF5C_CHIP_ID */
  58. #define RF5C_CHIP_RF5C296 0x32
  59. #define RF5C_CHIP_RF5C396 0xb2
  60. /* Flags for RF5C_MODE_CTL_3 */
  61. #define RF5C_MCTL3_DISABLE 0x01 /* Disable PCMCIA interface */
  62. #define RF5C_MCTL3_DMA_ENA 0x02
  63. /* Register definitions for Ricoh PCI-to-CardBus bridges */
  64. /* Extra bits in CB_BRIDGE_CONTROL */
  65. #define RL5C46X_BCR_3E0_ENA 0x0800
  66. #define RL5C46X_BCR_3E2_ENA 0x1000
  67. /* Bridge Configuration Register */
  68. #define RL5C4XX_CONFIG 0x80 /* 16 bit */
  69. #define RL5C4XX_CONFIG_IO_1_MODE 0x0200
  70. #define RL5C4XX_CONFIG_IO_0_MODE 0x0100
  71. #define RL5C4XX_CONFIG_PREFETCH 0x0001
  72. /* Misc Control Register */
  73. #define RL5C4XX_MISC 0x0082 /* 16 bit */
  74. #define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002
  75. #define RL5C4XX_MISC_VCCEN_POL 0x0100
  76. #define RL5C4XX_MISC_VPPEN_POL 0x0200
  77. #define RL5C46X_MISC_SUSPEND 0x0001
  78. #define RL5C46X_MISC_PWR_SAVE_2 0x0004
  79. #define RL5C46X_MISC_IFACE_BUSY 0x0008
  80. #define RL5C46X_MISC_B_LOCK 0x0010
  81. #define RL5C46X_MISC_A_LOCK 0x0020
  82. #define RL5C46X_MISC_PCI_LOCK 0x0040
  83. #define RL5C47X_MISC_IFACE_BUSY 0x0004
  84. #define RL5C47X_MISC_PCI_INT_MASK 0x0018
  85. #define RL5C47X_MISC_PCI_INT_DIS 0x0020
  86. #define RL5C47X_MISC_SUBSYS_WR 0x0040
  87. #define RL5C47X_MISC_SRIRQ_ENA 0x0080
  88. #define RL5C47X_MISC_5V_DISABLE 0x0400
  89. #define RL5C47X_MISC_LED_POL 0x0800
  90. /* 16-bit Interface Control Register */
  91. #define RL5C4XX_16BIT_CTL 0x0084 /* 16 bit */
  92. #define RL5C4XX_16CTL_IO_TIMING 0x0100
  93. #define RL5C4XX_16CTL_MEM_TIMING 0x0200
  94. #define RL5C46X_16CTL_LEVEL_1 0x0010
  95. #define RL5C46X_16CTL_LEVEL_2 0x0020
  96. /* 16-bit IO and memory timing registers */
  97. #define RL5C4XX_16BIT_IO_0 0x0088 /* 16 bit */
  98. #define RL5C4XX_16BIT_MEM_0 0x008a /* 16 bit */
  99. #define RL5C4XX_SETUP_MASK 0x0007
  100. #define RL5C4XX_SETUP_SHIFT 0
  101. #define RL5C4XX_CMD_MASK 0x01f0
  102. #define RL5C4XX_CMD_SHIFT 4
  103. #define RL5C4XX_HOLD_MASK 0x1c00
  104. #define RL5C4XX_HOLD_SHIFT 10
  105. #define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */
  106. #define RL5C4XX_ZV_ENABLE 0x08
  107. /* Misc Control 3 Register */
  108. #define RL5C4XX_MISC3 0x00A2 /* 16 bit */
  109. #define RL5C47X_MISC3_CB_CLKRUN_DIS BIT(1)
  110. #ifdef __YENTA_H
  111. #define rl_misc(socket) ((socket)->private[0])
  112. #define rl_ctl(socket) ((socket)->private[1])
  113. #define rl_io(socket) ((socket)->private[2])
  114. #define rl_mem(socket) ((socket)->private[3])
  115. #define rl_config(socket) ((socket)->private[4])
  116. static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff)
  117. {
  118. u8 reg;
  119. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  120. reg = config_readb(socket, RL5C4XX_MISC_CONTROL);
  121. if (onoff)
  122. /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
  123. reg |= RL5C4XX_ZV_ENABLE;
  124. else
  125. reg &= ~RL5C4XX_ZV_ENABLE;
  126. config_writeb(socket, RL5C4XX_MISC_CONTROL, reg);
  127. }
  128. static void ricoh_set_zv(struct yenta_socket *socket)
  129. {
  130. if(socket->dev->vendor == PCI_VENDOR_ID_RICOH)
  131. {
  132. switch(socket->dev->device)
  133. {
  134. /* There may be more .. */
  135. case PCI_DEVICE_ID_RICOH_RL5C478:
  136. socket->socket.zoom_video = ricoh_zoom_video;
  137. break;
  138. }
  139. }
  140. }
  141. static void ricoh_set_clkrun(struct yenta_socket *socket, bool quiet)
  142. {
  143. u16 misc3;
  144. /*
  145. * RL5C475II likely has this setting, too, however no datasheet
  146. * is publicly available for this chip
  147. */
  148. if (socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C476 &&
  149. socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C478)
  150. return;
  151. if (socket->dev->revision < 0x80)
  152. return;
  153. misc3 = config_readw(socket, RL5C4XX_MISC3);
  154. if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) {
  155. if (!quiet)
  156. dev_dbg(&socket->dev->dev,
  157. "CLKRUN feature already disabled\n");
  158. } else if (disable_clkrun) {
  159. if (!quiet)
  160. dev_info(&socket->dev->dev,
  161. "Disabling CLKRUN feature\n");
  162. misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS;
  163. config_writew(socket, RL5C4XX_MISC3, misc3);
  164. }
  165. }
  166. static void ricoh_save_state(struct yenta_socket *socket)
  167. {
  168. rl_misc(socket) = config_readw(socket, RL5C4XX_MISC);
  169. rl_ctl(socket) = config_readw(socket, RL5C4XX_16BIT_CTL);
  170. rl_io(socket) = config_readw(socket, RL5C4XX_16BIT_IO_0);
  171. rl_mem(socket) = config_readw(socket, RL5C4XX_16BIT_MEM_0);
  172. rl_config(socket) = config_readw(socket, RL5C4XX_CONFIG);
  173. }
  174. static void ricoh_restore_state(struct yenta_socket *socket)
  175. {
  176. config_writew(socket, RL5C4XX_MISC, rl_misc(socket));
  177. config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket));
  178. config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket));
  179. config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket));
  180. config_writew(socket, RL5C4XX_CONFIG, rl_config(socket));
  181. ricoh_set_clkrun(socket, true);
  182. }
  183. /*
  184. * Magic Ricoh initialization code..
  185. */
  186. static int ricoh_override(struct yenta_socket *socket)
  187. {
  188. u16 config, ctl;
  189. config = config_readw(socket, RL5C4XX_CONFIG);
  190. /* Set the default timings, don't trust the original values */
  191. ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
  192. if(socket->dev->device < PCI_DEVICE_ID_RICOH_RL5C475) {
  193. ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
  194. } else {
  195. config |= RL5C4XX_CONFIG_PREFETCH;
  196. }
  197. config_writew(socket, RL5C4XX_16BIT_CTL, ctl);
  198. config_writew(socket, RL5C4XX_CONFIG, config);
  199. ricoh_set_zv(socket);
  200. ricoh_set_clkrun(socket, false);
  201. return 0;
  202. }
  203. #endif /* CONFIG_CARDBUS */
  204. #endif /* _LINUX_RICOH_H */