pci-bridge-emul.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell
  4. *
  5. * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  6. *
  7. * This file helps PCI controller drivers implement a fake root port
  8. * PCI bridge when the HW doesn't provide such a root port PCI
  9. * bridge.
  10. *
  11. * It emulates a PCI bridge by providing a fake PCI configuration
  12. * space (and optionally a PCIe capability configuration space) in
  13. * memory. By default the read/write operations simply read and update
  14. * this fake configuration space in memory. However, PCI controller
  15. * drivers can provide through the 'struct pci_sw_bridge_ops'
  16. * structure a set of operations to override or complement this
  17. * default behavior.
  18. */
  19. #include <linux/pci.h>
  20. #include "pci-bridge-emul.h"
  21. #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
  22. #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
  23. #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
  24. #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
  25. /**
  26. * struct pci_bridge_reg_behavior - register bits behaviors
  27. * @ro: Read-Only bits
  28. * @rw: Read-Write bits
  29. * @w1c: Write-1-to-Clear bits
  30. *
  31. * Reads and Writes will be filtered by specified behavior. All other bits not
  32. * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
  33. * "Reserved register fields must be read only and must return 0 (all 0's for
  34. * multi-bit fields) when read".
  35. */
  36. struct pci_bridge_reg_behavior {
  37. /* Read-only bits */
  38. u32 ro;
  39. /* Read-write bits */
  40. u32 rw;
  41. /* Write-1-to-clear bits */
  42. u32 w1c;
  43. };
  44. static const
  45. struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
  46. [PCI_VENDOR_ID / 4] = { .ro = ~0 },
  47. [PCI_COMMAND / 4] = {
  48. .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  49. PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
  50. PCI_COMMAND_SERR),
  51. .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
  52. PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
  53. PCI_COMMAND_FAST_BACK) |
  54. (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
  55. PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
  56. .w1c = PCI_STATUS_ERROR_BITS << 16,
  57. },
  58. [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
  59. /*
  60. * Cache Line Size register: implement as read-only, we do not
  61. * pretend implementing "Memory Write and Invalidate"
  62. * transactions"
  63. *
  64. * Latency Timer Register: implemented as read-only, as "A
  65. * bridge that is not capable of a burst transfer of more than
  66. * two data phases on its primary interface is permitted to
  67. * hardwire the Latency Timer to a value of 16 or less"
  68. *
  69. * Header Type: always read-only
  70. *
  71. * BIST register: implemented as read-only, as "A bridge that
  72. * does not support BIST must implement this register as a
  73. * read-only register that returns 0 when read"
  74. */
  75. [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
  76. /*
  77. * Base Address registers not used must be implemented as
  78. * read-only registers that return 0 when read.
  79. */
  80. [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
  81. [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
  82. [PCI_PRIMARY_BUS / 4] = {
  83. /* Primary, secondary and subordinate bus are RW */
  84. .rw = GENMASK(24, 0),
  85. /* Secondary latency is read-only */
  86. .ro = GENMASK(31, 24),
  87. },
  88. [PCI_IO_BASE / 4] = {
  89. /* The high four bits of I/O base/limit are RW */
  90. .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
  91. /* The low four bits of I/O base/limit are RO */
  92. .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
  93. PCI_STATUS_DEVSEL_MASK) << 16) |
  94. GENMASK(11, 8) | GENMASK(3, 0)),
  95. .w1c = PCI_STATUS_ERROR_BITS << 16,
  96. },
  97. [PCI_MEMORY_BASE / 4] = {
  98. /* The high 12-bits of mem base/limit are RW */
  99. .rw = GENMASK(31, 20) | GENMASK(15, 4),
  100. /* The low four bits of mem base/limit are RO */
  101. .ro = GENMASK(19, 16) | GENMASK(3, 0),
  102. },
  103. [PCI_PREF_MEMORY_BASE / 4] = {
  104. /* The high 12-bits of pref mem base/limit are RW */
  105. .rw = GENMASK(31, 20) | GENMASK(15, 4),
  106. /* The low four bits of pref mem base/limit are RO */
  107. .ro = GENMASK(19, 16) | GENMASK(3, 0),
  108. },
  109. [PCI_PREF_BASE_UPPER32 / 4] = {
  110. .rw = ~0,
  111. },
  112. [PCI_PREF_LIMIT_UPPER32 / 4] = {
  113. .rw = ~0,
  114. },
  115. [PCI_IO_BASE_UPPER16 / 4] = {
  116. .rw = ~0,
  117. },
  118. [PCI_CAPABILITY_LIST / 4] = {
  119. .ro = GENMASK(7, 0),
  120. },
  121. /*
  122. * If expansion ROM is unsupported then ROM Base Address register must
  123. * be implemented as read-only register that return 0 when read, same
  124. * as for unused Base Address registers.
  125. */
  126. [PCI_ROM_ADDRESS1 / 4] = {
  127. .ro = ~0,
  128. },
  129. /*
  130. * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
  131. * are RO, and bridge control (31:16) are a mix of RW, RO,
  132. * reserved and W1C bits
  133. */
  134. [PCI_INTERRUPT_LINE / 4] = {
  135. /* Interrupt line is RW */
  136. .rw = (GENMASK(7, 0) |
  137. ((PCI_BRIDGE_CTL_PARITY |
  138. PCI_BRIDGE_CTL_SERR |
  139. PCI_BRIDGE_CTL_ISA |
  140. PCI_BRIDGE_CTL_VGA |
  141. PCI_BRIDGE_CTL_MASTER_ABORT |
  142. PCI_BRIDGE_CTL_BUS_RESET |
  143. BIT(8) | BIT(9) | BIT(11)) << 16)),
  144. /* Interrupt pin is RO */
  145. .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
  146. .w1c = BIT(10) << 16,
  147. },
  148. };
  149. static const
  150. struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
  151. [PCI_CAP_LIST_ID / 4] = {
  152. /*
  153. * Capability ID, Next Capability Pointer and
  154. * bits [14:0] of Capabilities register are all read-only.
  155. * Bit 15 of Capabilities register is reserved.
  156. */
  157. .ro = GENMASK(30, 0),
  158. },
  159. [PCI_EXP_DEVCAP / 4] = {
  160. /*
  161. * Bits [31:29] and [17:16] are reserved.
  162. * Bits [27:18] are reserved for non-upstream ports.
  163. * Bits 28 and [14:6] are reserved for non-endpoint devices.
  164. * Other bits are read-only.
  165. */
  166. .ro = BIT(15) | GENMASK(5, 0),
  167. },
  168. [PCI_EXP_DEVCTL / 4] = {
  169. /*
  170. * Device control register is RW, except bit 15 which is
  171. * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
  172. */
  173. .rw = GENMASK(14, 0),
  174. /*
  175. * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
  176. * the rest is reserved. Also bit 6 is reserved for non-upstream
  177. * ports.
  178. */
  179. .w1c = GENMASK(3, 0) << 16,
  180. .ro = GENMASK(5, 4) << 16,
  181. },
  182. [PCI_EXP_LNKCAP / 4] = {
  183. /*
  184. * All bits are RO, except bit 23 which is reserved and
  185. * bit 18 which is reserved for non-upstream ports.
  186. */
  187. .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
  188. },
  189. [PCI_EXP_LNKCTL / 4] = {
  190. /*
  191. * Link control has bits [15:14], [11:3] and [1:0] RW, the
  192. * rest is reserved. Bit 8 is reserved for non-upstream ports.
  193. *
  194. * Link status has bits [13:0] RO, and bits [15:14]
  195. * W1C.
  196. */
  197. .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
  198. .ro = GENMASK(13, 0) << 16,
  199. .w1c = GENMASK(15, 14) << 16,
  200. },
  201. [PCI_EXP_SLTCAP / 4] = {
  202. .ro = ~0,
  203. },
  204. [PCI_EXP_SLTCTL / 4] = {
  205. /*
  206. * Slot control has bits [14:0] RW, the rest is
  207. * reserved.
  208. *
  209. * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
  210. * rest is reserved.
  211. */
  212. .rw = GENMASK(14, 0),
  213. .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
  214. PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
  215. PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
  216. .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
  217. PCI_EXP_SLTSTA_EIS) << 16,
  218. },
  219. [PCI_EXP_RTCTL / 4] = {
  220. /*
  221. * Root control has bits [4:0] RW, the rest is
  222. * reserved.
  223. *
  224. * Root capabilities has bit 0 RO, the rest is reserved.
  225. */
  226. .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
  227. PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
  228. PCI_EXP_RTCTL_CRSSVE),
  229. .ro = PCI_EXP_RTCAP_CRSVIS << 16,
  230. },
  231. [PCI_EXP_RTSTA / 4] = {
  232. /*
  233. * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
  234. * is reserved.
  235. */
  236. .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
  237. .w1c = PCI_EXP_RTSTA_PME,
  238. },
  239. };
  240. /*
  241. * Initialize a pci_bridge_emul structure to represent a fake PCI
  242. * bridge configuration space. The caller needs to have initialized
  243. * the PCI configuration space with whatever values make sense
  244. * (typically at least vendor, device, revision), the ->ops pointer,
  245. * and optionally ->data and ->has_pcie.
  246. */
  247. int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
  248. unsigned int flags)
  249. {
  250. BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
  251. bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
  252. bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
  253. bridge->conf.cache_line_size = 0x10;
  254. bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
  255. bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
  256. sizeof(pci_regs_behavior),
  257. GFP_KERNEL);
  258. if (!bridge->pci_regs_behavior)
  259. return -ENOMEM;
  260. if (bridge->has_pcie) {
  261. bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
  262. bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
  263. bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
  264. bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
  265. bridge->pcie_cap_regs_behavior =
  266. kmemdup(pcie_cap_regs_behavior,
  267. sizeof(pcie_cap_regs_behavior),
  268. GFP_KERNEL);
  269. if (!bridge->pcie_cap_regs_behavior) {
  270. kfree(bridge->pci_regs_behavior);
  271. return -ENOMEM;
  272. }
  273. /* These bits are applicable only for PCI and reserved on PCIe */
  274. bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
  275. ~GENMASK(15, 8);
  276. bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
  277. ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
  278. PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
  279. PCI_COMMAND_FAST_BACK) |
  280. (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
  281. PCI_STATUS_DEVSEL_MASK) << 16);
  282. bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
  283. ~GENMASK(31, 24);
  284. bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
  285. ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
  286. PCI_STATUS_DEVSEL_MASK) << 16);
  287. bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
  288. ~((PCI_BRIDGE_CTL_MASTER_ABORT |
  289. BIT(8) | BIT(9) | BIT(11)) << 16);
  290. bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
  291. ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
  292. bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
  293. ~(BIT(10) << 16);
  294. }
  295. if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
  296. bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
  297. bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
  298. }
  299. return 0;
  300. }
  301. EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
  302. /*
  303. * Cleanup a pci_bridge_emul structure that was previously initialized
  304. * using pci_bridge_emul_init().
  305. */
  306. void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
  307. {
  308. if (bridge->has_pcie)
  309. kfree(bridge->pcie_cap_regs_behavior);
  310. kfree(bridge->pci_regs_behavior);
  311. }
  312. EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
  313. /*
  314. * Should be called by the PCI controller driver when reading the PCI
  315. * configuration space of the fake bridge. It will call back the
  316. * ->ops->read_base or ->ops->read_pcie operations.
  317. */
  318. int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
  319. int size, u32 *value)
  320. {
  321. int ret;
  322. int reg = where & ~3;
  323. pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
  324. int reg, u32 *value);
  325. __le32 *cfgspace;
  326. const struct pci_bridge_reg_behavior *behavior;
  327. if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
  328. *value = 0;
  329. return PCIBIOS_SUCCESSFUL;
  330. }
  331. if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
  332. *value = 0;
  333. return PCIBIOS_SUCCESSFUL;
  334. }
  335. if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
  336. reg -= PCI_CAP_PCIE_START;
  337. read_op = bridge->ops->read_pcie;
  338. cfgspace = (__le32 *) &bridge->pcie_conf;
  339. behavior = bridge->pcie_cap_regs_behavior;
  340. } else {
  341. read_op = bridge->ops->read_base;
  342. cfgspace = (__le32 *) &bridge->conf;
  343. behavior = bridge->pci_regs_behavior;
  344. }
  345. if (read_op)
  346. ret = read_op(bridge, reg, value);
  347. else
  348. ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
  349. if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
  350. *value = le32_to_cpu(cfgspace[reg / 4]);
  351. /*
  352. * Make sure we never return any reserved bit with a value
  353. * different from 0.
  354. */
  355. *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
  356. behavior[reg / 4].w1c;
  357. if (size == 1)
  358. *value = (*value >> (8 * (where & 3))) & 0xff;
  359. else if (size == 2)
  360. *value = (*value >> (8 * (where & 3))) & 0xffff;
  361. else if (size != 4)
  362. return PCIBIOS_BAD_REGISTER_NUMBER;
  363. return PCIBIOS_SUCCESSFUL;
  364. }
  365. EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
  366. /*
  367. * Should be called by the PCI controller driver when writing the PCI
  368. * configuration space of the fake bridge. It will call back the
  369. * ->ops->write_base or ->ops->write_pcie operations.
  370. */
  371. int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
  372. int size, u32 value)
  373. {
  374. int reg = where & ~3;
  375. int mask, ret, old, new, shift;
  376. void (*write_op)(struct pci_bridge_emul *bridge, int reg,
  377. u32 old, u32 new, u32 mask);
  378. __le32 *cfgspace;
  379. const struct pci_bridge_reg_behavior *behavior;
  380. if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
  381. return PCIBIOS_SUCCESSFUL;
  382. if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
  383. return PCIBIOS_SUCCESSFUL;
  384. shift = (where & 0x3) * 8;
  385. if (size == 4)
  386. mask = 0xffffffff;
  387. else if (size == 2)
  388. mask = 0xffff << shift;
  389. else if (size == 1)
  390. mask = 0xff << shift;
  391. else
  392. return PCIBIOS_BAD_REGISTER_NUMBER;
  393. ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
  394. if (ret != PCIBIOS_SUCCESSFUL)
  395. return ret;
  396. if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
  397. reg -= PCI_CAP_PCIE_START;
  398. write_op = bridge->ops->write_pcie;
  399. cfgspace = (__le32 *) &bridge->pcie_conf;
  400. behavior = bridge->pcie_cap_regs_behavior;
  401. } else {
  402. write_op = bridge->ops->write_base;
  403. cfgspace = (__le32 *) &bridge->conf;
  404. behavior = bridge->pci_regs_behavior;
  405. }
  406. /* Keep all bits, except the RW bits */
  407. new = old & (~mask | ~behavior[reg / 4].rw);
  408. /* Update the value of the RW bits */
  409. new |= (value << shift) & (behavior[reg / 4].rw & mask);
  410. /* Clear the W1C bits */
  411. new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
  412. /* Save the new value with the cleared W1C bits into the cfgspace */
  413. cfgspace[reg / 4] = cpu_to_le32(new);
  414. /*
  415. * Clear the W1C bits not specified by the write mask, so that the
  416. * write_op() does not clear them.
  417. */
  418. new &= ~(behavior[reg / 4].w1c & ~mask);
  419. /*
  420. * Set the W1C bits specified by the write mask, so that write_op()
  421. * knows about that they are to be cleared.
  422. */
  423. new |= (value << shift) & (behavior[reg / 4].w1c & mask);
  424. if (write_op)
  425. write_op(bridge, reg, old, new, mask);
  426. return PCIBIOS_SUCCESSFUL;
  427. }
  428. EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);