sc27xx-efuse.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Spreadtrum Communications Inc.
  3. #include <linux/hwspinlock.h>
  4. #include <linux/module.h>
  5. #include <linux/of.h>
  6. #include <linux/of_device.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <linux/nvmem-provider.h>
  10. /* PMIC global registers definition */
  11. #define SC27XX_MODULE_EN 0xc08
  12. #define SC2730_MODULE_EN 0x1808
  13. #define SC27XX_EFUSE_EN BIT(6)
  14. /* Efuse controller registers definition */
  15. #define SC27XX_EFUSE_GLB_CTRL 0x0
  16. #define SC27XX_EFUSE_DATA_RD 0x4
  17. #define SC27XX_EFUSE_DATA_WR 0x8
  18. #define SC27XX_EFUSE_BLOCK_INDEX 0xc
  19. #define SC27XX_EFUSE_MODE_CTRL 0x10
  20. #define SC27XX_EFUSE_STATUS 0x14
  21. #define SC27XX_EFUSE_WR_TIMING_CTRL 0x20
  22. #define SC27XX_EFUSE_RD_TIMING_CTRL 0x24
  23. #define SC27XX_EFUSE_EFUSE_DEB_CTRL 0x28
  24. /* Mask definition for SC27XX_EFUSE_BLOCK_INDEX register */
  25. #define SC27XX_EFUSE_BLOCK_MASK GENMASK(4, 0)
  26. /* Bits definitions for SC27XX_EFUSE_MODE_CTRL register */
  27. #define SC27XX_EFUSE_PG_START BIT(0)
  28. #define SC27XX_EFUSE_RD_START BIT(1)
  29. #define SC27XX_EFUSE_CLR_RDDONE BIT(2)
  30. /* Bits definitions for SC27XX_EFUSE_STATUS register */
  31. #define SC27XX_EFUSE_PGM_BUSY BIT(0)
  32. #define SC27XX_EFUSE_READ_BUSY BIT(1)
  33. #define SC27XX_EFUSE_STANDBY BIT(2)
  34. #define SC27XX_EFUSE_GLOBAL_PROT BIT(3)
  35. #define SC27XX_EFUSE_RD_DONE BIT(4)
  36. /* Block number and block width (bytes) definitions */
  37. #define SC27XX_EFUSE_BLOCK_MAX 32
  38. #define SC27XX_EFUSE_BLOCK_WIDTH 2
  39. /* Timeout (ms) for the trylock of hardware spinlocks */
  40. #define SC27XX_EFUSE_HWLOCK_TIMEOUT 5000
  41. /* Timeout (us) of polling the status */
  42. #define SC27XX_EFUSE_POLL_TIMEOUT 3000000
  43. #define SC27XX_EFUSE_POLL_DELAY_US 10000
  44. /*
  45. * Since different PMICs of SC27xx series can have different
  46. * address , we should save address in the device data structure.
  47. */
  48. struct sc27xx_efuse_variant_data {
  49. u32 module_en;
  50. };
  51. struct sc27xx_efuse {
  52. struct device *dev;
  53. struct regmap *regmap;
  54. struct hwspinlock *hwlock;
  55. struct mutex mutex;
  56. u32 base;
  57. const struct sc27xx_efuse_variant_data *var_data;
  58. };
  59. static const struct sc27xx_efuse_variant_data sc2731_edata = {
  60. .module_en = SC27XX_MODULE_EN,
  61. };
  62. static const struct sc27xx_efuse_variant_data sc2730_edata = {
  63. .module_en = SC2730_MODULE_EN,
  64. };
  65. /*
  66. * On Spreadtrum platform, we have multi-subsystems will access the unique
  67. * efuse controller, so we need one hardware spinlock to synchronize between
  68. * the multiple subsystems.
  69. */
  70. static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse)
  71. {
  72. int ret;
  73. mutex_lock(&efuse->mutex);
  74. ret = hwspin_lock_timeout_raw(efuse->hwlock,
  75. SC27XX_EFUSE_HWLOCK_TIMEOUT);
  76. if (ret) {
  77. dev_err(efuse->dev, "timeout to get the hwspinlock\n");
  78. mutex_unlock(&efuse->mutex);
  79. return ret;
  80. }
  81. return 0;
  82. }
  83. static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse)
  84. {
  85. hwspin_unlock_raw(efuse->hwlock);
  86. mutex_unlock(&efuse->mutex);
  87. }
  88. static int sc27xx_efuse_poll_status(struct sc27xx_efuse *efuse, u32 bits)
  89. {
  90. int ret;
  91. u32 val;
  92. ret = regmap_read_poll_timeout(efuse->regmap,
  93. efuse->base + SC27XX_EFUSE_STATUS,
  94. val, (val & bits),
  95. SC27XX_EFUSE_POLL_DELAY_US,
  96. SC27XX_EFUSE_POLL_TIMEOUT);
  97. if (ret) {
  98. dev_err(efuse->dev, "timeout to update the efuse status\n");
  99. return ret;
  100. }
  101. return 0;
  102. }
  103. static int sc27xx_efuse_read(void *context, u32 offset, void *val, size_t bytes)
  104. {
  105. struct sc27xx_efuse *efuse = context;
  106. u32 buf, blk_index = offset / SC27XX_EFUSE_BLOCK_WIDTH;
  107. u32 blk_offset = (offset % SC27XX_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
  108. int ret;
  109. if (blk_index > SC27XX_EFUSE_BLOCK_MAX ||
  110. bytes > SC27XX_EFUSE_BLOCK_WIDTH)
  111. return -EINVAL;
  112. ret = sc27xx_efuse_lock(efuse);
  113. if (ret)
  114. return ret;
  115. /* Enable the efuse controller. */
  116. ret = regmap_update_bits(efuse->regmap, efuse->var_data->module_en,
  117. SC27XX_EFUSE_EN, SC27XX_EFUSE_EN);
  118. if (ret)
  119. goto unlock_efuse;
  120. /*
  121. * Before reading, we should ensure the efuse controller is in
  122. * standby state.
  123. */
  124. ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_STANDBY);
  125. if (ret)
  126. goto disable_efuse;
  127. /* Set the block address to be read. */
  128. ret = regmap_write(efuse->regmap,
  129. efuse->base + SC27XX_EFUSE_BLOCK_INDEX,
  130. blk_index & SC27XX_EFUSE_BLOCK_MASK);
  131. if (ret)
  132. goto disable_efuse;
  133. /* Start reading process from efuse memory. */
  134. ret = regmap_update_bits(efuse->regmap,
  135. efuse->base + SC27XX_EFUSE_MODE_CTRL,
  136. SC27XX_EFUSE_RD_START,
  137. SC27XX_EFUSE_RD_START);
  138. if (ret)
  139. goto disable_efuse;
  140. /*
  141. * Polling the read done status to make sure the reading process
  142. * is completed, that means the data can be read out now.
  143. */
  144. ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_RD_DONE);
  145. if (ret)
  146. goto disable_efuse;
  147. /* Read data from efuse memory. */
  148. ret = regmap_read(efuse->regmap, efuse->base + SC27XX_EFUSE_DATA_RD,
  149. &buf);
  150. if (ret)
  151. goto disable_efuse;
  152. /* Clear the read done flag. */
  153. ret = regmap_update_bits(efuse->regmap,
  154. efuse->base + SC27XX_EFUSE_MODE_CTRL,
  155. SC27XX_EFUSE_CLR_RDDONE,
  156. SC27XX_EFUSE_CLR_RDDONE);
  157. disable_efuse:
  158. /* Disable the efuse controller after reading. */
  159. regmap_update_bits(efuse->regmap, efuse->var_data->module_en, SC27XX_EFUSE_EN, 0);
  160. unlock_efuse:
  161. sc27xx_efuse_unlock(efuse);
  162. if (!ret) {
  163. buf >>= blk_offset;
  164. memcpy(val, &buf, bytes);
  165. }
  166. return ret;
  167. }
  168. static int sc27xx_efuse_probe(struct platform_device *pdev)
  169. {
  170. struct device_node *np = pdev->dev.of_node;
  171. struct nvmem_config econfig = { };
  172. struct nvmem_device *nvmem;
  173. struct sc27xx_efuse *efuse;
  174. int ret;
  175. efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
  176. if (!efuse)
  177. return -ENOMEM;
  178. efuse->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  179. if (!efuse->regmap) {
  180. dev_err(&pdev->dev, "failed to get efuse regmap\n");
  181. return -ENODEV;
  182. }
  183. ret = of_property_read_u32(np, "reg", &efuse->base);
  184. if (ret) {
  185. dev_err(&pdev->dev, "failed to get efuse base address\n");
  186. return ret;
  187. }
  188. ret = of_hwspin_lock_get_id(np, 0);
  189. if (ret < 0) {
  190. dev_err(&pdev->dev, "failed to get hwspinlock id\n");
  191. return ret;
  192. }
  193. efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
  194. if (!efuse->hwlock) {
  195. dev_err(&pdev->dev, "failed to request hwspinlock\n");
  196. return -ENXIO;
  197. }
  198. mutex_init(&efuse->mutex);
  199. efuse->dev = &pdev->dev;
  200. efuse->var_data = of_device_get_match_data(&pdev->dev);
  201. econfig.stride = 1;
  202. econfig.word_size = 1;
  203. econfig.read_only = true;
  204. econfig.name = "sc27xx-efuse";
  205. econfig.size = SC27XX_EFUSE_BLOCK_MAX * SC27XX_EFUSE_BLOCK_WIDTH;
  206. econfig.reg_read = sc27xx_efuse_read;
  207. econfig.priv = efuse;
  208. econfig.dev = &pdev->dev;
  209. nvmem = devm_nvmem_register(&pdev->dev, &econfig);
  210. if (IS_ERR(nvmem)) {
  211. dev_err(&pdev->dev, "failed to register nvmem config\n");
  212. return PTR_ERR(nvmem);
  213. }
  214. return 0;
  215. }
  216. static const struct of_device_id sc27xx_efuse_of_match[] = {
  217. { .compatible = "sprd,sc2731-efuse", .data = &sc2731_edata},
  218. { .compatible = "sprd,sc2730-efuse", .data = &sc2730_edata},
  219. { }
  220. };
  221. static struct platform_driver sc27xx_efuse_driver = {
  222. .probe = sc27xx_efuse_probe,
  223. .driver = {
  224. .name = "sc27xx-efuse",
  225. .of_match_table = sc27xx_efuse_of_match,
  226. },
  227. };
  228. module_platform_driver(sc27xx_efuse_driver);
  229. MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
  230. MODULE_DESCRIPTION("Spreadtrum SC27xx efuse driver");
  231. MODULE_LICENSE("GPL v2");