rockchip-efuse.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Rockchip eFuse Driver
  4. *
  5. * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
  6. * Author: Caesar Wang <wxt@rock-chips.com>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/nvmem-provider.h>
  14. #include <linux/slab.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/platform_device.h>
  18. #define RK3288_A_SHIFT 6
  19. #define RK3288_A_MASK 0x3ff
  20. #define RK3288_PGENB BIT(3)
  21. #define RK3288_LOAD BIT(2)
  22. #define RK3288_STROBE BIT(1)
  23. #define RK3288_CSB BIT(0)
  24. #define RK3328_SECURE_SIZES 96
  25. #define RK3328_INT_STATUS 0x0018
  26. #define RK3328_DOUT 0x0020
  27. #define RK3328_AUTO_CTRL 0x0024
  28. #define RK3328_INT_FINISH BIT(0)
  29. #define RK3328_AUTO_ENB BIT(0)
  30. #define RK3328_AUTO_RD BIT(1)
  31. #define RK3399_A_SHIFT 16
  32. #define RK3399_A_MASK 0x3ff
  33. #define RK3399_NBYTES 4
  34. #define RK3399_STROBSFTSEL BIT(9)
  35. #define RK3399_RSB BIT(7)
  36. #define RK3399_PD BIT(5)
  37. #define RK3399_PGENB BIT(3)
  38. #define RK3399_LOAD BIT(2)
  39. #define RK3399_STROBE BIT(1)
  40. #define RK3399_CSB BIT(0)
  41. #define REG_EFUSE_CTRL 0x0000
  42. #define REG_EFUSE_DOUT 0x0004
  43. struct rockchip_efuse_chip {
  44. struct device *dev;
  45. void __iomem *base;
  46. struct clk *clk;
  47. };
  48. static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
  49. void *val, size_t bytes)
  50. {
  51. struct rockchip_efuse_chip *efuse = context;
  52. u8 *buf = val;
  53. int ret;
  54. ret = clk_prepare_enable(efuse->clk);
  55. if (ret < 0) {
  56. dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
  57. return ret;
  58. }
  59. writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
  60. udelay(1);
  61. while (bytes--) {
  62. writel(readl(efuse->base + REG_EFUSE_CTRL) &
  63. (~(RK3288_A_MASK << RK3288_A_SHIFT)),
  64. efuse->base + REG_EFUSE_CTRL);
  65. writel(readl(efuse->base + REG_EFUSE_CTRL) |
  66. ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
  67. efuse->base + REG_EFUSE_CTRL);
  68. udelay(1);
  69. writel(readl(efuse->base + REG_EFUSE_CTRL) |
  70. RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
  71. udelay(1);
  72. *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
  73. writel(readl(efuse->base + REG_EFUSE_CTRL) &
  74. (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
  75. udelay(1);
  76. }
  77. /* Switch to standby mode */
  78. writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
  79. clk_disable_unprepare(efuse->clk);
  80. return 0;
  81. }
  82. static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
  83. void *val, size_t bytes)
  84. {
  85. struct rockchip_efuse_chip *efuse = context;
  86. unsigned int addr_start, addr_end, addr_offset, addr_len;
  87. u32 out_value, status;
  88. u8 *buf;
  89. int ret, i = 0;
  90. ret = clk_prepare_enable(efuse->clk);
  91. if (ret < 0) {
  92. dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
  93. return ret;
  94. }
  95. /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
  96. offset += RK3328_SECURE_SIZES;
  97. addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
  98. addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
  99. addr_offset = offset % RK3399_NBYTES;
  100. addr_len = addr_end - addr_start;
  101. buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
  102. GFP_KERNEL);
  103. if (!buf) {
  104. ret = -ENOMEM;
  105. goto nomem;
  106. }
  107. while (addr_len--) {
  108. writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
  109. ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
  110. efuse->base + RK3328_AUTO_CTRL);
  111. udelay(4);
  112. status = readl(efuse->base + RK3328_INT_STATUS);
  113. if (!(status & RK3328_INT_FINISH)) {
  114. ret = -EIO;
  115. goto err;
  116. }
  117. out_value = readl(efuse->base + RK3328_DOUT);
  118. writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
  119. memcpy(&buf[i], &out_value, RK3399_NBYTES);
  120. i += RK3399_NBYTES;
  121. }
  122. memcpy(val, buf + addr_offset, bytes);
  123. err:
  124. kfree(buf);
  125. nomem:
  126. clk_disable_unprepare(efuse->clk);
  127. return ret;
  128. }
  129. static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
  130. void *val, size_t bytes)
  131. {
  132. struct rockchip_efuse_chip *efuse = context;
  133. unsigned int addr_start, addr_end, addr_offset, addr_len;
  134. u32 out_value;
  135. u8 *buf;
  136. int ret, i = 0;
  137. ret = clk_prepare_enable(efuse->clk);
  138. if (ret < 0) {
  139. dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
  140. return ret;
  141. }
  142. addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
  143. addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
  144. addr_offset = offset % RK3399_NBYTES;
  145. addr_len = addr_end - addr_start;
  146. buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)),
  147. GFP_KERNEL);
  148. if (!buf) {
  149. clk_disable_unprepare(efuse->clk);
  150. return -ENOMEM;
  151. }
  152. writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
  153. efuse->base + REG_EFUSE_CTRL);
  154. udelay(1);
  155. while (addr_len--) {
  156. writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
  157. ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
  158. efuse->base + REG_EFUSE_CTRL);
  159. udelay(1);
  160. out_value = readl(efuse->base + REG_EFUSE_DOUT);
  161. writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
  162. efuse->base + REG_EFUSE_CTRL);
  163. udelay(1);
  164. memcpy(&buf[i], &out_value, RK3399_NBYTES);
  165. i += RK3399_NBYTES;
  166. }
  167. /* Switch to standby mode */
  168. writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
  169. memcpy(val, buf + addr_offset, bytes);
  170. kfree(buf);
  171. clk_disable_unprepare(efuse->clk);
  172. return 0;
  173. }
  174. static struct nvmem_config econfig = {
  175. .name = "rockchip-efuse",
  176. .stride = 1,
  177. .word_size = 1,
  178. .read_only = true,
  179. };
  180. static const struct of_device_id rockchip_efuse_match[] = {
  181. /* deprecated but kept around for dts binding compatibility */
  182. {
  183. .compatible = "rockchip,rockchip-efuse",
  184. .data = (void *)&rockchip_rk3288_efuse_read,
  185. },
  186. {
  187. .compatible = "rockchip,rk3066a-efuse",
  188. .data = (void *)&rockchip_rk3288_efuse_read,
  189. },
  190. {
  191. .compatible = "rockchip,rk3188-efuse",
  192. .data = (void *)&rockchip_rk3288_efuse_read,
  193. },
  194. {
  195. .compatible = "rockchip,rk3228-efuse",
  196. .data = (void *)&rockchip_rk3288_efuse_read,
  197. },
  198. {
  199. .compatible = "rockchip,rk3288-efuse",
  200. .data = (void *)&rockchip_rk3288_efuse_read,
  201. },
  202. {
  203. .compatible = "rockchip,rk3368-efuse",
  204. .data = (void *)&rockchip_rk3288_efuse_read,
  205. },
  206. {
  207. .compatible = "rockchip,rk3328-efuse",
  208. .data = (void *)&rockchip_rk3328_efuse_read,
  209. },
  210. {
  211. .compatible = "rockchip,rk3399-efuse",
  212. .data = (void *)&rockchip_rk3399_efuse_read,
  213. },
  214. { /* sentinel */},
  215. };
  216. MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
  217. static int rockchip_efuse_probe(struct platform_device *pdev)
  218. {
  219. struct resource *res;
  220. struct nvmem_device *nvmem;
  221. struct rockchip_efuse_chip *efuse;
  222. const void *data;
  223. struct device *dev = &pdev->dev;
  224. data = of_device_get_match_data(dev);
  225. if (!data) {
  226. dev_err(dev, "failed to get match data\n");
  227. return -EINVAL;
  228. }
  229. efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip),
  230. GFP_KERNEL);
  231. if (!efuse)
  232. return -ENOMEM;
  233. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  234. efuse->base = devm_ioremap_resource(dev, res);
  235. if (IS_ERR(efuse->base))
  236. return PTR_ERR(efuse->base);
  237. efuse->clk = devm_clk_get(dev, "pclk_efuse");
  238. if (IS_ERR(efuse->clk))
  239. return PTR_ERR(efuse->clk);
  240. efuse->dev = dev;
  241. if (of_property_read_u32(dev->of_node, "rockchip,efuse-size",
  242. &econfig.size))
  243. econfig.size = resource_size(res);
  244. econfig.reg_read = data;
  245. econfig.priv = efuse;
  246. econfig.dev = efuse->dev;
  247. nvmem = devm_nvmem_register(dev, &econfig);
  248. return PTR_ERR_OR_ZERO(nvmem);
  249. }
  250. static struct platform_driver rockchip_efuse_driver = {
  251. .probe = rockchip_efuse_probe,
  252. .driver = {
  253. .name = "rockchip-efuse",
  254. .of_match_table = rockchip_efuse_match,
  255. },
  256. };
  257. module_platform_driver(rockchip_efuse_driver);
  258. MODULE_DESCRIPTION("rockchip_efuse driver");
  259. MODULE_LICENSE("GPL v2");