light-efuse.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2021 Alibaba Inc.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/compiler_types.h>
  7. #include <linux/device.h>
  8. #include <linux/pm_runtime.h>
  9. #include <asm/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/mod_devicetable.h>
  13. #include <linux/nvmem-provider.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/slab.h>
  17. #include <linux/types.h>
  18. #include <linux/mfd/syscon.h>
  19. #define CON 0x00
  20. #define LCPAR 0x04
  21. #define ADDR 0x40
  22. #define WDATA 0x44
  23. #define WDATA_MASK 0x48
  24. #define WP0 0x50
  25. #define WP1 0x54
  26. #define WP2 0x58
  27. #define WP3 0x5c
  28. #define STA 0x70
  29. #define RDATA0 0x80
  30. #define SHADOW_RDATA0 0xc0
  31. #define SHADOW_RDATA1 0xc4
  32. #define SHADOW_RDATA2 0xc8
  33. #define SHADOW_RDATA3 0xcc
  34. #define SHADOW_RDATA4 0xd0
  35. #define SHADOW_RDATA5 0xd4
  36. #define SHADOW_RDATA6 0xd8
  37. #define SHADOW_RDATA7 0xdc
  38. #define TEE_SYS_EFUSE_DBG_KEY1_OFF 0x70
  39. #define ENABLE_DFT_FUNC_MASK GENMASK(3, 0)
  40. #define ENABLE_DFT_FUNC 0x5
  41. #define DISABLE_DFT_FUNC 0xa
  42. /* bit definition for CON */
  43. #define EFUSE_CON_POWER_MSK BIT(14)
  44. /* bit definition for STA */
  45. #define EFUSE_STA_IDLE_MSK BIT(0)
  46. #define EFUSE_STA_RD_STATUS_POS 4
  47. #define EFUSE_STA_RD_STATUS_MSK (0x7UL << EFUSE_STA_RD_STATUS_POS)
  48. #define EFUSE_STA_WR_STATUS_POS 8
  49. #define EFUSE_STA_WR_STATUS_MSK (0x7UL << EFUSE_STA_WR_STATUS_POS)
  50. #define EFUSE_STA_CMD_ILLEGAL_POS 11
  51. #define EFUSE_STA_CMD_ILLEGAL_MSK (0x1UL << EFUSE_STA_CMD_ILLEGAL_POS)
  52. #define EFUSE_STA_KTRANS_ALARM_POS 14
  53. #define EFUSE_STA_KTRANS_ALARM_MSK (0x1UL << EFUSE_STA_KTRANS_ALARM_POS)
  54. /* Max try time for idle check */
  55. #define MAX_TRY_TIME_IDLE 10000
  56. #define DEVICE_BUSY 1
  57. #define EFUSE_CON_CMD_POS 8
  58. #define EFUSE_CON_CMD_MSK GENMASK(12, 8)
  59. #define EFUSE_CON_CMD_IDLE (0x0 << EFUSE_CON_CMD_POS)
  60. #define EFUSE_CON_CMD_READ (0x1 << EFUSE_CON_CMD_POS)
  61. #define EFUSE_CON_CMD_WRITE (0x2 << EFUSE_CON_CMD_POS)
  62. #define EFUSE_CON_CMD_BLKREAD (0x3 << EFUSE_CON_CMD_POS)
  63. #define EFUSE_CON_CMD_WP_LOCK (0x8 << EFUSE_CON_CMD_POS)
  64. #define EFUSE_CON_CMD_CP_LOCK (0x9 << EFUSE_CON_CMD_POS)
  65. #define EFUSE_CON_CMD_RP_LOCK (0xA << EFUSE_CON_CMD_POS)
  66. #define EFUSE_CON_CMD_UP_LC (0x10 << EFUSE_CON_CMD_POS)
  67. #define EFUSE_CON_START BIT(0)
  68. #define EFUSE_CON_CLEAR BIT(1)
  69. #define EFUSE_CON_KEY_TRANS_MSK BIT(13)
  70. #define EFUSE_CON_LC_READ_MSK BIT(2)
  71. #define EFUSE_CON_START_MSK BIT(0)
  72. #define EFUSE_CON_MSK (EFUSE_CON_LC_READ_MSK | \
  73. EFUSE_CON_CMD_MSK | \
  74. EFUSE_CON_KEY_TRANS_MSK | \
  75. EFUSE_CON_START_MSK)
  76. #define IS_CVKEY1(addr) ((addr >= 0x38) && (addr < 0x3C))
  77. #define IS_CVKEY2(addr) ((addr >= 0x3C) && (addr < 0x78))
  78. #define IS_USRKEY2(addr) ((addr >= 0x78) && (addr < 0xd8))
  79. /* Block width (bytes) definitions */
  80. #define LIGHT_EFUSE_LIT_BLOCK_WIDTH 16
  81. #define LIGHT_EFUSE_BIG_BLOCK_WIDTH 32
  82. #define LIGHT_EFUSE_LIT_BLOCK_NUM 52
  83. #define LIGHT_EFUSE_BIG_BLOCK_NUM 6
  84. #define RMA_LIFE_CYCLE_PARA 0x1A946F9B
  85. #define RIP_LIFE_CYCLE_PARA 0xEE45E8A7
  86. struct light_efuse_priv {
  87. struct device *dev;
  88. void __iomem *base;
  89. struct regmap *teesys_regs;
  90. struct clk *clk;
  91. u32 sysfs_rd_offset;
  92. u32 sysfs_rd_len;
  93. };
  94. static u32 perm_spi_magic[] = {
  95. 0x9804E1BC,
  96. 0x4B8B59F5,
  97. 0x36D33417,
  98. 0x7491B7D5,
  99. };
  100. static u32 update_lc_magic[] = {
  101. 0x768A7E2F,
  102. 0xE4D53282,
  103. 0x8BD97337,
  104. 0x677B9E85,
  105. };
  106. static u32 read_magic[] = {
  107. 0x32224E05,
  108. 0xC3F981D0,
  109. 0xF4D7FB08,
  110. 0xA4C8C6DE,
  111. };
  112. static u32 write_magic[] = {
  113. 0xB4BC4A0A,
  114. 0x2A8B7E6F,
  115. 0x974B25A1,
  116. 0x67DB5F5F,
  117. };
  118. static u32 block_read_magic[] = {
  119. 0x39CF83C1,
  120. 0xD0DDD6B2,
  121. 0xBD50693B,
  122. 0x5F61B752,
  123. };
  124. static u32 wp_lock_magic[] = {
  125. 0x0D11ECA6,
  126. 0x06EDF631,
  127. 0xB58CA544,
  128. 0x1EBDE503,
  129. };
  130. static u32 cp_lock_magic[] = {
  131. 0xC21E9BB8,
  132. 0x0FC428F1,
  133. 0xD8E95026,
  134. 0x1C34AC41,
  135. };
  136. static u32 rp_lock_magic[] = {
  137. 0xAEB3089A,
  138. 0x8DE56E9A,
  139. 0x453416C2,
  140. 0x969F6937,
  141. };
  142. static u32 key_tran_magic[] = {
  143. 0x1AF5952C,
  144. 0x111B5E55,
  145. 0xFAE8A83D,
  146. 0xEDFE9E7F,
  147. };
  148. static u32 *cmd_perm_magic_num[] = {
  149. perm_spi_magic,
  150. update_lc_magic,
  151. read_magic,
  152. write_magic,
  153. block_read_magic,
  154. wp_lock_magic,
  155. cp_lock_magic,
  156. rp_lock_magic,
  157. key_tran_magic
  158. };
  159. enum permission_type {
  160. CMD_SPI = 0,
  161. CMD_UPDATE_LC,
  162. CMD_READ,
  163. CMD_WRITE,
  164. CMD_BLOCK_READ,
  165. CMD_WP_LOCK,
  166. CMD_CP_LOCK,
  167. CMD_RP_LOCK,
  168. CMD_KEY_TRAN,
  169. CMD_KEY_MAX,
  170. };
  171. enum con_cmd_type {
  172. CON_CMD_IDLE = 0,
  173. CON_CMD_READ,
  174. CON_CMD_WRITE,
  175. CON_CMD_BLOCK_RD,
  176. CON_CMD_WP_LOCK,
  177. CON_CMD_CP_LOCK,
  178. CON_CMD_RP_LOCK,
  179. CON_CMD_UP_LC,
  180. CON_CMD_MAX,
  181. };
  182. static inline bool efuse_poweron_status_get(void __iomem *base)
  183. {
  184. return readl(base + CON) & EFUSE_CON_POWER_MSK ? false : true;
  185. }
  186. static inline int efuse_idle_check(void __iomem *base)
  187. {
  188. int try_cnt = MAX_TRY_TIME_IDLE;
  189. while (try_cnt--) {
  190. if (!(readl(base + STA) & EFUSE_STA_IDLE_MSK))
  191. return 0;
  192. }
  193. if (try_cnt <= 0)
  194. return -DEVICE_BUSY;
  195. return 0;
  196. }
  197. static inline int efuse_status_check(void __iomem *base)
  198. {
  199. u32 data = readl(base + STA);
  200. int errcode;
  201. errcode = data & (EFUSE_STA_RD_STATUS_MSK | EFUSE_STA_WR_STATUS_MSK |
  202. EFUSE_STA_CMD_ILLEGAL_MSK | EFUSE_STA_KTRANS_ALARM_MSK);
  203. pr_debug("[%s,%d]efuse status before clear: 0x%x\n", __func__, __LINE__, errcode);
  204. /* If error happens, write clear should be added */
  205. if (errcode) {
  206. pr_err("error efuse operation STA status: 0x%x\n", errcode);
  207. writel(data, base + STA);
  208. }
  209. return -errcode;
  210. }
  211. static inline int efuse_poweron(void __iomem *base)
  212. {
  213. u32 data;
  214. int ret;
  215. if (efuse_poweron_status_get(base))
  216. return 0;
  217. data = readl(base + CON);
  218. data &= ~EFUSE_CON_POWER_MSK;
  219. writel(data, base + CON);
  220. ret = efuse_idle_check(base);
  221. ret |= efuse_status_check(base);
  222. pr_debug("pd status: 0x%lx\n", readl(base + CON) & EFUSE_CON_POWER_MSK);
  223. return ret;
  224. }
  225. static inline u32 efuse_data_read(void __iomem *base)
  226. {
  227. return readl(base + RDATA0);
  228. }
  229. static inline void efuse_data_clear(void __iomem *base)
  230. {
  231. u32 data = readl(base + CON);
  232. data |= EFUSE_CON_CLEAR;
  233. writel(data, base + CON);
  234. }
  235. static
  236. inline void efuse_permission_magic_config(void __iomem *base, u32 *magic_num[],
  237. enum permission_type cmd)
  238. {
  239. writel(magic_num[cmd][3], base + WP0);
  240. writel(magic_num[cmd][2], base + WP1);
  241. writel(magic_num[cmd][1], base + WP2);
  242. writel(magic_num[cmd][0], base + WP3);
  243. }
  244. static inline void efuse_addr_config(void __iomem *base, u32 addr)
  245. {
  246. writel(addr, base + ADDR);
  247. pr_debug("[%s, %d]efuse addr reg: 0x%x\n", __func__, __LINE__, readl(base + ADDR));
  248. }
  249. static inline void efuse_data_mask_config(void __iomem *base, u32 mask)
  250. {
  251. writel(mask, base + WDATA_MASK);
  252. }
  253. static inline void efuse_data_config(void __iomem *base, u32 data)
  254. {
  255. writel(data, base + WDATA);
  256. pr_debug("[%s, %d]efuse data reg: 0x%x\n", __func__, __LINE__, readl(base + WDATA));
  257. }
  258. static inline void efuse_life_cycle_para_config(void __iomem *base, u32 data)
  259. {
  260. writel(data, base + LCPAR);
  261. }
  262. static inline u32 efuse_life_cycle_para_get(void __iomem *base)
  263. {
  264. return readl(base + LCPAR);
  265. }
  266. static inline int efuse_cmd_start(void __iomem *base, enum con_cmd_type cmd_type)
  267. {
  268. u32 data, cmd;
  269. switch (cmd_type) {
  270. case CON_CMD_IDLE:
  271. cmd = EFUSE_CON_CMD_IDLE;
  272. break;
  273. case CON_CMD_READ:
  274. cmd = EFUSE_CON_CMD_READ;
  275. break;
  276. case CON_CMD_WRITE:
  277. cmd = EFUSE_CON_CMD_WRITE;
  278. break;
  279. case CON_CMD_BLOCK_RD:
  280. cmd = EFUSE_CON_CMD_BLKREAD;
  281. break;
  282. case CON_CMD_WP_LOCK:
  283. cmd = EFUSE_CON_CMD_WP_LOCK;
  284. break;
  285. case CON_CMD_CP_LOCK:
  286. cmd = EFUSE_CON_CMD_CP_LOCK;
  287. break;
  288. case CON_CMD_RP_LOCK:
  289. cmd = EFUSE_CON_CMD_RP_LOCK;
  290. break;
  291. case CON_CMD_UP_LC:
  292. cmd = EFUSE_CON_CMD_UP_LC;
  293. break;
  294. default:
  295. return -EINVAL;
  296. }
  297. /* Mask LC_Read, Key_transfer, command and start bits */
  298. data = readl(base + CON);
  299. data &= ~EFUSE_CON_MSK;
  300. data |= cmd | EFUSE_CON_START;
  301. writel(data, base + CON);
  302. return 0;
  303. }
  304. static DEFINE_MUTEX(light_efuse_mutex);
  305. static int light_efuse_read_start(void __iomem *base, u32 addr, enum con_cmd_type cmd_type)
  306. {
  307. int ret = 0;
  308. enum permission_type permission;
  309. if (cmd_type == CON_CMD_READ)
  310. permission = CMD_READ;
  311. else if (cmd_type == CON_CMD_BLOCK_RD)
  312. permission = CMD_BLOCK_READ;
  313. else {
  314. pr_err("invaid efuse read command type\n");
  315. return -EINVAL;
  316. }
  317. ret = efuse_idle_check(base);
  318. if (ret) {
  319. pr_err("the device is busy\n");
  320. return ret;
  321. }
  322. efuse_permission_magic_config(base, cmd_perm_magic_num, permission);
  323. efuse_addr_config(base, addr);
  324. ret = efuse_cmd_start(base, cmd_type);
  325. if (ret)
  326. return ret;
  327. /* Wait controller completed */
  328. ret = efuse_idle_check(base);
  329. /* Check status, if there has error, reort and clear status */
  330. ret |= efuse_status_check(base);
  331. if (ret) {
  332. pr_err("error occurs while start reading at efuse byte addr: %d\n", addr * 4);
  333. return ret;
  334. }
  335. if (cmd_type == CON_CMD_BLOCK_RD) {
  336. pr_debug("=======================================\n");
  337. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA0));
  338. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA1));
  339. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA2));
  340. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA3));
  341. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA4));
  342. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA5));
  343. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA6));
  344. pr_debug("shadow: 0x%x\n", readl(base + SHADOW_RDATA7));
  345. }
  346. return ret;
  347. }
  348. static int light_efuse_read_word(void __iomem *base, u32 addr, u32 *val)
  349. {
  350. int ret = 0;
  351. ret = efuse_idle_check(base);
  352. if (ret)
  353. return ret;
  354. ret = light_efuse_read_start(base, addr, CON_CMD_READ);
  355. if (ret) {
  356. pr_err("failed to start efuse read\n");
  357. goto exit;
  358. }
  359. *val = efuse_data_read(base);
  360. pr_debug("[%s][%d]data = 0x%x\n", __func__, __LINE__,*val);
  361. exit:
  362. efuse_data_clear(base);
  363. return ret;
  364. }
  365. static int light_efuse_write_word(void __iomem *base, u32 addr, u32 data, u32 mask)
  366. {
  367. int ret = 0;
  368. ret = efuse_idle_check(base);
  369. if (ret)
  370. return ret;
  371. /*
  372. * Check permission:
  373. * Check it every time to avoid wp0~3 are changed somewhere
  374. */
  375. efuse_permission_magic_config(base, cmd_perm_magic_num, CMD_WRITE);
  376. /* Config address */
  377. efuse_addr_config(base, addr);
  378. /* Config data */
  379. efuse_data_config(base, data);
  380. /* Config data mask , if we're in keyrange mask should be set to 0 */
  381. if (IS_CVKEY1(addr) || IS_CVKEY2(addr) || IS_USRKEY2(addr))
  382. efuse_data_mask_config(base, 0);
  383. else
  384. efuse_data_mask_config(base, mask);
  385. /* Set write command */
  386. ret = efuse_cmd_start(base, CON_CMD_WRITE);
  387. if (ret)
  388. goto exit;
  389. /* Wait controller completed */
  390. ret = efuse_idle_check(base);
  391. exit:
  392. /* Check status, if there has error, reort and clear status */
  393. ret |= efuse_status_check(base);
  394. if (ret)
  395. pr_err("error occurs while start writing at efuse byte addr: %d\n", addr * 4);
  396. efuse_data_clear(base);
  397. return ret;
  398. }
  399. static int light_efuse_read(void *context, unsigned int addr, void *data, size_t bytes)
  400. {
  401. struct light_efuse_priv *priv = context;
  402. u32 byte_offset, read_count, read_addr;
  403. u8 *pdst, *psrc;
  404. u32 value;
  405. int ret = 0;
  406. mutex_lock(&light_efuse_mutex);
  407. dev_dbg(priv->dev, "[%s]efuse addr: 0x%x, bytes: %d\n", __func__, addr, (int)bytes);
  408. ret = pm_runtime_get_sync(priv->dev);
  409. if (ret < 0) {
  410. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  411. pm_runtime_put_noidle(priv->dev);
  412. goto read_end;
  413. }
  414. if (efuse_poweron(priv->base)) {
  415. dev_err(priv->dev, "failed to power on efuse\n");
  416. ret = -EBUSY;
  417. goto read_end;
  418. }
  419. pdst = data;
  420. byte_offset = addr & 0x3;
  421. read_addr = addr / 4; /* Efuse unit is 4 bytes */
  422. /* byte_offset != 0, means not 4 bytes aligned, read first word first */
  423. if (byte_offset) {
  424. ret = light_efuse_read_word(priv->base, read_addr, &value);
  425. if (ret) {
  426. dev_err(priv->dev, "failed to read efuse data\n");
  427. goto read_end;
  428. }
  429. read_count = 4 - byte_offset;
  430. psrc = (u8 *)&value + byte_offset;
  431. if (bytes < read_count)
  432. read_count = bytes;
  433. memcpy(pdst, psrc, read_count);
  434. read_addr++;
  435. pdst += read_count;
  436. bytes -= read_count;
  437. }
  438. while (bytes >= 4) {
  439. ret = light_efuse_read_word(priv->base, read_addr, &value);
  440. if (ret) {
  441. dev_err(priv->dev, "failed to read efuse data\n");
  442. goto read_end;
  443. }
  444. memcpy(pdst, &value, 4);
  445. bytes -= 4;
  446. read_addr++; /* the hardware will span over one word length automatically */
  447. pdst += 4;
  448. }
  449. if (bytes > 0) {
  450. ret = light_efuse_read_word(priv->base, read_addr, &value);
  451. if (ret) {
  452. dev_err(priv->dev, "failed to read data from efuse\n");
  453. goto read_end;
  454. }
  455. memcpy(pdst, &value, bytes);
  456. }
  457. pm_runtime_put_sync(priv->dev);
  458. read_end:
  459. mutex_unlock(&light_efuse_mutex);
  460. return ret;
  461. }
  462. static int light_efuse_write(void *context, unsigned int addr, void *data, size_t bytes)
  463. {
  464. struct light_efuse_priv *priv = context;
  465. int ret = 0;
  466. u32 byte_offset, write_addr, value = 0;
  467. u32 write_count, mask;
  468. u8 *psrc, *pdst;
  469. size_t __maybe_unused orign_bytes = bytes;
  470. mutex_lock(&light_efuse_mutex);
  471. dev_dbg(priv->dev, "[%s]efuse addr: 0x%x, bytes: %d\n", __func__, addr, (int)bytes);
  472. ret = pm_runtime_get_sync(priv->dev);
  473. if (ret < 0) {
  474. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  475. pm_runtime_put_noidle(priv->dev);
  476. goto write_end;
  477. }
  478. if (efuse_poweron(priv->base)) {
  479. dev_err(priv->dev, "failed to power on efuse\n");
  480. ret = -EBUSY;
  481. goto write_end;
  482. }
  483. byte_offset = addr & 0x3;
  484. psrc = (u8 *)data;
  485. write_addr = addr / 4;
  486. pr_debug("[%s][%d]: write addr = 0x%x\n", __func__, __LINE__, write_addr);
  487. pr_debug("Write data: ");
  488. if (byte_offset) {
  489. write_count = 4 - byte_offset;
  490. if (bytes < write_count)
  491. write_count = bytes;
  492. pdst = (u8 *)&value + byte_offset;
  493. memcpy(pdst, psrc, write_count);
  494. pr_debug("0x%x ", *psrc);
  495. mask = ~value;
  496. ret = light_efuse_write_word(priv->base, write_addr, value, mask);
  497. if (ret) {
  498. dev_err(priv->dev, "failed to write data to efuse\n");
  499. goto write_end;
  500. }
  501. psrc += write_count;
  502. write_addr++;
  503. bytes -= write_count;
  504. }
  505. while (bytes >= 4) {
  506. value = 0;
  507. pdst = (u8 *)&value;
  508. write_count = 4;
  509. memcpy(pdst, psrc, write_count);
  510. pr_debug("0x%x ", *psrc);
  511. mask = ~value;
  512. ret = light_efuse_write_word(priv->base, write_addr, value, mask);
  513. if (ret) {
  514. dev_err(priv->dev, "failed to write data to efuse\n");
  515. goto write_end;
  516. }
  517. psrc += write_count;
  518. bytes -= write_count;
  519. write_addr++;
  520. }
  521. if (bytes > 0) {
  522. value = 0;
  523. pdst = (u8 *)&value;
  524. memcpy(pdst, psrc, bytes);
  525. pr_debug("0x%x ", *psrc);
  526. mask = ~value;
  527. ret = light_efuse_write_word(priv->base, write_addr, value, mask);
  528. if (ret) {
  529. dev_err(priv->dev, "failed to write data to efuse\n");
  530. goto write_end;
  531. }
  532. }
  533. pr_debug("\n");
  534. pm_runtime_put_sync(priv->dev);
  535. write_end:
  536. mutex_unlock(&light_efuse_mutex);
  537. return ret < 0 ? ret : orign_bytes;
  538. }
  539. static ssize_t efuse_nvmem_store(struct device *dev,
  540. struct device_attribute *attr,
  541. const char *buf, size_t count)
  542. {
  543. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  544. char *start = (char *)buf;
  545. char type;
  546. unsigned long addr, len;
  547. unsigned char *data;
  548. int i, ret;
  549. /*
  550. * echo types:
  551. * echo w offset len 0x01 0x02 0x03 ... > efuse_nvmem
  552. * echo r offset len > efuse_nvmem
  553. */
  554. while (*start == ' ') /* skip space */
  555. start++;
  556. if (*start != 'w' && *start != 'r')
  557. return -EINVAL;
  558. type = *start;
  559. start++;
  560. while (*start == ' ')
  561. start++;
  562. addr = simple_strtoul(start, &start, 0);
  563. while (*start == ' ')
  564. start++;
  565. len = simple_strtoul(start, &start, 0);
  566. priv->sysfs_rd_offset = addr;
  567. priv->sysfs_rd_len = len;
  568. if (type == 'r')
  569. goto exit;
  570. data = kzalloc(sizeof(*data) * len, GFP_KERNEL);
  571. if (!data)
  572. return -ENOMEM;
  573. pr_debug("echo data:\n");
  574. for (i = 0; i < len; i++) {
  575. while (*start == ' ')
  576. start++;
  577. data[i] = simple_strtoul(start, &start, 0);
  578. pr_debug("0x%x ", data[i]);
  579. }
  580. ret = light_efuse_write(priv, addr, data, len);
  581. if (ret < 0) {
  582. kfree(data);
  583. return ret;
  584. }
  585. kfree(data);
  586. exit:
  587. return count;
  588. }
  589. static ssize_t efuse_nvmem_show(struct device *dev,
  590. struct device_attribute *attr, char *buf)
  591. {
  592. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  593. u32 addr = priv->sysfs_rd_offset;
  594. u32 len = priv->sysfs_rd_len;
  595. int ret, i;
  596. unsigned char *data;
  597. size_t bufpos = 0, count;
  598. data = kzalloc(sizeof(*data) * len, GFP_KERNEL);
  599. if (!data)
  600. return -ENOMEM;
  601. ret = light_efuse_read(priv, addr, data, len);
  602. if (ret < 0)
  603. goto out;
  604. count = (len + 2) * 10;
  605. for (i = 0; i < len; i++) {
  606. snprintf(buf + bufpos, count - bufpos, "0x%.*x", 2, data[i]);
  607. bufpos += 4;
  608. if (i == len - 1 || (i !=0 && i % 16 == 0))
  609. buf[bufpos++] = '\n';
  610. else
  611. buf[bufpos++] = ' ';
  612. }
  613. out:
  614. kfree(data);
  615. return bufpos;
  616. }
  617. static ssize_t rma_lc_store(struct device *dev,
  618. struct device_attribute *attr,
  619. const char *buf, size_t count)
  620. {
  621. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  622. u32 value = RMA_LIFE_CYCLE_PARA;
  623. int ret;
  624. ret = pm_runtime_get_sync(priv->dev);
  625. if (ret < 0) {
  626. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  627. pm_runtime_put_noidle(priv->dev);
  628. return ret;
  629. }
  630. regmap_update_bits(priv->teesys_regs,
  631. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  632. ENABLE_DFT_FUNC_MASK,
  633. ENABLE_DFT_FUNC);
  634. efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
  635. efuse_life_cycle_para_config(priv->base, value);
  636. /* Set command */
  637. ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
  638. if (ret)
  639. goto exit;
  640. /* Wait controller completed */
  641. ret = efuse_idle_check(priv->base);
  642. pr_debug("set life cycle value: 0x%x\n", value);
  643. exit:
  644. regmap_update_bits(priv->teesys_regs,
  645. TEE_SYS_EFUSE_DBG_KEY1_OFF,
  646. ENABLE_DFT_FUNC_MASK,
  647. DISABLE_DFT_FUNC);
  648. /* Check status, if there has error, reort and clear status */
  649. ret |= efuse_status_check(priv->base);
  650. if (ret)
  651. pr_err("error occurs while starting write\n");
  652. efuse_data_clear(priv->base);
  653. pm_runtime_put_sync(priv->dev);
  654. return ret < 0 ? ret : count;
  655. }
  656. static ssize_t rip_lc_store(struct device *dev,
  657. struct device_attribute *attr,
  658. const char *buf, size_t count)
  659. {
  660. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  661. u32 value = RIP_LIFE_CYCLE_PARA;
  662. int ret;
  663. ret = pm_runtime_get_sync(priv->dev);
  664. if (ret < 0) {
  665. dev_err(priv->dev, "failed to get the efuse device(%d)\n", ret);
  666. pm_runtime_put_noidle(priv->dev);
  667. return ret;
  668. }
  669. efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
  670. efuse_life_cycle_para_config(priv->base, value);
  671. /* Set command */
  672. ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
  673. if (ret)
  674. goto exit;
  675. /* Wait controller completed */
  676. ret = efuse_idle_check(priv->base);
  677. exit:
  678. /* Check status, if there has error, reort and clear status */
  679. ret |= efuse_status_check(priv->base);
  680. if (ret)
  681. pr_err("error occurs while starting write\n");
  682. efuse_data_clear(priv->base);
  683. pm_runtime_put_sync(priv->dev);
  684. return ret < 0 ? ret : count;
  685. }
  686. static DEVICE_ATTR_WO(rma_lc);
  687. static DEVICE_ATTR_WO(rip_lc);
  688. static DEVICE_ATTR_RW(efuse_nvmem);
  689. static struct attribute *light_efuse_sysfs_entries[] = {
  690. &dev_attr_efuse_nvmem.attr,
  691. &dev_attr_rip_lc.attr,
  692. &dev_attr_rma_lc.attr,
  693. NULL
  694. };
  695. static const struct attribute_group dev_attr_efuse_sysfs_group = {
  696. .attrs = light_efuse_sysfs_entries,
  697. };
  698. static const struct of_device_id light_efuse_of_match[] = {
  699. {.compatible = "thead,light-fm-efuse"},
  700. { /* sentinel */},
  701. };
  702. MODULE_DEVICE_TABLE(of, light_efuse_of_match);
  703. static int __maybe_unused light_efuse_runtime_suspend(struct device *dev)
  704. {
  705. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  706. u32 data;
  707. int ret;
  708. dev_dbg(dev, "[%s,%d]efuse runtime power down\n", __func__, __LINE__);
  709. if (!efuse_poweron_status_get(priv->base))
  710. return 0;
  711. data = readl(priv->base + CON);
  712. data |= EFUSE_CON_POWER_MSK;
  713. writel(data, priv->base + CON);
  714. ret = efuse_idle_check(priv->base);
  715. ret |= efuse_status_check(priv->base);
  716. dev_dbg(dev, "[%s,%d] ret = %d, pd status: 0x%lx\n", __func__, __LINE__, ret,
  717. readl(priv->base + CON) & EFUSE_CON_POWER_MSK);
  718. return ret;
  719. }
  720. static int __maybe_unused light_efuse_runtime_resume(struct device *dev)
  721. {
  722. struct light_efuse_priv *priv = dev_get_drvdata(dev);
  723. dev_dbg(dev, "[%s,%d]efuse runtime power on\n", __func__, __LINE__);
  724. return efuse_poweron(priv->base);
  725. }
  726. static int light_efuse_probe(struct platform_device *pdev)
  727. {
  728. struct device *dev = &pdev->dev;
  729. struct nvmem_device *nvmem;
  730. struct nvmem_config config = {};
  731. struct light_efuse_priv *priv;
  732. int ret;
  733. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  734. if (!priv)
  735. return -ENOMEM;
  736. priv->base = devm_platform_ioremap_resource(pdev, 0);
  737. if (IS_ERR(priv->base))
  738. return PTR_ERR(priv->base);
  739. /* optional clock, default open */
  740. priv->clk = devm_clk_get(dev, NULL);
  741. if (IS_ERR(priv->clk))
  742. priv->clk = NULL;
  743. priv->teesys_regs = syscon_regmap_lookup_by_phandle(dev->of_node, "thead,teesys");
  744. if (IS_ERR(priv->teesys_regs)) {
  745. dev_err(dev, "unable to find teesys registers\n");
  746. return PTR_ERR(priv->teesys_regs);
  747. }
  748. priv->dev = dev;
  749. dev_set_drvdata(dev, priv);
  750. ret = sysfs_create_group(&dev->kobj, &dev_attr_efuse_sysfs_group);
  751. if (ret) {
  752. dev_err(dev, "failed to create efuse debug sysfs\n");
  753. return ret;
  754. }
  755. config.name = "light-efuse";
  756. config.read_only = false;
  757. config.stride = 1;
  758. config.word_size = 1; /* the least read and write unit on the upper level */
  759. config.reg_read = light_efuse_read;
  760. config.reg_write = light_efuse_write;
  761. config.size = LIGHT_EFUSE_LIT_BLOCK_NUM * LIGHT_EFUSE_LIT_BLOCK_WIDTH +
  762. LIGHT_EFUSE_BIG_BLOCK_NUM * LIGHT_EFUSE_BIG_BLOCK_WIDTH;
  763. config.priv = priv;
  764. config.dev = dev;
  765. nvmem = devm_nvmem_register(dev, &config);
  766. if (IS_ERR(nvmem))
  767. return PTR_ERR_OR_ZERO(nvmem);
  768. pm_runtime_enable(dev);
  769. dev_info(dev, "succeed to register light efuse driver\n");
  770. return 0;
  771. }
  772. static const struct dev_pm_ops efuse_runtime_pm_ops = {
  773. SET_RUNTIME_PM_OPS(light_efuse_runtime_suspend, light_efuse_runtime_resume, NULL)
  774. };
  775. static struct platform_driver light_efuse_driver = {
  776. .probe = light_efuse_probe,
  777. .driver = {
  778. .name = "light_efuse",
  779. .of_match_table = light_efuse_of_match,
  780. .pm = &efuse_runtime_pm_ops,
  781. },
  782. };
  783. module_platform_driver(light_efuse_driver);
  784. MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
  785. MODULE_DESCRIPTION("Thead light nvmem driver");
  786. MODULE_LICENSE("GPL v2");