via-sdmmc.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
  4. * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
  5. */
  6. #include <linux/pci.h>
  7. #include <linux/module.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/highmem.h>
  10. #include <linux/delay.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/mmc/host.h>
  13. #define DRV_NAME "via_sdmmc"
  14. #define PCI_DEVICE_ID_VIA_9530 0x9530
  15. #define VIA_CRDR_SDC_OFF 0x200
  16. #define VIA_CRDR_DDMA_OFF 0x400
  17. #define VIA_CRDR_PCICTRL_OFF 0x600
  18. #define VIA_CRDR_MIN_CLOCK 375000
  19. #define VIA_CRDR_MAX_CLOCK 48000000
  20. /*
  21. * PCI registers
  22. */
  23. #define VIA_CRDR_PCI_WORK_MODE 0x40
  24. #define VIA_CRDR_PCI_DBG_MODE 0x41
  25. /*
  26. * SDC MMIO Registers
  27. */
  28. #define VIA_CRDR_SDCTRL 0x0
  29. #define VIA_CRDR_SDCTRL_START 0x01
  30. #define VIA_CRDR_SDCTRL_WRITE 0x04
  31. #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
  32. #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
  33. #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
  34. #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
  35. #define VIA_CRDR_SDCTRL_STOP 0x70
  36. #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
  37. #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
  38. #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
  39. #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
  40. #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
  41. #define VIA_CRDR_SDCARG 0x4
  42. #define VIA_CRDR_SDBUSMODE 0x8
  43. #define VIA_CRDR_SDMODE_4BIT 0x02
  44. #define VIA_CRDR_SDMODE_CLK_ON 0x40
  45. #define VIA_CRDR_SDBLKLEN 0xc
  46. /*
  47. * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
  48. * Bit 11 - Bit 13 : Reserved.
  49. * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
  50. * INTEN : Enable SD host interrupt.
  51. * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
  52. */
  53. #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
  54. #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
  55. #define VIA_CRDR_MAX_BLOCK_COUNT 65536
  56. #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
  57. #define VIA_CRDR_SDRESP0 0x10
  58. #define VIA_CRDR_SDRESP1 0x14
  59. #define VIA_CRDR_SDRESP2 0x18
  60. #define VIA_CRDR_SDRESP3 0x1c
  61. #define VIA_CRDR_SDCURBLKCNT 0x20
  62. #define VIA_CRDR_SDINTMASK 0x24
  63. /*
  64. * MBDIE : Multiple Blocks transfer Done Interrupt Enable
  65. * BDDIE : Block Data transfer Done Interrupt Enable
  66. * CIRIE : Card Insertion or Removal Interrupt Enable
  67. * CRDIE : Command-Response transfer Done Interrupt Enable
  68. * CRTOIE : Command-Response response TimeOut Interrupt Enable
  69. * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
  70. * DTIE : Data access Timeout Interrupt Enable
  71. * SCIE : reSponse CRC error Interrupt Enable
  72. * RCIE : Read data CRC error Interrupt Enable
  73. * WCIE : Write data CRC error Interrupt Enable
  74. */
  75. #define VIA_CRDR_SDINTMASK_MBDIE 0x10
  76. #define VIA_CRDR_SDINTMASK_BDDIE 0x20
  77. #define VIA_CRDR_SDINTMASK_CIRIE 0x80
  78. #define VIA_CRDR_SDINTMASK_CRDIE 0x200
  79. #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
  80. #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
  81. #define VIA_CRDR_SDINTMASK_DTIE 0x1000
  82. #define VIA_CRDR_SDINTMASK_SCIE 0x2000
  83. #define VIA_CRDR_SDINTMASK_RCIE 0x4000
  84. #define VIA_CRDR_SDINTMASK_WCIE 0x8000
  85. #define VIA_CRDR_SDACTIVE_INTMASK \
  86. (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
  87. | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
  88. | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
  89. | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
  90. #define VIA_CRDR_SDSTATUS 0x28
  91. /*
  92. * CECC : Reserved
  93. * WP : SD card Write Protect status
  94. * SLOTD : Reserved
  95. * SLOTG : SD SLOT status(Gpi pin status)
  96. * MBD : Multiple Blocks transfer Done interrupt status
  97. * BDD : Block Data transfer Done interrupt status
  98. * CD : Reserved
  99. * CIR : Card Insertion or Removal interrupt detected on GPI pin
  100. * IO : Reserved
  101. * CRD : Command-Response transfer Done interrupt status
  102. * CRTO : Command-Response response TimeOut interrupt status
  103. * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
  104. * DT : Data access Timeout interrupt status
  105. * SC : reSponse CRC error interrupt status
  106. * RC : Read data CRC error interrupt status
  107. * WC : Write data CRC error interrupt status
  108. */
  109. #define VIA_CRDR_SDSTS_CECC 0x01
  110. #define VIA_CRDR_SDSTS_WP 0x02
  111. #define VIA_CRDR_SDSTS_SLOTD 0x04
  112. #define VIA_CRDR_SDSTS_SLOTG 0x08
  113. #define VIA_CRDR_SDSTS_MBD 0x10
  114. #define VIA_CRDR_SDSTS_BDD 0x20
  115. #define VIA_CRDR_SDSTS_CD 0x40
  116. #define VIA_CRDR_SDSTS_CIR 0x80
  117. #define VIA_CRDR_SDSTS_IO 0x100
  118. #define VIA_CRDR_SDSTS_CRD 0x200
  119. #define VIA_CRDR_SDSTS_CRTO 0x400
  120. #define VIA_CRDR_SDSTS_ASCRDIE 0x800
  121. #define VIA_CRDR_SDSTS_DT 0x1000
  122. #define VIA_CRDR_SDSTS_SC 0x2000
  123. #define VIA_CRDR_SDSTS_RC 0x4000
  124. #define VIA_CRDR_SDSTS_WC 0x8000
  125. #define VIA_CRDR_SDSTS_IGN_MASK\
  126. (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
  127. #define VIA_CRDR_SDSTS_INT_MASK \
  128. (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
  129. | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
  130. | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
  131. | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
  132. #define VIA_CRDR_SDSTS_W1C_MASK \
  133. (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
  134. | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
  135. | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
  136. | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
  137. #define VIA_CRDR_SDSTS_CMD_MASK \
  138. (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
  139. #define VIA_CRDR_SDSTS_DATA_MASK\
  140. (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
  141. | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
  142. #define VIA_CRDR_SDSTATUS2 0x2a
  143. /*
  144. * CFE : Enable SD host automatic Clock FReezing
  145. */
  146. #define VIA_CRDR_SDSTS_CFE 0x80
  147. #define VIA_CRDR_SDRSPTMO 0x2C
  148. #define VIA_CRDR_SDCLKSEL 0x30
  149. #define VIA_CRDR_SDEXTCTRL 0x34
  150. #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
  151. #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
  152. #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
  153. #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
  154. #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
  155. #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
  156. #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
  157. #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
  158. /* 0x38-0xFF reserved */
  159. /*
  160. * Data DMA Control Registers
  161. */
  162. #define VIA_CRDR_DMABASEADD 0x0
  163. #define VIA_CRDR_DMACOUNTER 0x4
  164. #define VIA_CRDR_DMACTRL 0x8
  165. /*
  166. * DIR :Transaction Direction
  167. * 0 : From card to memory
  168. * 1 : From memory to card
  169. */
  170. #define VIA_CRDR_DMACTRL_DIR 0x100
  171. #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
  172. #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
  173. #define VIA_CRDR_DMASTS 0xc
  174. #define VIA_CRDR_DMASTART 0x10
  175. /*0x14-0xFF reserved*/
  176. /*
  177. * PCI Control Registers
  178. */
  179. /*0x0 - 0x1 reserved*/
  180. #define VIA_CRDR_PCICLKGATT 0x2
  181. /*
  182. * SFTRST :
  183. * 0 : Soft reset all the controller and it will be de-asserted automatically
  184. * 1 : Soft reset is de-asserted
  185. */
  186. #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
  187. /*
  188. * 3V3 : Pad power select
  189. * 0 : 1.8V
  190. * 1 : 3.3V
  191. * NOTE : No mater what the actual value should be, this bit always
  192. * read as 0. This is a hardware bug.
  193. */
  194. #define VIA_CRDR_PCICLKGATT_3V3 0x10
  195. /*
  196. * PAD_PWRON : Pad Power on/off select
  197. * 0 : Power off
  198. * 1 : Power on
  199. * NOTE : No mater what the actual value should be, this bit always
  200. * read as 0. This is a hardware bug.
  201. */
  202. #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
  203. #define VIA_CRDR_PCISDCCLK 0x5
  204. #define VIA_CRDR_PCIDMACLK 0x7
  205. #define VIA_CRDR_PCIDMACLK_SDC 0x2
  206. #define VIA_CRDR_PCIINTCTRL 0x8
  207. #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
  208. #define VIA_CRDR_PCIINTSTATUS 0x9
  209. #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
  210. #define VIA_CRDR_PCITMOCTRL 0xa
  211. #define VIA_CRDR_PCITMOCTRL_NO 0x0
  212. #define VIA_CRDR_PCITMOCTRL_32US 0x1
  213. #define VIA_CRDR_PCITMOCTRL_256US 0x2
  214. #define VIA_CRDR_PCITMOCTRL_1024US 0x3
  215. #define VIA_CRDR_PCITMOCTRL_256MS 0x4
  216. #define VIA_CRDR_PCITMOCTRL_512MS 0x5
  217. #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
  218. /*0xB-0xFF reserved*/
  219. enum PCI_HOST_CLK_CONTROL {
  220. PCI_CLK_375K = 0x03,
  221. PCI_CLK_8M = 0x04,
  222. PCI_CLK_12M = 0x00,
  223. PCI_CLK_16M = 0x05,
  224. PCI_CLK_24M = 0x01,
  225. PCI_CLK_33M = 0x06,
  226. PCI_CLK_48M = 0x02
  227. };
  228. struct sdhcreg {
  229. u32 sdcontrol_reg;
  230. u32 sdcmdarg_reg;
  231. u32 sdbusmode_reg;
  232. u32 sdblklen_reg;
  233. u32 sdresp_reg[4];
  234. u32 sdcurblkcnt_reg;
  235. u32 sdintmask_reg;
  236. u32 sdstatus_reg;
  237. u32 sdrsptmo_reg;
  238. u32 sdclksel_reg;
  239. u32 sdextctrl_reg;
  240. };
  241. struct pcictrlreg {
  242. u8 reserve[2];
  243. u8 pciclkgat_reg;
  244. u8 pcinfcclk_reg;
  245. u8 pcimscclk_reg;
  246. u8 pcisdclk_reg;
  247. u8 pcicaclk_reg;
  248. u8 pcidmaclk_reg;
  249. u8 pciintctrl_reg;
  250. u8 pciintstatus_reg;
  251. u8 pcitmoctrl_reg;
  252. u8 Resv;
  253. };
  254. struct via_crdr_mmc_host {
  255. struct mmc_host *mmc;
  256. struct mmc_request *mrq;
  257. struct mmc_command *cmd;
  258. struct mmc_data *data;
  259. void __iomem *mmiobase;
  260. void __iomem *sdhc_mmiobase;
  261. void __iomem *ddma_mmiobase;
  262. void __iomem *pcictrl_mmiobase;
  263. struct pcictrlreg pm_pcictrl_reg;
  264. struct sdhcreg pm_sdhc_reg;
  265. struct work_struct carddet_work;
  266. struct tasklet_struct finish_tasklet;
  267. struct timer_list timer;
  268. spinlock_t lock;
  269. u8 power;
  270. int reject;
  271. unsigned int quirks;
  272. };
  273. /* some devices need a very long delay for power to stabilize */
  274. #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
  275. #define VIA_CMD_TIMEOUT_MS 1000
  276. static const struct pci_device_id via_ids[] = {
  277. {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
  278. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  279. {0,}
  280. };
  281. MODULE_DEVICE_TABLE(pci, via_ids);
  282. static void via_print_sdchc(struct via_crdr_mmc_host *host)
  283. {
  284. void __iomem *addrbase = host->sdhc_mmiobase;
  285. pr_debug("SDC MMIO Registers:\n");
  286. pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
  287. readl(addrbase + VIA_CRDR_SDCTRL),
  288. readl(addrbase + VIA_CRDR_SDCARG),
  289. readl(addrbase + VIA_CRDR_SDBUSMODE));
  290. pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
  291. readl(addrbase + VIA_CRDR_SDBLKLEN),
  292. readl(addrbase + VIA_CRDR_SDCURBLKCNT),
  293. readl(addrbase + VIA_CRDR_SDINTMASK));
  294. pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
  295. readl(addrbase + VIA_CRDR_SDSTATUS),
  296. readl(addrbase + VIA_CRDR_SDCLKSEL),
  297. readl(addrbase + VIA_CRDR_SDEXTCTRL));
  298. }
  299. static void via_print_pcictrl(struct via_crdr_mmc_host *host)
  300. {
  301. void __iomem *addrbase = host->pcictrl_mmiobase;
  302. pr_debug("PCI Control Registers:\n");
  303. pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
  304. readb(addrbase + VIA_CRDR_PCICLKGATT),
  305. readb(addrbase + VIA_CRDR_PCISDCCLK),
  306. readb(addrbase + VIA_CRDR_PCIDMACLK));
  307. pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
  308. readb(addrbase + VIA_CRDR_PCIINTCTRL),
  309. readb(addrbase + VIA_CRDR_PCIINTSTATUS));
  310. }
  311. static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
  312. {
  313. struct pcictrlreg *pm_pcictrl_reg;
  314. void __iomem *addrbase;
  315. pm_pcictrl_reg = &(host->pm_pcictrl_reg);
  316. addrbase = host->pcictrl_mmiobase;
  317. pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
  318. pm_pcictrl_reg->pciclkgat_reg |=
  319. VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
  320. pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
  321. pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
  322. pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
  323. pm_pcictrl_reg->pciintstatus_reg =
  324. readb(addrbase + VIA_CRDR_PCIINTSTATUS);
  325. pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
  326. }
  327. static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
  328. {
  329. struct pcictrlreg *pm_pcictrl_reg;
  330. void __iomem *addrbase;
  331. pm_pcictrl_reg = &(host->pm_pcictrl_reg);
  332. addrbase = host->pcictrl_mmiobase;
  333. writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
  334. writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
  335. writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
  336. writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
  337. writeb(pm_pcictrl_reg->pciintstatus_reg,
  338. addrbase + VIA_CRDR_PCIINTSTATUS);
  339. writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
  340. }
  341. static void via_save_sdcreg(struct via_crdr_mmc_host *host)
  342. {
  343. struct sdhcreg *pm_sdhc_reg;
  344. void __iomem *addrbase;
  345. pm_sdhc_reg = &(host->pm_sdhc_reg);
  346. addrbase = host->sdhc_mmiobase;
  347. pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
  348. pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
  349. pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
  350. pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
  351. pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
  352. pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
  353. pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
  354. pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
  355. pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
  356. pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
  357. }
  358. static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
  359. {
  360. struct sdhcreg *pm_sdhc_reg;
  361. void __iomem *addrbase;
  362. pm_sdhc_reg = &(host->pm_sdhc_reg);
  363. addrbase = host->sdhc_mmiobase;
  364. writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
  365. writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
  366. writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
  367. writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
  368. writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
  369. writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
  370. writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
  371. writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
  372. writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
  373. writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
  374. }
  375. static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
  376. {
  377. if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
  378. msleep(300);
  379. else
  380. msleep(3);
  381. }
  382. static void via_set_ddma(struct via_crdr_mmc_host *host,
  383. dma_addr_t dmaaddr, u32 count, int dir, int enirq)
  384. {
  385. void __iomem *addrbase;
  386. u32 ctrl_data = 0;
  387. if (enirq)
  388. ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
  389. if (dir)
  390. ctrl_data |= VIA_CRDR_DMACTRL_DIR;
  391. addrbase = host->ddma_mmiobase;
  392. writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
  393. writel(count, addrbase + VIA_CRDR_DMACOUNTER);
  394. writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
  395. writel(0x01, addrbase + VIA_CRDR_DMASTART);
  396. /* It seems that our DMA can not work normally with 375kHz clock */
  397. /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
  398. addrbase = host->pcictrl_mmiobase;
  399. if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
  400. dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
  401. writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
  402. }
  403. }
  404. static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
  405. struct mmc_data *data)
  406. {
  407. void __iomem *addrbase;
  408. u32 blk_reg;
  409. int count;
  410. WARN_ON(host->data);
  411. /* Sanity checks */
  412. BUG_ON(data->blksz > host->mmc->max_blk_size);
  413. BUG_ON(data->blocks > host->mmc->max_blk_count);
  414. host->data = data;
  415. count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  416. ((data->flags & MMC_DATA_READ) ?
  417. PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
  418. BUG_ON(count != 1);
  419. via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
  420. (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
  421. addrbase = host->sdhc_mmiobase;
  422. blk_reg = data->blksz - 1;
  423. blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
  424. blk_reg |= (data->blocks) << 16;
  425. writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
  426. }
  427. static void via_sdc_get_response(struct via_crdr_mmc_host *host,
  428. struct mmc_command *cmd)
  429. {
  430. void __iomem *addrbase = host->sdhc_mmiobase;
  431. u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
  432. u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
  433. u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
  434. u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
  435. if (cmd->flags & MMC_RSP_136) {
  436. cmd->resp[0] = ((u8) (dwdata1)) |
  437. (((u8) (dwdata0 >> 24)) << 8) |
  438. (((u8) (dwdata0 >> 16)) << 16) |
  439. (((u8) (dwdata0 >> 8)) << 24);
  440. cmd->resp[1] = ((u8) (dwdata2)) |
  441. (((u8) (dwdata1 >> 24)) << 8) |
  442. (((u8) (dwdata1 >> 16)) << 16) |
  443. (((u8) (dwdata1 >> 8)) << 24);
  444. cmd->resp[2] = ((u8) (dwdata3)) |
  445. (((u8) (dwdata2 >> 24)) << 8) |
  446. (((u8) (dwdata2 >> 16)) << 16) |
  447. (((u8) (dwdata2 >> 8)) << 24);
  448. cmd->resp[3] = 0xff |
  449. ((((u8) (dwdata3 >> 24))) << 8) |
  450. (((u8) (dwdata3 >> 16)) << 16) |
  451. (((u8) (dwdata3 >> 8)) << 24);
  452. } else {
  453. dwdata0 >>= 8;
  454. cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
  455. (((dwdata0 >> 8) & 0xff) << 16) |
  456. (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
  457. dwdata1 >>= 8;
  458. cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
  459. (((dwdata1 >> 8) & 0xff) << 16) |
  460. (((dwdata1 >> 16) & 0xff) << 8);
  461. }
  462. }
  463. static void via_sdc_send_command(struct via_crdr_mmc_host *host,
  464. struct mmc_command *cmd)
  465. {
  466. void __iomem *addrbase;
  467. struct mmc_data *data;
  468. unsigned int timeout_ms;
  469. u32 cmdctrl = 0;
  470. WARN_ON(host->cmd);
  471. data = cmd->data;
  472. host->cmd = cmd;
  473. timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS;
  474. mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
  475. /*Command index*/
  476. cmdctrl = cmd->opcode << 8;
  477. /*Response type*/
  478. switch (mmc_resp_type(cmd)) {
  479. case MMC_RSP_NONE:
  480. cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
  481. break;
  482. case MMC_RSP_R1:
  483. cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
  484. break;
  485. case MMC_RSP_R1B:
  486. cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
  487. break;
  488. case MMC_RSP_R2:
  489. cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
  490. break;
  491. case MMC_RSP_R3:
  492. cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
  493. break;
  494. default:
  495. pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
  496. break;
  497. }
  498. if (!(cmd->data))
  499. goto nodata;
  500. via_sdc_preparedata(host, data);
  501. /*Command control*/
  502. if (data->blocks > 1) {
  503. if (data->flags & MMC_DATA_WRITE) {
  504. cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
  505. cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
  506. } else {
  507. cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
  508. }
  509. } else {
  510. if (data->flags & MMC_DATA_WRITE) {
  511. cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
  512. cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
  513. } else {
  514. cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
  515. }
  516. }
  517. nodata:
  518. if (cmd == host->mrq->stop)
  519. cmdctrl |= VIA_CRDR_SDCTRL_STOP;
  520. cmdctrl |= VIA_CRDR_SDCTRL_START;
  521. addrbase = host->sdhc_mmiobase;
  522. writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
  523. writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
  524. }
  525. static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
  526. {
  527. struct mmc_data *data;
  528. BUG_ON(!host->data);
  529. data = host->data;
  530. host->data = NULL;
  531. if (data->error)
  532. data->bytes_xfered = 0;
  533. else
  534. data->bytes_xfered = data->blocks * data->blksz;
  535. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  536. ((data->flags & MMC_DATA_READ) ?
  537. PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
  538. if (data->stop)
  539. via_sdc_send_command(host, data->stop);
  540. else
  541. tasklet_schedule(&host->finish_tasklet);
  542. }
  543. static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
  544. {
  545. via_sdc_get_response(host, host->cmd);
  546. host->cmd->error = 0;
  547. if (!host->cmd->data)
  548. tasklet_schedule(&host->finish_tasklet);
  549. host->cmd = NULL;
  550. }
  551. static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  552. {
  553. void __iomem *addrbase;
  554. struct via_crdr_mmc_host *host;
  555. unsigned long flags;
  556. u16 status;
  557. host = mmc_priv(mmc);
  558. spin_lock_irqsave(&host->lock, flags);
  559. addrbase = host->pcictrl_mmiobase;
  560. writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
  561. status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
  562. status &= VIA_CRDR_SDSTS_W1C_MASK;
  563. writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
  564. WARN_ON(host->mrq != NULL);
  565. host->mrq = mrq;
  566. status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
  567. if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
  568. host->mrq->cmd->error = -ENOMEDIUM;
  569. tasklet_schedule(&host->finish_tasklet);
  570. } else {
  571. via_sdc_send_command(host, mrq->cmd);
  572. }
  573. spin_unlock_irqrestore(&host->lock, flags);
  574. }
  575. static void via_sdc_set_power(struct via_crdr_mmc_host *host,
  576. unsigned short power, unsigned int on)
  577. {
  578. unsigned long flags;
  579. u8 gatt;
  580. spin_lock_irqsave(&host->lock, flags);
  581. host->power = (1 << power);
  582. gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  583. if (host->power == MMC_VDD_165_195)
  584. gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
  585. else
  586. gatt |= VIA_CRDR_PCICLKGATT_3V3;
  587. if (on)
  588. gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
  589. else
  590. gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
  591. writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  592. spin_unlock_irqrestore(&host->lock, flags);
  593. via_pwron_sleep(host);
  594. }
  595. static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  596. {
  597. struct via_crdr_mmc_host *host;
  598. unsigned long flags;
  599. void __iomem *addrbase;
  600. u32 org_data, sdextctrl;
  601. u8 clock;
  602. host = mmc_priv(mmc);
  603. spin_lock_irqsave(&host->lock, flags);
  604. addrbase = host->sdhc_mmiobase;
  605. org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
  606. sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
  607. if (ios->bus_width == MMC_BUS_WIDTH_1)
  608. org_data &= ~VIA_CRDR_SDMODE_4BIT;
  609. else
  610. org_data |= VIA_CRDR_SDMODE_4BIT;
  611. if (ios->power_mode == MMC_POWER_OFF)
  612. org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
  613. else
  614. org_data |= VIA_CRDR_SDMODE_CLK_ON;
  615. if (ios->timing == MMC_TIMING_SD_HS)
  616. sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
  617. else
  618. sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
  619. writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
  620. writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
  621. if (ios->clock >= 48000000)
  622. clock = PCI_CLK_48M;
  623. else if (ios->clock >= 33000000)
  624. clock = PCI_CLK_33M;
  625. else if (ios->clock >= 24000000)
  626. clock = PCI_CLK_24M;
  627. else if (ios->clock >= 16000000)
  628. clock = PCI_CLK_16M;
  629. else if (ios->clock >= 12000000)
  630. clock = PCI_CLK_12M;
  631. else if (ios->clock >= 8000000)
  632. clock = PCI_CLK_8M;
  633. else
  634. clock = PCI_CLK_375K;
  635. addrbase = host->pcictrl_mmiobase;
  636. if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
  637. writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
  638. spin_unlock_irqrestore(&host->lock, flags);
  639. if (ios->power_mode != MMC_POWER_OFF)
  640. via_sdc_set_power(host, ios->vdd, 1);
  641. else
  642. via_sdc_set_power(host, ios->vdd, 0);
  643. }
  644. static int via_sdc_get_ro(struct mmc_host *mmc)
  645. {
  646. struct via_crdr_mmc_host *host;
  647. unsigned long flags;
  648. u16 status;
  649. host = mmc_priv(mmc);
  650. spin_lock_irqsave(&host->lock, flags);
  651. status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
  652. spin_unlock_irqrestore(&host->lock, flags);
  653. return !(status & VIA_CRDR_SDSTS_WP);
  654. }
  655. static const struct mmc_host_ops via_sdc_ops = {
  656. .request = via_sdc_request,
  657. .set_ios = via_sdc_set_ios,
  658. .get_ro = via_sdc_get_ro,
  659. };
  660. static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
  661. {
  662. unsigned long flags;
  663. u8 gatt;
  664. spin_lock_irqsave(&host->lock, flags);
  665. via_save_pcictrlreg(host);
  666. via_save_sdcreg(host);
  667. spin_unlock_irqrestore(&host->lock, flags);
  668. gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
  669. if (host->power == MMC_VDD_165_195)
  670. gatt &= VIA_CRDR_PCICLKGATT_3V3;
  671. else
  672. gatt |= VIA_CRDR_PCICLKGATT_3V3;
  673. writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  674. via_pwron_sleep(host);
  675. gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
  676. writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  677. msleep(3);
  678. spin_lock_irqsave(&host->lock, flags);
  679. via_restore_pcictrlreg(host);
  680. via_restore_sdcreg(host);
  681. spin_unlock_irqrestore(&host->lock, flags);
  682. }
  683. static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
  684. {
  685. BUG_ON(intmask == 0);
  686. if (!host->cmd) {
  687. pr_err("%s: Got command interrupt 0x%x even "
  688. "though no command operation was in progress.\n",
  689. mmc_hostname(host->mmc), intmask);
  690. return;
  691. }
  692. if (intmask & VIA_CRDR_SDSTS_CRTO)
  693. host->cmd->error = -ETIMEDOUT;
  694. else if (intmask & VIA_CRDR_SDSTS_SC)
  695. host->cmd->error = -EILSEQ;
  696. if (host->cmd->error)
  697. tasklet_schedule(&host->finish_tasklet);
  698. else if (intmask & VIA_CRDR_SDSTS_CRD)
  699. via_sdc_finish_command(host);
  700. }
  701. static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
  702. {
  703. BUG_ON(intmask == 0);
  704. if (!host->data)
  705. return;
  706. if (intmask & VIA_CRDR_SDSTS_DT)
  707. host->data->error = -ETIMEDOUT;
  708. else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
  709. host->data->error = -EILSEQ;
  710. via_sdc_finish_data(host);
  711. }
  712. static irqreturn_t via_sdc_isr(int irq, void *dev_id)
  713. {
  714. struct via_crdr_mmc_host *sdhost = dev_id;
  715. void __iomem *addrbase;
  716. u8 pci_status;
  717. u16 sd_status;
  718. irqreturn_t result;
  719. if (!sdhost)
  720. return IRQ_NONE;
  721. spin_lock(&sdhost->lock);
  722. addrbase = sdhost->pcictrl_mmiobase;
  723. pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
  724. if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
  725. result = IRQ_NONE;
  726. goto out;
  727. }
  728. addrbase = sdhost->sdhc_mmiobase;
  729. sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
  730. sd_status &= VIA_CRDR_SDSTS_INT_MASK;
  731. sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
  732. if (!sd_status) {
  733. result = IRQ_NONE;
  734. goto out;
  735. }
  736. if (sd_status & VIA_CRDR_SDSTS_CIR) {
  737. writew(sd_status & VIA_CRDR_SDSTS_CIR,
  738. addrbase + VIA_CRDR_SDSTATUS);
  739. schedule_work(&sdhost->carddet_work);
  740. }
  741. sd_status &= ~VIA_CRDR_SDSTS_CIR;
  742. if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
  743. writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
  744. addrbase + VIA_CRDR_SDSTATUS);
  745. via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
  746. }
  747. if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
  748. writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
  749. addrbase + VIA_CRDR_SDSTATUS);
  750. via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
  751. }
  752. sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
  753. if (sd_status) {
  754. pr_err("%s: Unexpected interrupt 0x%x\n",
  755. mmc_hostname(sdhost->mmc), sd_status);
  756. writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
  757. }
  758. result = IRQ_HANDLED;
  759. out:
  760. spin_unlock(&sdhost->lock);
  761. return result;
  762. }
  763. static void via_sdc_timeout(struct timer_list *t)
  764. {
  765. struct via_crdr_mmc_host *sdhost;
  766. unsigned long flags;
  767. sdhost = from_timer(sdhost, t, timer);
  768. spin_lock_irqsave(&sdhost->lock, flags);
  769. if (sdhost->mrq) {
  770. pr_err("%s: Timeout waiting for hardware interrupt."
  771. "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
  772. sdhost->mrq->cmd->opcode);
  773. if (sdhost->data) {
  774. writel(VIA_CRDR_DMACTRL_SFTRST,
  775. sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
  776. sdhost->data->error = -ETIMEDOUT;
  777. via_sdc_finish_data(sdhost);
  778. } else {
  779. if (sdhost->cmd)
  780. sdhost->cmd->error = -ETIMEDOUT;
  781. else
  782. sdhost->mrq->cmd->error = -ETIMEDOUT;
  783. tasklet_schedule(&sdhost->finish_tasklet);
  784. }
  785. }
  786. spin_unlock_irqrestore(&sdhost->lock, flags);
  787. }
  788. static void via_sdc_tasklet_finish(unsigned long param)
  789. {
  790. struct via_crdr_mmc_host *host;
  791. unsigned long flags;
  792. struct mmc_request *mrq;
  793. host = (struct via_crdr_mmc_host *)param;
  794. spin_lock_irqsave(&host->lock, flags);
  795. del_timer(&host->timer);
  796. mrq = host->mrq;
  797. host->mrq = NULL;
  798. host->cmd = NULL;
  799. host->data = NULL;
  800. spin_unlock_irqrestore(&host->lock, flags);
  801. mmc_request_done(host->mmc, mrq);
  802. }
  803. static void via_sdc_card_detect(struct work_struct *work)
  804. {
  805. struct via_crdr_mmc_host *host;
  806. void __iomem *addrbase;
  807. unsigned long flags;
  808. u16 status;
  809. host = container_of(work, struct via_crdr_mmc_host, carddet_work);
  810. addrbase = host->ddma_mmiobase;
  811. writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
  812. spin_lock_irqsave(&host->lock, flags);
  813. addrbase = host->pcictrl_mmiobase;
  814. writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
  815. addrbase = host->sdhc_mmiobase;
  816. status = readw(addrbase + VIA_CRDR_SDSTATUS);
  817. if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
  818. if (host->mrq) {
  819. pr_err("%s: Card removed during transfer!\n",
  820. mmc_hostname(host->mmc));
  821. host->mrq->cmd->error = -ENOMEDIUM;
  822. tasklet_schedule(&host->finish_tasklet);
  823. }
  824. spin_unlock_irqrestore(&host->lock, flags);
  825. via_reset_pcictrl(host);
  826. spin_lock_irqsave(&host->lock, flags);
  827. }
  828. spin_unlock_irqrestore(&host->lock, flags);
  829. via_print_pcictrl(host);
  830. via_print_sdchc(host);
  831. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  832. }
  833. static void via_init_mmc_host(struct via_crdr_mmc_host *host)
  834. {
  835. struct mmc_host *mmc = host->mmc;
  836. void __iomem *addrbase;
  837. u32 lenreg;
  838. u32 status;
  839. timer_setup(&host->timer, via_sdc_timeout, 0);
  840. spin_lock_init(&host->lock);
  841. mmc->f_min = VIA_CRDR_MIN_CLOCK;
  842. mmc->f_max = VIA_CRDR_MAX_CLOCK;
  843. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  844. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
  845. mmc->ops = &via_sdc_ops;
  846. /*Hardware cannot do scatter lists*/
  847. mmc->max_segs = 1;
  848. mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
  849. mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
  850. mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
  851. mmc->max_req_size = mmc->max_seg_size;
  852. INIT_WORK(&host->carddet_work, via_sdc_card_detect);
  853. tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
  854. (unsigned long)host);
  855. addrbase = host->sdhc_mmiobase;
  856. writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
  857. msleep(1);
  858. lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
  859. writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
  860. status = readw(addrbase + VIA_CRDR_SDSTATUS);
  861. status &= VIA_CRDR_SDSTS_W1C_MASK;
  862. writew(status, addrbase + VIA_CRDR_SDSTATUS);
  863. status = readw(addrbase + VIA_CRDR_SDSTATUS2);
  864. status |= VIA_CRDR_SDSTS_CFE;
  865. writew(status, addrbase + VIA_CRDR_SDSTATUS2);
  866. writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
  867. writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
  868. msleep(1);
  869. }
  870. static int via_sd_probe(struct pci_dev *pcidev,
  871. const struct pci_device_id *id)
  872. {
  873. struct mmc_host *mmc;
  874. struct via_crdr_mmc_host *sdhost;
  875. u32 base, len;
  876. u8 gatt;
  877. int ret;
  878. pr_info(DRV_NAME
  879. ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
  880. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
  881. (int)pcidev->revision);
  882. ret = pci_enable_device(pcidev);
  883. if (ret)
  884. return ret;
  885. ret = pci_request_regions(pcidev, DRV_NAME);
  886. if (ret)
  887. goto disable;
  888. pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
  889. pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
  890. mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
  891. if (!mmc) {
  892. ret = -ENOMEM;
  893. goto release;
  894. }
  895. sdhost = mmc_priv(mmc);
  896. sdhost->mmc = mmc;
  897. dev_set_drvdata(&pcidev->dev, sdhost);
  898. len = pci_resource_len(pcidev, 0);
  899. base = pci_resource_start(pcidev, 0);
  900. sdhost->mmiobase = ioremap(base, len);
  901. if (!sdhost->mmiobase) {
  902. ret = -ENOMEM;
  903. goto free_mmc_host;
  904. }
  905. sdhost->sdhc_mmiobase =
  906. sdhost->mmiobase + VIA_CRDR_SDC_OFF;
  907. sdhost->ddma_mmiobase =
  908. sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
  909. sdhost->pcictrl_mmiobase =
  910. sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
  911. sdhost->power = MMC_VDD_165_195;
  912. gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
  913. writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  914. via_pwron_sleep(sdhost);
  915. gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
  916. writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  917. msleep(3);
  918. via_init_mmc_host(sdhost);
  919. ret =
  920. request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
  921. sdhost);
  922. if (ret)
  923. goto unmap;
  924. writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
  925. sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
  926. writeb(VIA_CRDR_PCITMOCTRL_1024MS,
  927. sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
  928. /* device-specific quirks */
  929. if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
  930. pcidev->subsystem_device == 0x3891)
  931. sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
  932. mmc_add_host(mmc);
  933. return 0;
  934. unmap:
  935. iounmap(sdhost->mmiobase);
  936. free_mmc_host:
  937. dev_set_drvdata(&pcidev->dev, NULL);
  938. mmc_free_host(mmc);
  939. release:
  940. pci_release_regions(pcidev);
  941. disable:
  942. pci_disable_device(pcidev);
  943. return ret;
  944. }
  945. static void via_sd_remove(struct pci_dev *pcidev)
  946. {
  947. struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
  948. unsigned long flags;
  949. u8 gatt;
  950. spin_lock_irqsave(&sdhost->lock, flags);
  951. /* Ensure we don't accept more commands from mmc layer */
  952. sdhost->reject = 1;
  953. /* Disable generating further interrupts */
  954. writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
  955. if (sdhost->mrq) {
  956. pr_err("%s: Controller removed during "
  957. "transfer\n", mmc_hostname(sdhost->mmc));
  958. /* make sure all DMA is stopped */
  959. writel(VIA_CRDR_DMACTRL_SFTRST,
  960. sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
  961. sdhost->mrq->cmd->error = -ENOMEDIUM;
  962. if (sdhost->mrq->stop)
  963. sdhost->mrq->stop->error = -ENOMEDIUM;
  964. tasklet_schedule(&sdhost->finish_tasklet);
  965. }
  966. spin_unlock_irqrestore(&sdhost->lock, flags);
  967. mmc_remove_host(sdhost->mmc);
  968. free_irq(pcidev->irq, sdhost);
  969. del_timer_sync(&sdhost->timer);
  970. tasklet_kill(&sdhost->finish_tasklet);
  971. /* switch off power */
  972. gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  973. gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
  974. writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  975. iounmap(sdhost->mmiobase);
  976. dev_set_drvdata(&pcidev->dev, NULL);
  977. mmc_free_host(sdhost->mmc);
  978. pci_release_regions(pcidev);
  979. pci_disable_device(pcidev);
  980. pr_info(DRV_NAME
  981. ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
  982. pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
  983. }
  984. static void __maybe_unused via_init_sdc_pm(struct via_crdr_mmc_host *host)
  985. {
  986. struct sdhcreg *pm_sdhcreg;
  987. void __iomem *addrbase;
  988. u32 lenreg;
  989. u16 status;
  990. pm_sdhcreg = &(host->pm_sdhc_reg);
  991. addrbase = host->sdhc_mmiobase;
  992. writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
  993. lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
  994. writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
  995. status = readw(addrbase + VIA_CRDR_SDSTATUS);
  996. status &= VIA_CRDR_SDSTS_W1C_MASK;
  997. writew(status, addrbase + VIA_CRDR_SDSTATUS);
  998. status = readw(addrbase + VIA_CRDR_SDSTATUS2);
  999. status |= VIA_CRDR_SDSTS_CFE;
  1000. writew(status, addrbase + VIA_CRDR_SDSTATUS2);
  1001. writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
  1002. writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
  1003. writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
  1004. writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
  1005. writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
  1006. writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
  1007. via_print_pcictrl(host);
  1008. via_print_sdchc(host);
  1009. }
  1010. static int __maybe_unused via_sd_suspend(struct device *dev)
  1011. {
  1012. struct via_crdr_mmc_host *host;
  1013. unsigned long flags;
  1014. host = dev_get_drvdata(dev);
  1015. spin_lock_irqsave(&host->lock, flags);
  1016. via_save_pcictrlreg(host);
  1017. via_save_sdcreg(host);
  1018. spin_unlock_irqrestore(&host->lock, flags);
  1019. device_wakeup_enable(dev);
  1020. return 0;
  1021. }
  1022. static int __maybe_unused via_sd_resume(struct device *dev)
  1023. {
  1024. struct via_crdr_mmc_host *sdhost;
  1025. int ret = 0;
  1026. u8 gatt;
  1027. sdhost = dev_get_drvdata(dev);
  1028. gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
  1029. if (sdhost->power == MMC_VDD_165_195)
  1030. gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
  1031. else
  1032. gatt |= VIA_CRDR_PCICLKGATT_3V3;
  1033. writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  1034. via_pwron_sleep(sdhost);
  1035. gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
  1036. writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
  1037. msleep(3);
  1038. msleep(100);
  1039. via_restore_pcictrlreg(sdhost);
  1040. via_init_sdc_pm(sdhost);
  1041. return ret;
  1042. }
  1043. static SIMPLE_DEV_PM_OPS(via_sd_pm_ops, via_sd_suspend, via_sd_resume);
  1044. static struct pci_driver via_sd_driver = {
  1045. .name = DRV_NAME,
  1046. .id_table = via_ids,
  1047. .probe = via_sd_probe,
  1048. .remove = via_sd_remove,
  1049. .driver.pm = &via_sd_pm_ops,
  1050. };
  1051. module_pci_driver(via_sd_driver);
  1052. MODULE_LICENSE("GPL");
  1053. MODULE_AUTHOR("VIA Technologies Inc.");
  1054. MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");