ushc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * USB SD Host Controller (USHC) controller driver.
  4. *
  5. * Copyright (C) 2010 Cambridge Silicon Radio Ltd.
  6. *
  7. * Notes:
  8. * - Only version 2 devices are supported.
  9. * - Version 2 devices only support SDIO cards/devices (R2 response is
  10. * unsupported).
  11. *
  12. * References:
  13. * [USHC] USB SD Host Controller specification (CS-118793-SP)
  14. */
  15. #include <linux/module.h>
  16. #include <linux/usb.h>
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/mmc/host.h>
  21. enum ushc_request {
  22. USHC_GET_CAPS = 0x00,
  23. USHC_HOST_CTRL = 0x01,
  24. USHC_PWR_CTRL = 0x02,
  25. USHC_CLK_FREQ = 0x03,
  26. USHC_EXEC_CMD = 0x04,
  27. USHC_READ_RESP = 0x05,
  28. USHC_RESET = 0x06,
  29. };
  30. enum ushc_request_type {
  31. USHC_GET_CAPS_TYPE = USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  32. USHC_HOST_CTRL_TYPE = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  33. USHC_PWR_CTRL_TYPE = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  34. USHC_CLK_FREQ_TYPE = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  35. USHC_EXEC_CMD_TYPE = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  36. USHC_READ_RESP_TYPE = USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  37. USHC_RESET_TYPE = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  38. };
  39. #define USHC_GET_CAPS_VERSION_MASK 0xff
  40. #define USHC_GET_CAPS_3V3 (1 << 8)
  41. #define USHC_GET_CAPS_3V0 (1 << 9)
  42. #define USHC_GET_CAPS_1V8 (1 << 10)
  43. #define USHC_GET_CAPS_HIGH_SPD (1 << 16)
  44. #define USHC_HOST_CTRL_4BIT (1 << 1)
  45. #define USHC_HOST_CTRL_HIGH_SPD (1 << 0)
  46. #define USHC_PWR_CTRL_OFF 0x00
  47. #define USHC_PWR_CTRL_3V3 0x01
  48. #define USHC_PWR_CTRL_3V0 0x02
  49. #define USHC_PWR_CTRL_1V8 0x03
  50. #define USHC_READ_RESP_BUSY (1 << 4)
  51. #define USHC_READ_RESP_ERR_TIMEOUT (1 << 3)
  52. #define USHC_READ_RESP_ERR_CRC (1 << 2)
  53. #define USHC_READ_RESP_ERR_DAT (1 << 1)
  54. #define USHC_READ_RESP_ERR_CMD (1 << 0)
  55. #define USHC_READ_RESP_ERR_MASK 0x0f
  56. struct ushc_cbw {
  57. __u8 signature;
  58. __u8 cmd_idx;
  59. __le16 block_size;
  60. __le32 arg;
  61. } __attribute__((packed));
  62. #define USHC_CBW_SIGNATURE 'C'
  63. struct ushc_csw {
  64. __u8 signature;
  65. __u8 status;
  66. __le32 response;
  67. } __attribute__((packed));
  68. #define USHC_CSW_SIGNATURE 'S'
  69. struct ushc_int_data {
  70. u8 status;
  71. u8 reserved[3];
  72. };
  73. #define USHC_INT_STATUS_SDIO_INT (1 << 1)
  74. #define USHC_INT_STATUS_CARD_PRESENT (1 << 0)
  75. struct ushc_data {
  76. struct usb_device *usb_dev;
  77. struct mmc_host *mmc;
  78. struct urb *int_urb;
  79. struct ushc_int_data *int_data;
  80. struct urb *cbw_urb;
  81. struct ushc_cbw *cbw;
  82. struct urb *data_urb;
  83. struct urb *csw_urb;
  84. struct ushc_csw *csw;
  85. spinlock_t lock;
  86. struct mmc_request *current_req;
  87. u32 caps;
  88. u16 host_ctrl;
  89. unsigned long flags;
  90. u8 last_status;
  91. int clock_freq;
  92. };
  93. #define DISCONNECTED 0
  94. #define INT_EN 1
  95. #define IGNORE_NEXT_INT 2
  96. static void data_callback(struct urb *urb);
  97. static int ushc_hw_reset(struct ushc_data *ushc)
  98. {
  99. return usb_control_msg(ushc->usb_dev, usb_sndctrlpipe(ushc->usb_dev, 0),
  100. USHC_RESET, USHC_RESET_TYPE,
  101. 0, 0, NULL, 0, 100);
  102. }
  103. static int ushc_hw_get_caps(struct ushc_data *ushc)
  104. {
  105. int ret;
  106. int version;
  107. ret = usb_control_msg(ushc->usb_dev, usb_rcvctrlpipe(ushc->usb_dev, 0),
  108. USHC_GET_CAPS, USHC_GET_CAPS_TYPE,
  109. 0, 0, &ushc->caps, sizeof(ushc->caps), 100);
  110. if (ret < 0)
  111. return ret;
  112. ushc->caps = le32_to_cpu(ushc->caps);
  113. version = ushc->caps & USHC_GET_CAPS_VERSION_MASK;
  114. if (version != 0x02) {
  115. dev_err(&ushc->usb_dev->dev, "controller version %d is not supported\n", version);
  116. return -EINVAL;
  117. }
  118. return 0;
  119. }
  120. static int ushc_hw_set_host_ctrl(struct ushc_data *ushc, u16 mask, u16 val)
  121. {
  122. u16 host_ctrl;
  123. int ret;
  124. host_ctrl = (ushc->host_ctrl & ~mask) | val;
  125. ret = usb_control_msg(ushc->usb_dev, usb_sndctrlpipe(ushc->usb_dev, 0),
  126. USHC_HOST_CTRL, USHC_HOST_CTRL_TYPE,
  127. host_ctrl, 0, NULL, 0, 100);
  128. if (ret < 0)
  129. return ret;
  130. ushc->host_ctrl = host_ctrl;
  131. return 0;
  132. }
  133. static void int_callback(struct urb *urb)
  134. {
  135. struct ushc_data *ushc = urb->context;
  136. u8 status, last_status;
  137. if (urb->status < 0)
  138. return;
  139. status = ushc->int_data->status;
  140. last_status = ushc->last_status;
  141. ushc->last_status = status;
  142. /*
  143. * Ignore the card interrupt status on interrupt transfers that
  144. * were submitted while card interrupts where disabled.
  145. *
  146. * This avoid occasional spurious interrupts when enabling
  147. * interrupts immediately after clearing the source on the card.
  148. */
  149. if (!test_and_clear_bit(IGNORE_NEXT_INT, &ushc->flags)
  150. && test_bit(INT_EN, &ushc->flags)
  151. && status & USHC_INT_STATUS_SDIO_INT) {
  152. mmc_signal_sdio_irq(ushc->mmc);
  153. }
  154. if ((status ^ last_status) & USHC_INT_STATUS_CARD_PRESENT)
  155. mmc_detect_change(ushc->mmc, msecs_to_jiffies(100));
  156. if (!test_bit(INT_EN, &ushc->flags))
  157. set_bit(IGNORE_NEXT_INT, &ushc->flags);
  158. usb_submit_urb(ushc->int_urb, GFP_ATOMIC);
  159. }
  160. static void cbw_callback(struct urb *urb)
  161. {
  162. struct ushc_data *ushc = urb->context;
  163. if (urb->status != 0) {
  164. usb_unlink_urb(ushc->data_urb);
  165. usb_unlink_urb(ushc->csw_urb);
  166. }
  167. }
  168. static void data_callback(struct urb *urb)
  169. {
  170. struct ushc_data *ushc = urb->context;
  171. if (urb->status != 0)
  172. usb_unlink_urb(ushc->csw_urb);
  173. }
  174. static void csw_callback(struct urb *urb)
  175. {
  176. struct ushc_data *ushc = urb->context;
  177. struct mmc_request *req = ushc->current_req;
  178. int status;
  179. status = ushc->csw->status;
  180. if (urb->status != 0) {
  181. req->cmd->error = urb->status;
  182. } else if (status & USHC_READ_RESP_ERR_CMD) {
  183. if (status & USHC_READ_RESP_ERR_CRC)
  184. req->cmd->error = -EIO;
  185. else
  186. req->cmd->error = -ETIMEDOUT;
  187. }
  188. if (req->data) {
  189. if (status & USHC_READ_RESP_ERR_DAT) {
  190. if (status & USHC_READ_RESP_ERR_CRC)
  191. req->data->error = -EIO;
  192. else
  193. req->data->error = -ETIMEDOUT;
  194. req->data->bytes_xfered = 0;
  195. } else {
  196. req->data->bytes_xfered = req->data->blksz * req->data->blocks;
  197. }
  198. }
  199. req->cmd->resp[0] = le32_to_cpu(ushc->csw->response);
  200. mmc_request_done(ushc->mmc, req);
  201. }
  202. static void ushc_request(struct mmc_host *mmc, struct mmc_request *req)
  203. {
  204. struct ushc_data *ushc = mmc_priv(mmc);
  205. int ret;
  206. unsigned long flags;
  207. spin_lock_irqsave(&ushc->lock, flags);
  208. if (test_bit(DISCONNECTED, &ushc->flags)) {
  209. ret = -ENODEV;
  210. goto out;
  211. }
  212. /* Version 2 firmware doesn't support the R2 response format. */
  213. if (req->cmd->flags & MMC_RSP_136) {
  214. ret = -EINVAL;
  215. goto out;
  216. }
  217. /* The Astoria's data FIFOs don't work with clock speeds < 5MHz so
  218. limit commands with data to 6MHz or more. */
  219. if (req->data && ushc->clock_freq < 6000000) {
  220. ret = -EINVAL;
  221. goto out;
  222. }
  223. ushc->current_req = req;
  224. /* Start cmd with CBW. */
  225. ushc->cbw->cmd_idx = cpu_to_le16(req->cmd->opcode);
  226. if (req->data)
  227. ushc->cbw->block_size = cpu_to_le16(req->data->blksz);
  228. else
  229. ushc->cbw->block_size = 0;
  230. ushc->cbw->arg = cpu_to_le32(req->cmd->arg);
  231. ret = usb_submit_urb(ushc->cbw_urb, GFP_ATOMIC);
  232. if (ret < 0)
  233. goto out;
  234. /* Submit data (if any). */
  235. if (req->data) {
  236. struct mmc_data *data = req->data;
  237. int pipe;
  238. if (data->flags & MMC_DATA_READ)
  239. pipe = usb_rcvbulkpipe(ushc->usb_dev, 6);
  240. else
  241. pipe = usb_sndbulkpipe(ushc->usb_dev, 2);
  242. usb_fill_bulk_urb(ushc->data_urb, ushc->usb_dev, pipe,
  243. NULL, data->sg->length,
  244. data_callback, ushc);
  245. ushc->data_urb->num_sgs = 1;
  246. ushc->data_urb->sg = data->sg;
  247. ret = usb_submit_urb(ushc->data_urb, GFP_ATOMIC);
  248. if (ret < 0)
  249. goto out;
  250. }
  251. /* Submit CSW. */
  252. ret = usb_submit_urb(ushc->csw_urb, GFP_ATOMIC);
  253. out:
  254. spin_unlock_irqrestore(&ushc->lock, flags);
  255. if (ret < 0) {
  256. usb_unlink_urb(ushc->cbw_urb);
  257. usb_unlink_urb(ushc->data_urb);
  258. req->cmd->error = ret;
  259. mmc_request_done(mmc, req);
  260. }
  261. }
  262. static int ushc_set_power(struct ushc_data *ushc, unsigned char power_mode)
  263. {
  264. u16 voltage;
  265. switch (power_mode) {
  266. case MMC_POWER_OFF:
  267. voltage = USHC_PWR_CTRL_OFF;
  268. break;
  269. case MMC_POWER_UP:
  270. case MMC_POWER_ON:
  271. voltage = USHC_PWR_CTRL_3V3;
  272. break;
  273. default:
  274. return -EINVAL;
  275. }
  276. return usb_control_msg(ushc->usb_dev, usb_sndctrlpipe(ushc->usb_dev, 0),
  277. USHC_PWR_CTRL, USHC_PWR_CTRL_TYPE,
  278. voltage, 0, NULL, 0, 100);
  279. }
  280. static int ushc_set_bus_width(struct ushc_data *ushc, int bus_width)
  281. {
  282. return ushc_hw_set_host_ctrl(ushc, USHC_HOST_CTRL_4BIT,
  283. bus_width == 4 ? USHC_HOST_CTRL_4BIT : 0);
  284. }
  285. static int ushc_set_bus_freq(struct ushc_data *ushc, int clk, bool enable_hs)
  286. {
  287. int ret;
  288. /* Hardware can't detect interrupts while the clock is off. */
  289. if (clk == 0)
  290. clk = 400000;
  291. ret = ushc_hw_set_host_ctrl(ushc, USHC_HOST_CTRL_HIGH_SPD,
  292. enable_hs ? USHC_HOST_CTRL_HIGH_SPD : 0);
  293. if (ret < 0)
  294. return ret;
  295. ret = usb_control_msg(ushc->usb_dev, usb_sndctrlpipe(ushc->usb_dev, 0),
  296. USHC_CLK_FREQ, USHC_CLK_FREQ_TYPE,
  297. clk & 0xffff, (clk >> 16) & 0xffff, NULL, 0, 100);
  298. if (ret < 0)
  299. return ret;
  300. ushc->clock_freq = clk;
  301. return 0;
  302. }
  303. static void ushc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  304. {
  305. struct ushc_data *ushc = mmc_priv(mmc);
  306. ushc_set_power(ushc, ios->power_mode);
  307. ushc_set_bus_width(ushc, 1 << ios->bus_width);
  308. ushc_set_bus_freq(ushc, ios->clock, ios->timing == MMC_TIMING_SD_HS);
  309. }
  310. static int ushc_get_cd(struct mmc_host *mmc)
  311. {
  312. struct ushc_data *ushc = mmc_priv(mmc);
  313. return !!(ushc->last_status & USHC_INT_STATUS_CARD_PRESENT);
  314. }
  315. static void ushc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  316. {
  317. struct ushc_data *ushc = mmc_priv(mmc);
  318. if (enable)
  319. set_bit(INT_EN, &ushc->flags);
  320. else
  321. clear_bit(INT_EN, &ushc->flags);
  322. }
  323. static void ushc_clean_up(struct ushc_data *ushc)
  324. {
  325. usb_free_urb(ushc->int_urb);
  326. usb_free_urb(ushc->csw_urb);
  327. usb_free_urb(ushc->data_urb);
  328. usb_free_urb(ushc->cbw_urb);
  329. kfree(ushc->int_data);
  330. kfree(ushc->cbw);
  331. kfree(ushc->csw);
  332. mmc_free_host(ushc->mmc);
  333. }
  334. static const struct mmc_host_ops ushc_ops = {
  335. .request = ushc_request,
  336. .set_ios = ushc_set_ios,
  337. .get_cd = ushc_get_cd,
  338. .enable_sdio_irq = ushc_enable_sdio_irq,
  339. };
  340. static int ushc_probe(struct usb_interface *intf, const struct usb_device_id *id)
  341. {
  342. struct usb_device *usb_dev = interface_to_usbdev(intf);
  343. struct mmc_host *mmc;
  344. struct ushc_data *ushc;
  345. int ret;
  346. if (intf->cur_altsetting->desc.bNumEndpoints < 1)
  347. return -ENODEV;
  348. mmc = mmc_alloc_host(sizeof(struct ushc_data), &intf->dev);
  349. if (mmc == NULL)
  350. return -ENOMEM;
  351. ushc = mmc_priv(mmc);
  352. usb_set_intfdata(intf, ushc);
  353. ushc->usb_dev = usb_dev;
  354. ushc->mmc = mmc;
  355. spin_lock_init(&ushc->lock);
  356. ret = ushc_hw_reset(ushc);
  357. if (ret < 0)
  358. goto err;
  359. /* Read capabilities. */
  360. ret = ushc_hw_get_caps(ushc);
  361. if (ret < 0)
  362. goto err;
  363. mmc->ops = &ushc_ops;
  364. mmc->f_min = 400000;
  365. mmc->f_max = 50000000;
  366. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  367. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
  368. mmc->caps |= (ushc->caps & USHC_GET_CAPS_HIGH_SPD) ? MMC_CAP_SD_HIGHSPEED : 0;
  369. mmc->max_seg_size = 512*511;
  370. mmc->max_segs = 1;
  371. mmc->max_req_size = 512*511;
  372. mmc->max_blk_size = 512;
  373. mmc->max_blk_count = 511;
  374. ushc->int_urb = usb_alloc_urb(0, GFP_KERNEL);
  375. if (ushc->int_urb == NULL) {
  376. ret = -ENOMEM;
  377. goto err;
  378. }
  379. ushc->int_data = kzalloc(sizeof(struct ushc_int_data), GFP_KERNEL);
  380. if (ushc->int_data == NULL) {
  381. ret = -ENOMEM;
  382. goto err;
  383. }
  384. usb_fill_int_urb(ushc->int_urb, ushc->usb_dev,
  385. usb_rcvintpipe(usb_dev,
  386. intf->cur_altsetting->endpoint[0].desc.bEndpointAddress),
  387. ushc->int_data, sizeof(struct ushc_int_data),
  388. int_callback, ushc,
  389. intf->cur_altsetting->endpoint[0].desc.bInterval);
  390. ushc->cbw_urb = usb_alloc_urb(0, GFP_KERNEL);
  391. if (ushc->cbw_urb == NULL) {
  392. ret = -ENOMEM;
  393. goto err;
  394. }
  395. ushc->cbw = kzalloc(sizeof(struct ushc_cbw), GFP_KERNEL);
  396. if (ushc->cbw == NULL) {
  397. ret = -ENOMEM;
  398. goto err;
  399. }
  400. ushc->cbw->signature = USHC_CBW_SIGNATURE;
  401. usb_fill_bulk_urb(ushc->cbw_urb, ushc->usb_dev, usb_sndbulkpipe(usb_dev, 2),
  402. ushc->cbw, sizeof(struct ushc_cbw),
  403. cbw_callback, ushc);
  404. ushc->data_urb = usb_alloc_urb(0, GFP_KERNEL);
  405. if (ushc->data_urb == NULL) {
  406. ret = -ENOMEM;
  407. goto err;
  408. }
  409. ushc->csw_urb = usb_alloc_urb(0, GFP_KERNEL);
  410. if (ushc->csw_urb == NULL) {
  411. ret = -ENOMEM;
  412. goto err;
  413. }
  414. ushc->csw = kzalloc(sizeof(struct ushc_csw), GFP_KERNEL);
  415. if (ushc->csw == NULL) {
  416. ret = -ENOMEM;
  417. goto err;
  418. }
  419. usb_fill_bulk_urb(ushc->csw_urb, ushc->usb_dev, usb_rcvbulkpipe(usb_dev, 6),
  420. ushc->csw, sizeof(struct ushc_csw),
  421. csw_callback, ushc);
  422. ret = mmc_add_host(ushc->mmc);
  423. if (ret)
  424. goto err;
  425. ret = usb_submit_urb(ushc->int_urb, GFP_KERNEL);
  426. if (ret < 0) {
  427. mmc_remove_host(ushc->mmc);
  428. goto err;
  429. }
  430. return 0;
  431. err:
  432. ushc_clean_up(ushc);
  433. return ret;
  434. }
  435. static void ushc_disconnect(struct usb_interface *intf)
  436. {
  437. struct ushc_data *ushc = usb_get_intfdata(intf);
  438. spin_lock_irq(&ushc->lock);
  439. set_bit(DISCONNECTED, &ushc->flags);
  440. spin_unlock_irq(&ushc->lock);
  441. usb_kill_urb(ushc->int_urb);
  442. usb_kill_urb(ushc->cbw_urb);
  443. usb_kill_urb(ushc->data_urb);
  444. usb_kill_urb(ushc->csw_urb);
  445. mmc_remove_host(ushc->mmc);
  446. ushc_clean_up(ushc);
  447. }
  448. static struct usb_device_id ushc_id_table[] = {
  449. /* CSR USB SD Host Controller */
  450. { USB_DEVICE(0x0a12, 0x5d10) },
  451. { },
  452. };
  453. MODULE_DEVICE_TABLE(usb, ushc_id_table);
  454. static struct usb_driver ushc_driver = {
  455. .name = "ushc",
  456. .id_table = ushc_id_table,
  457. .probe = ushc_probe,
  458. .disconnect = ushc_disconnect,
  459. };
  460. module_usb_driver(ushc_driver);
  461. MODULE_DESCRIPTION("USB SD Host Controller driver");
  462. MODULE_AUTHOR("David Vrabel <david.vrabel@csr.com>");
  463. MODULE_LICENSE("GPL");