uniphier-sd.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2017-2018 Socionext Inc.
  4. // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. #include <linux/bitfield.h>
  6. #include <linux/bitops.h>
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/mfd/tmio.h>
  11. #include <linux/mmc/host.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pinctrl/consumer.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/reset.h>
  18. #include "tmio_mmc.h"
  19. #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16)
  20. #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10)
  21. #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
  22. #define UNIPHIER_SD_CC_EXT_MODE 0x1b0
  23. #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1)
  24. #define UNIPHIER_SD_HOST_MODE 0x1c8
  25. #define UNIPHIER_SD_VOLT 0x1e4
  26. #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)
  27. #define UNIPHIER_SD_VOLT_OFF 0
  28. #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal
  29. #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal
  30. #define UNIPHIER_SD_DMA_MODE 0x410
  31. #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)
  32. #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0
  33. #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
  34. #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)
  35. #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0
  36. #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1
  37. #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2
  38. #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3
  39. #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed
  40. #define UNIPHIER_SD_DMA_CTL 0x414
  41. #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared)
  42. #define UNIPHIER_SD_DMA_RST 0x418
  43. #define UNIPHIER_SD_DMA_RST_CH1 BIT(9)
  44. #define UNIPHIER_SD_DMA_RST_CH0 BIT(8)
  45. #define UNIPHIER_SD_DMA_ADDR_L 0x440
  46. #define UNIPHIER_SD_DMA_ADDR_H 0x444
  47. /*
  48. * IP is extended to support various features: built-in DMA engine,
  49. * 1/1024 divisor, etc.
  50. */
  51. #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0)
  52. /* RX channel of the built-in DMA controller is broken (Pro5) */
  53. #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1)
  54. struct uniphier_sd_priv {
  55. struct tmio_mmc_data tmio_data;
  56. struct pinctrl *pinctrl;
  57. struct pinctrl_state *pinstate_uhs;
  58. struct clk *clk;
  59. struct reset_control *rst;
  60. struct reset_control *rst_br;
  61. struct reset_control *rst_hw;
  62. struct dma_chan *chan;
  63. enum dma_data_direction dma_dir;
  64. unsigned long clk_rate;
  65. unsigned long caps;
  66. };
  67. static void *uniphier_sd_priv(struct tmio_mmc_host *host)
  68. {
  69. return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
  70. }
  71. static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
  72. {
  73. sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
  74. }
  75. /* external DMA engine */
  76. static void uniphier_sd_external_dma_issue(unsigned long arg)
  77. {
  78. struct tmio_mmc_host *host = (void *)arg;
  79. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  80. uniphier_sd_dma_endisable(host, 1);
  81. dma_async_issue_pending(priv->chan);
  82. }
  83. static void uniphier_sd_external_dma_callback(void *param,
  84. const struct dmaengine_result *result)
  85. {
  86. struct tmio_mmc_host *host = param;
  87. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  88. unsigned long flags;
  89. dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
  90. priv->dma_dir);
  91. spin_lock_irqsave(&host->lock, flags);
  92. if (result->result == DMA_TRANS_NOERROR) {
  93. /*
  94. * When the external DMA engine is enabled, strangely enough,
  95. * the DATAEND flag can be asserted even if the DMA engine has
  96. * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only
  97. * after we make sure the DMA engine finishes the transfer,
  98. * hence, in this callback.
  99. */
  100. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  101. } else {
  102. host->data->error = -ETIMEDOUT;
  103. tmio_mmc_do_data_irq(host);
  104. }
  105. spin_unlock_irqrestore(&host->lock, flags);
  106. }
  107. static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
  108. struct mmc_data *data)
  109. {
  110. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  111. enum dma_transfer_direction dma_tx_dir;
  112. struct dma_async_tx_descriptor *desc;
  113. dma_cookie_t cookie;
  114. int sg_len;
  115. if (!priv->chan)
  116. goto force_pio;
  117. if (data->flags & MMC_DATA_READ) {
  118. priv->dma_dir = DMA_FROM_DEVICE;
  119. dma_tx_dir = DMA_DEV_TO_MEM;
  120. } else {
  121. priv->dma_dir = DMA_TO_DEVICE;
  122. dma_tx_dir = DMA_MEM_TO_DEV;
  123. }
  124. sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
  125. priv->dma_dir);
  126. if (sg_len == 0)
  127. goto force_pio;
  128. desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
  129. dma_tx_dir, DMA_CTRL_ACK);
  130. if (!desc)
  131. goto unmap_sg;
  132. desc->callback_result = uniphier_sd_external_dma_callback;
  133. desc->callback_param = host;
  134. cookie = dmaengine_submit(desc);
  135. if (cookie < 0)
  136. goto unmap_sg;
  137. host->dma_on = true;
  138. return;
  139. unmap_sg:
  140. dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
  141. priv->dma_dir);
  142. force_pio:
  143. uniphier_sd_dma_endisable(host, 0);
  144. }
  145. static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
  146. bool enable)
  147. {
  148. }
  149. static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
  150. struct tmio_mmc_data *pdata)
  151. {
  152. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  153. struct dma_chan *chan;
  154. chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
  155. if (IS_ERR(chan)) {
  156. dev_warn(mmc_dev(host->mmc),
  157. "failed to request DMA channel. falling back to PIO\n");
  158. return; /* just use PIO even for -EPROBE_DEFER */
  159. }
  160. /* this driver uses a single channel for both RX an TX */
  161. priv->chan = chan;
  162. host->chan_rx = chan;
  163. host->chan_tx = chan;
  164. tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
  165. (unsigned long)host);
  166. }
  167. static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
  168. {
  169. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  170. if (priv->chan)
  171. dma_release_channel(priv->chan);
  172. }
  173. static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
  174. {
  175. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  176. uniphier_sd_dma_endisable(host, 0);
  177. if (priv->chan)
  178. dmaengine_terminate_sync(priv->chan);
  179. }
  180. static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
  181. {
  182. uniphier_sd_dma_endisable(host, 0);
  183. tmio_mmc_do_data_irq(host);
  184. }
  185. static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
  186. .start = uniphier_sd_external_dma_start,
  187. .enable = uniphier_sd_external_dma_enable,
  188. .request = uniphier_sd_external_dma_request,
  189. .release = uniphier_sd_external_dma_release,
  190. .abort = uniphier_sd_external_dma_abort,
  191. .dataend = uniphier_sd_external_dma_dataend,
  192. };
  193. static void uniphier_sd_internal_dma_issue(unsigned long arg)
  194. {
  195. struct tmio_mmc_host *host = (void *)arg;
  196. unsigned long flags;
  197. spin_lock_irqsave(&host->lock, flags);
  198. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  199. spin_unlock_irqrestore(&host->lock, flags);
  200. uniphier_sd_dma_endisable(host, 1);
  201. writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
  202. }
  203. static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
  204. struct mmc_data *data)
  205. {
  206. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  207. struct scatterlist *sg = host->sg_ptr;
  208. dma_addr_t dma_addr;
  209. unsigned int dma_mode_dir;
  210. u32 dma_mode;
  211. int sg_len;
  212. if ((data->flags & MMC_DATA_READ) && !host->chan_rx)
  213. goto force_pio;
  214. if (WARN_ON(host->sg_len != 1))
  215. goto force_pio;
  216. if (!IS_ALIGNED(sg->offset, 8))
  217. goto force_pio;
  218. if (data->flags & MMC_DATA_READ) {
  219. priv->dma_dir = DMA_FROM_DEVICE;
  220. dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
  221. } else {
  222. priv->dma_dir = DMA_TO_DEVICE;
  223. dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
  224. }
  225. sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
  226. if (sg_len == 0)
  227. goto force_pio;
  228. dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
  229. dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
  230. UNIPHIER_SD_DMA_MODE_WIDTH_64);
  231. dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
  232. writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
  233. dma_addr = sg_dma_address(data->sg);
  234. writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
  235. writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
  236. host->dma_on = true;
  237. return;
  238. force_pio:
  239. uniphier_sd_dma_endisable(host, 0);
  240. }
  241. static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
  242. bool enable)
  243. {
  244. }
  245. static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
  246. struct tmio_mmc_data *pdata)
  247. {
  248. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  249. /*
  250. * Due to a hardware bug, Pro5 cannot use DMA for RX.
  251. * We can still use DMA for TX, but PIO for RX.
  252. */
  253. if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
  254. host->chan_rx = (void *)0xdeadbeaf;
  255. host->chan_tx = (void *)0xdeadbeaf;
  256. tasklet_init(&host->dma_issue, uniphier_sd_internal_dma_issue,
  257. (unsigned long)host);
  258. }
  259. static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
  260. {
  261. /* Each value is set to zero to assume "disabling" each DMA */
  262. host->chan_rx = NULL;
  263. host->chan_tx = NULL;
  264. }
  265. static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
  266. {
  267. u32 tmp;
  268. uniphier_sd_dma_endisable(host, 0);
  269. tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
  270. tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
  271. writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
  272. tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
  273. writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
  274. }
  275. static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
  276. {
  277. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  278. uniphier_sd_dma_endisable(host, 0);
  279. dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
  280. tmio_mmc_do_data_irq(host);
  281. }
  282. static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
  283. .start = uniphier_sd_internal_dma_start,
  284. .enable = uniphier_sd_internal_dma_enable,
  285. .request = uniphier_sd_internal_dma_request,
  286. .release = uniphier_sd_internal_dma_release,
  287. .abort = uniphier_sd_internal_dma_abort,
  288. .dataend = uniphier_sd_internal_dma_dataend,
  289. };
  290. static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
  291. {
  292. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  293. struct mmc_host *mmc = host->mmc;
  294. int ret;
  295. ret = clk_prepare_enable(priv->clk);
  296. if (ret)
  297. return ret;
  298. ret = clk_set_rate(priv->clk, ULONG_MAX);
  299. if (ret)
  300. goto disable_clk;
  301. priv->clk_rate = clk_get_rate(priv->clk);
  302. /* If max-frequency property is set, use it. */
  303. if (!mmc->f_max)
  304. mmc->f_max = priv->clk_rate;
  305. /*
  306. * 1/512 is the finest divisor in the original IP. Newer versions
  307. * also supports 1/1024 divisor. (UniPhier-specific extension)
  308. */
  309. if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
  310. mmc->f_min = priv->clk_rate / 1024;
  311. else
  312. mmc->f_min = priv->clk_rate / 512;
  313. ret = reset_control_deassert(priv->rst);
  314. if (ret)
  315. goto disable_clk;
  316. ret = reset_control_deassert(priv->rst_br);
  317. if (ret)
  318. goto assert_rst;
  319. return 0;
  320. assert_rst:
  321. reset_control_assert(priv->rst);
  322. disable_clk:
  323. clk_disable_unprepare(priv->clk);
  324. return ret;
  325. }
  326. static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
  327. {
  328. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  329. reset_control_assert(priv->rst_br);
  330. reset_control_assert(priv->rst);
  331. clk_disable_unprepare(priv->clk);
  332. }
  333. static void uniphier_sd_hw_reset(struct mmc_host *mmc)
  334. {
  335. struct tmio_mmc_host *host = mmc_priv(mmc);
  336. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  337. reset_control_assert(priv->rst_hw);
  338. /* For eMMC, minimum is 1us but give it 9us for good measure */
  339. udelay(9);
  340. reset_control_deassert(priv->rst_hw);
  341. /* For eMMC, minimum is 200us but give it 300us for good measure */
  342. usleep_range(300, 1000);
  343. }
  344. static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
  345. unsigned int clock)
  346. {
  347. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  348. unsigned long divisor;
  349. u32 tmp;
  350. tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
  351. /* stop the clock before changing its rate to avoid a glitch signal */
  352. tmp &= ~CLK_CTL_SCLKEN;
  353. writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
  354. if (clock == 0)
  355. return;
  356. tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
  357. tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
  358. tmp &= ~CLK_CTL_DIV_MASK;
  359. divisor = priv->clk_rate / clock;
  360. /*
  361. * In the original IP, bit[7:0] represents the divisor.
  362. * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
  363. *
  364. * The IP does not define a way to achieve 1/1. For UniPhier variants,
  365. * bit10 is used for 1/1. Newer versions of UniPhier variants use
  366. * bit16 for 1/1024.
  367. */
  368. if (divisor <= 1)
  369. tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
  370. else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
  371. tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
  372. else
  373. tmp |= roundup_pow_of_two(divisor) >> 2;
  374. writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
  375. tmp |= CLK_CTL_SCLKEN;
  376. writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
  377. }
  378. static void uniphier_sd_host_init(struct tmio_mmc_host *host)
  379. {
  380. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  381. u32 val;
  382. /*
  383. * Connected to 32bit AXI.
  384. * This register holds settings for SoC-specific internal bus
  385. * connection. What is worse, the register spec was changed,
  386. * breaking the backward compatibility. Write an appropriate
  387. * value depending on a flag associated with a compatible string.
  388. */
  389. if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
  390. val = 0x00000101;
  391. else
  392. val = 0x00000000;
  393. writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
  394. val = 0;
  395. /*
  396. * If supported, the controller can automatically
  397. * enable/disable the clock line to the card.
  398. */
  399. if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
  400. val |= UNIPHIER_SD_CLKCTL_OFFEN;
  401. writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
  402. }
  403. static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
  404. struct mmc_ios *ios)
  405. {
  406. struct tmio_mmc_host *host = mmc_priv(mmc);
  407. struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
  408. struct pinctrl_state *pinstate = NULL;
  409. u32 val, tmp;
  410. switch (ios->signal_voltage) {
  411. case MMC_SIGNAL_VOLTAGE_330:
  412. val = UNIPHIER_SD_VOLT_330;
  413. break;
  414. case MMC_SIGNAL_VOLTAGE_180:
  415. val = UNIPHIER_SD_VOLT_180;
  416. pinstate = priv->pinstate_uhs;
  417. break;
  418. default:
  419. return -ENOTSUPP;
  420. }
  421. tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
  422. tmp &= ~UNIPHIER_SD_VOLT_MASK;
  423. tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
  424. writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
  425. if (pinstate)
  426. pinctrl_select_state(priv->pinctrl, pinstate);
  427. else
  428. pinctrl_select_default_state(mmc_dev(mmc));
  429. return 0;
  430. }
  431. static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
  432. struct uniphier_sd_priv *priv)
  433. {
  434. priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
  435. if (IS_ERR(priv->pinctrl))
  436. return PTR_ERR(priv->pinctrl);
  437. priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
  438. if (IS_ERR(priv->pinstate_uhs))
  439. return PTR_ERR(priv->pinstate_uhs);
  440. host->ops.start_signal_voltage_switch =
  441. uniphier_sd_start_signal_voltage_switch;
  442. return 0;
  443. }
  444. static int uniphier_sd_probe(struct platform_device *pdev)
  445. {
  446. struct device *dev = &pdev->dev;
  447. struct uniphier_sd_priv *priv;
  448. struct tmio_mmc_data *tmio_data;
  449. struct tmio_mmc_host *host;
  450. int irq, ret;
  451. irq = platform_get_irq(pdev, 0);
  452. if (irq < 0)
  453. return irq;
  454. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  455. if (!priv)
  456. return -ENOMEM;
  457. priv->caps = (unsigned long)of_device_get_match_data(dev);
  458. priv->clk = devm_clk_get(dev, NULL);
  459. if (IS_ERR(priv->clk)) {
  460. dev_err(dev, "failed to get clock\n");
  461. return PTR_ERR(priv->clk);
  462. }
  463. priv->rst = devm_reset_control_get_shared(dev, "host");
  464. if (IS_ERR(priv->rst)) {
  465. dev_err(dev, "failed to get host reset\n");
  466. return PTR_ERR(priv->rst);
  467. }
  468. /* old version has one more reset */
  469. if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
  470. priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
  471. if (IS_ERR(priv->rst_br)) {
  472. dev_err(dev, "failed to get bridge reset\n");
  473. return PTR_ERR(priv->rst_br);
  474. }
  475. }
  476. tmio_data = &priv->tmio_data;
  477. tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
  478. host = tmio_mmc_host_alloc(pdev, tmio_data);
  479. if (IS_ERR(host))
  480. return PTR_ERR(host);
  481. if (host->mmc->caps & MMC_CAP_HW_RESET) {
  482. priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
  483. if (IS_ERR(priv->rst_hw)) {
  484. dev_err(dev, "failed to get hw reset\n");
  485. ret = PTR_ERR(priv->rst_hw);
  486. goto free_host;
  487. }
  488. host->ops.hw_reset = uniphier_sd_hw_reset;
  489. }
  490. if (host->mmc->caps & MMC_CAP_UHS) {
  491. ret = uniphier_sd_uhs_init(host, priv);
  492. if (ret) {
  493. dev_warn(dev,
  494. "failed to setup UHS (error %d). Disabling UHS.",
  495. ret);
  496. host->mmc->caps &= ~MMC_CAP_UHS;
  497. }
  498. }
  499. if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
  500. host->dma_ops = &uniphier_sd_internal_dma_ops;
  501. else
  502. host->dma_ops = &uniphier_sd_external_dma_ops;
  503. host->bus_shift = 1;
  504. host->clk_enable = uniphier_sd_clk_enable;
  505. host->clk_disable = uniphier_sd_clk_disable;
  506. host->set_clock = uniphier_sd_set_clock;
  507. ret = uniphier_sd_clk_enable(host);
  508. if (ret)
  509. goto free_host;
  510. uniphier_sd_host_init(host);
  511. tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
  512. if (host->mmc->caps & MMC_CAP_UHS)
  513. tmio_data->ocr_mask |= MMC_VDD_165_195;
  514. tmio_data->max_segs = 1;
  515. tmio_data->max_blk_count = U16_MAX;
  516. ret = tmio_mmc_host_probe(host);
  517. if (ret)
  518. goto disable_clk;
  519. ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
  520. dev_name(dev), host);
  521. if (ret)
  522. goto remove_host;
  523. return 0;
  524. remove_host:
  525. tmio_mmc_host_remove(host);
  526. disable_clk:
  527. uniphier_sd_clk_disable(host);
  528. free_host:
  529. tmio_mmc_host_free(host);
  530. return ret;
  531. }
  532. static int uniphier_sd_remove(struct platform_device *pdev)
  533. {
  534. struct tmio_mmc_host *host = platform_get_drvdata(pdev);
  535. tmio_mmc_host_remove(host);
  536. uniphier_sd_clk_disable(host);
  537. tmio_mmc_host_free(host);
  538. return 0;
  539. }
  540. static const struct of_device_id uniphier_sd_match[] = {
  541. {
  542. .compatible = "socionext,uniphier-sd-v2.91",
  543. },
  544. {
  545. .compatible = "socionext,uniphier-sd-v3.1",
  546. .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
  547. UNIPHIER_SD_CAP_BROKEN_DMA_RX),
  548. },
  549. {
  550. .compatible = "socionext,uniphier-sd-v3.1.1",
  551. .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
  552. },
  553. { /* sentinel */ }
  554. };
  555. MODULE_DEVICE_TABLE(of, uniphier_sd_match);
  556. static struct platform_driver uniphier_sd_driver = {
  557. .probe = uniphier_sd_probe,
  558. .remove = uniphier_sd_remove,
  559. .driver = {
  560. .name = "uniphier-sd",
  561. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  562. .of_match_table = uniphier_sd_match,
  563. },
  564. };
  565. module_platform_driver(uniphier_sd_driver);
  566. MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
  567. MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
  568. MODULE_LICENSE("GPL v2");