toshsd.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Toshiba PCI Secure Digital Host Controller Interface driver
  4. *
  5. * Copyright (C) 2014 Ondrej Zary
  6. * Copyright (C) 2007 Richard Betts, All Rights Reserved.
  7. *
  8. * Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and,
  9. * sdhci.c, copyright (C) 2005-2006 Pierre Ossman
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/module.h>
  14. #include <linux/pci.h>
  15. #include <linux/scatterlist.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/pm.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/mmc/mmc.h>
  22. #include "toshsd.h"
  23. #define DRIVER_NAME "toshsd"
  24. static const struct pci_device_id pci_ids[] = {
  25. { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0805) },
  26. { /* end: all zeroes */ },
  27. };
  28. MODULE_DEVICE_TABLE(pci, pci_ids);
  29. static void toshsd_init(struct toshsd_host *host)
  30. {
  31. /* enable clock */
  32. pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP,
  33. SD_PCICFG_CLKSTOP_ENABLE_ALL);
  34. pci_write_config_byte(host->pdev, SD_PCICFG_CARDDETECT, 2);
  35. /* reset */
  36. iowrite16(0, host->ioaddr + SD_SOFTWARERESET); /* assert */
  37. mdelay(2);
  38. iowrite16(1, host->ioaddr + SD_SOFTWARERESET); /* deassert */
  39. mdelay(2);
  40. /* Clear card registers */
  41. iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
  42. iowrite32(0, host->ioaddr + SD_CARDSTATUS);
  43. iowrite32(0, host->ioaddr + SD_ERRORSTATUS0);
  44. iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
  45. /* SDIO clock? */
  46. iowrite16(0x100, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
  47. /* enable LED */
  48. pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE1,
  49. SD_PCICFG_LED_ENABLE1_START);
  50. pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE2,
  51. SD_PCICFG_LED_ENABLE2_START);
  52. /* set interrupt masks */
  53. iowrite32(~(u32)(SD_CARD_RESP_END | SD_CARD_RW_END
  54. | SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0
  55. | SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE
  56. | SD_BUF_CMD_TIMEOUT),
  57. host->ioaddr + SD_INTMASKCARD);
  58. iowrite16(0x1000, host->ioaddr + SD_TRANSACTIONCTRL);
  59. }
  60. /* Set MMC clock / power.
  61. * Note: This controller uses a simple divider scheme therefore it cannot run
  62. * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
  63. * and the next slowest is 16MHz (div=2).
  64. */
  65. static void __toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  66. {
  67. struct toshsd_host *host = mmc_priv(mmc);
  68. if (ios->clock) {
  69. u16 clk;
  70. int div = 1;
  71. while (ios->clock < HCLK / div)
  72. div *= 2;
  73. clk = div >> 2;
  74. if (div == 1) { /* disable the divider */
  75. pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE,
  76. SD_PCICFG_CLKMODE_DIV_DISABLE);
  77. clk |= SD_CARDCLK_DIV_DISABLE;
  78. } else
  79. pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE, 0);
  80. clk |= SD_CARDCLK_ENABLE_CLOCK;
  81. iowrite16(clk, host->ioaddr + SD_CARDCLOCKCTRL);
  82. mdelay(10);
  83. } else
  84. iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
  85. switch (ios->power_mode) {
  86. case MMC_POWER_OFF:
  87. pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
  88. SD_PCICFG_PWR1_OFF);
  89. mdelay(1);
  90. break;
  91. case MMC_POWER_UP:
  92. break;
  93. case MMC_POWER_ON:
  94. pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
  95. SD_PCICFG_PWR1_33V);
  96. pci_write_config_byte(host->pdev, SD_PCICFG_POWER2,
  97. SD_PCICFG_PWR2_AUTO);
  98. mdelay(20);
  99. break;
  100. }
  101. switch (ios->bus_width) {
  102. case MMC_BUS_WIDTH_1:
  103. iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
  104. | SD_CARDOPT_C2_MODULE_ABSENT
  105. | SD_CARDOPT_DATA_XFR_WIDTH_1,
  106. host->ioaddr + SD_CARDOPTIONSETUP);
  107. break;
  108. case MMC_BUS_WIDTH_4:
  109. iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
  110. | SD_CARDOPT_C2_MODULE_ABSENT
  111. | SD_CARDOPT_DATA_XFR_WIDTH_4,
  112. host->ioaddr + SD_CARDOPTIONSETUP);
  113. break;
  114. }
  115. }
  116. static void toshsd_set_led(struct toshsd_host *host, unsigned char state)
  117. {
  118. iowrite16(state, host->ioaddr + SDIO_BASE + SDIO_LEDCTRL);
  119. }
  120. static void toshsd_finish_request(struct toshsd_host *host)
  121. {
  122. struct mmc_request *mrq = host->mrq;
  123. /* Write something to end the command */
  124. host->mrq = NULL;
  125. host->cmd = NULL;
  126. host->data = NULL;
  127. toshsd_set_led(host, 0);
  128. mmc_request_done(host->mmc, mrq);
  129. }
  130. static irqreturn_t toshsd_thread_irq(int irq, void *dev_id)
  131. {
  132. struct toshsd_host *host = dev_id;
  133. struct mmc_data *data = host->data;
  134. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  135. unsigned short *buf;
  136. int count;
  137. unsigned long flags;
  138. if (!data) {
  139. dev_warn(&host->pdev->dev, "Spurious Data IRQ\n");
  140. if (host->cmd) {
  141. host->cmd->error = -EIO;
  142. toshsd_finish_request(host);
  143. }
  144. return IRQ_NONE;
  145. }
  146. spin_lock_irqsave(&host->lock, flags);
  147. if (!sg_miter_next(sg_miter))
  148. goto done;
  149. buf = sg_miter->addr;
  150. /* Ensure we dont read more than one block. The chip will interrupt us
  151. * When the next block is available.
  152. */
  153. count = sg_miter->length;
  154. if (count > data->blksz)
  155. count = data->blksz;
  156. dev_dbg(&host->pdev->dev, "count: %08x, flags %08x\n", count,
  157. data->flags);
  158. /* Transfer the data */
  159. if (data->flags & MMC_DATA_READ)
  160. ioread32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
  161. else
  162. iowrite32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
  163. sg_miter->consumed = count;
  164. sg_miter_stop(sg_miter);
  165. done:
  166. spin_unlock_irqrestore(&host->lock, flags);
  167. return IRQ_HANDLED;
  168. }
  169. static void toshsd_cmd_irq(struct toshsd_host *host)
  170. {
  171. struct mmc_command *cmd = host->cmd;
  172. u8 *buf;
  173. u16 data;
  174. if (!host->cmd) {
  175. dev_warn(&host->pdev->dev, "Spurious CMD irq\n");
  176. return;
  177. }
  178. buf = (u8 *)cmd->resp;
  179. host->cmd = NULL;
  180. if (cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) {
  181. /* R2 */
  182. buf[12] = 0xff;
  183. data = ioread16(host->ioaddr + SD_RESPONSE0);
  184. buf[13] = data & 0xff;
  185. buf[14] = data >> 8;
  186. data = ioread16(host->ioaddr + SD_RESPONSE1);
  187. buf[15] = data & 0xff;
  188. buf[8] = data >> 8;
  189. data = ioread16(host->ioaddr + SD_RESPONSE2);
  190. buf[9] = data & 0xff;
  191. buf[10] = data >> 8;
  192. data = ioread16(host->ioaddr + SD_RESPONSE3);
  193. buf[11] = data & 0xff;
  194. buf[4] = data >> 8;
  195. data = ioread16(host->ioaddr + SD_RESPONSE4);
  196. buf[5] = data & 0xff;
  197. buf[6] = data >> 8;
  198. data = ioread16(host->ioaddr + SD_RESPONSE5);
  199. buf[7] = data & 0xff;
  200. buf[0] = data >> 8;
  201. data = ioread16(host->ioaddr + SD_RESPONSE6);
  202. buf[1] = data & 0xff;
  203. buf[2] = data >> 8;
  204. data = ioread16(host->ioaddr + SD_RESPONSE7);
  205. buf[3] = data & 0xff;
  206. } else if (cmd->flags & MMC_RSP_PRESENT) {
  207. /* R1, R1B, R3, R6, R7 */
  208. data = ioread16(host->ioaddr + SD_RESPONSE0);
  209. buf[0] = data & 0xff;
  210. buf[1] = data >> 8;
  211. data = ioread16(host->ioaddr + SD_RESPONSE1);
  212. buf[2] = data & 0xff;
  213. buf[3] = data >> 8;
  214. }
  215. dev_dbg(&host->pdev->dev, "Command IRQ complete %d %d %x\n",
  216. cmd->opcode, cmd->error, cmd->flags);
  217. /* If there is data to handle we will
  218. * finish the request in the mmc_data_end_irq handler.*/
  219. if (host->data)
  220. return;
  221. toshsd_finish_request(host);
  222. }
  223. static void toshsd_data_end_irq(struct toshsd_host *host)
  224. {
  225. struct mmc_data *data = host->data;
  226. host->data = NULL;
  227. if (!data) {
  228. dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
  229. return;
  230. }
  231. if (data->error == 0)
  232. data->bytes_xfered = data->blocks * data->blksz;
  233. else
  234. data->bytes_xfered = 0;
  235. dev_dbg(&host->pdev->dev, "Completed data request xfr=%d\n",
  236. data->bytes_xfered);
  237. iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
  238. toshsd_finish_request(host);
  239. }
  240. static irqreturn_t toshsd_irq(int irq, void *dev_id)
  241. {
  242. struct toshsd_host *host = dev_id;
  243. u32 int_reg, int_mask, int_status, detail;
  244. int error = 0, ret = IRQ_HANDLED;
  245. spin_lock(&host->lock);
  246. int_status = ioread32(host->ioaddr + SD_CARDSTATUS);
  247. int_mask = ioread32(host->ioaddr + SD_INTMASKCARD);
  248. int_reg = int_status & ~int_mask & ~IRQ_DONT_CARE_BITS;
  249. dev_dbg(&host->pdev->dev, "IRQ status:%x mask:%x\n",
  250. int_status, int_mask);
  251. /* nothing to do: it's not our IRQ */
  252. if (!int_reg) {
  253. ret = IRQ_NONE;
  254. goto irq_end;
  255. }
  256. if (int_reg & SD_BUF_CMD_TIMEOUT) {
  257. error = -ETIMEDOUT;
  258. dev_dbg(&host->pdev->dev, "Timeout\n");
  259. } else if (int_reg & SD_BUF_CRC_ERR) {
  260. error = -EILSEQ;
  261. dev_err(&host->pdev->dev, "BadCRC\n");
  262. } else if (int_reg & (SD_BUF_ILLEGAL_ACCESS
  263. | SD_BUF_CMD_INDEX_ERR
  264. | SD_BUF_STOP_BIT_END_ERR
  265. | SD_BUF_OVERFLOW
  266. | SD_BUF_UNDERFLOW
  267. | SD_BUF_DATA_TIMEOUT)) {
  268. dev_err(&host->pdev->dev, "Buffer status error: { %s%s%s%s%s%s}\n",
  269. int_reg & SD_BUF_ILLEGAL_ACCESS ? "ILLEGAL_ACC " : "",
  270. int_reg & SD_BUF_CMD_INDEX_ERR ? "CMD_INDEX " : "",
  271. int_reg & SD_BUF_STOP_BIT_END_ERR ? "STOPBIT_END " : "",
  272. int_reg & SD_BUF_OVERFLOW ? "OVERFLOW " : "",
  273. int_reg & SD_BUF_UNDERFLOW ? "UNDERFLOW " : "",
  274. int_reg & SD_BUF_DATA_TIMEOUT ? "DATA_TIMEOUT " : "");
  275. detail = ioread32(host->ioaddr + SD_ERRORSTATUS0);
  276. dev_err(&host->pdev->dev, "detail error status { %s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
  277. detail & SD_ERR0_RESP_CMD_ERR ? "RESP_CMD " : "",
  278. detail & SD_ERR0_RESP_NON_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
  279. detail & SD_ERR0_RESP_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
  280. detail & SD_ERR0_READ_DATA_END_BIT_ERR ? "READ_DATA_END_BIT " : "",
  281. detail & SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR ? "WRITE_CMD_END_BIT " : "",
  282. detail & SD_ERR0_RESP_NON_CMD12_CRC_ERR ? "RESP_CRC " : "",
  283. detail & SD_ERR0_RESP_CMD12_CRC_ERR ? "RESP_CRC " : "",
  284. detail & SD_ERR0_READ_DATA_CRC_ERR ? "READ_DATA_CRC " : "",
  285. detail & SD_ERR0_WRITE_CMD_CRC_ERR ? "WRITE_CMD_CRC " : "",
  286. detail & SD_ERR1_NO_CMD_RESP ? "NO_CMD_RESP " : "",
  287. detail & SD_ERR1_TIMEOUT_READ_DATA ? "READ_DATA_TIMEOUT " : "",
  288. detail & SD_ERR1_TIMEOUT_CRS_STATUS ? "CRS_STATUS_TIMEOUT " : "",
  289. detail & SD_ERR1_TIMEOUT_CRC_BUSY ? "CRC_BUSY_TIMEOUT " : "");
  290. error = -EIO;
  291. }
  292. if (error) {
  293. if (host->cmd)
  294. host->cmd->error = error;
  295. if (error == -ETIMEDOUT) {
  296. iowrite32(int_status &
  297. ~(SD_BUF_CMD_TIMEOUT | SD_CARD_RESP_END),
  298. host->ioaddr + SD_CARDSTATUS);
  299. } else {
  300. toshsd_init(host);
  301. __toshsd_set_ios(host->mmc, &host->mmc->ios);
  302. goto irq_end;
  303. }
  304. }
  305. /* Card insert/remove. The mmc controlling code is stateless. */
  306. if (int_reg & (SD_CARD_CARD_INSERTED_0 | SD_CARD_CARD_REMOVED_0)) {
  307. iowrite32(int_status &
  308. ~(SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0),
  309. host->ioaddr + SD_CARDSTATUS);
  310. if (int_reg & SD_CARD_CARD_INSERTED_0)
  311. toshsd_init(host);
  312. mmc_detect_change(host->mmc, 1);
  313. }
  314. /* Data transfer */
  315. if (int_reg & (SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE)) {
  316. iowrite32(int_status &
  317. ~(SD_BUF_WRITE_ENABLE | SD_BUF_READ_ENABLE),
  318. host->ioaddr + SD_CARDSTATUS);
  319. ret = IRQ_WAKE_THREAD;
  320. goto irq_end;
  321. }
  322. /* Command completion */
  323. if (int_reg & SD_CARD_RESP_END) {
  324. iowrite32(int_status & ~(SD_CARD_RESP_END),
  325. host->ioaddr + SD_CARDSTATUS);
  326. toshsd_cmd_irq(host);
  327. }
  328. /* Data transfer completion */
  329. if (int_reg & SD_CARD_RW_END) {
  330. iowrite32(int_status & ~(SD_CARD_RW_END),
  331. host->ioaddr + SD_CARDSTATUS);
  332. toshsd_data_end_irq(host);
  333. }
  334. irq_end:
  335. spin_unlock(&host->lock);
  336. return ret;
  337. }
  338. static void toshsd_start_cmd(struct toshsd_host *host, struct mmc_command *cmd)
  339. {
  340. struct mmc_data *data = host->data;
  341. int c = cmd->opcode;
  342. dev_dbg(&host->pdev->dev, "Command opcode: %d\n", cmd->opcode);
  343. if (cmd->opcode == MMC_STOP_TRANSMISSION) {
  344. iowrite16(SD_STOPINT_ISSUE_CMD12,
  345. host->ioaddr + SD_STOPINTERNAL);
  346. cmd->resp[0] = cmd->opcode;
  347. cmd->resp[1] = 0;
  348. cmd->resp[2] = 0;
  349. cmd->resp[3] = 0;
  350. toshsd_finish_request(host);
  351. return;
  352. }
  353. switch (mmc_resp_type(cmd)) {
  354. case MMC_RSP_NONE:
  355. c |= SD_CMD_RESP_TYPE_NONE;
  356. break;
  357. case MMC_RSP_R1:
  358. c |= SD_CMD_RESP_TYPE_EXT_R1;
  359. break;
  360. case MMC_RSP_R1B:
  361. c |= SD_CMD_RESP_TYPE_EXT_R1B;
  362. break;
  363. case MMC_RSP_R2:
  364. c |= SD_CMD_RESP_TYPE_EXT_R2;
  365. break;
  366. case MMC_RSP_R3:
  367. c |= SD_CMD_RESP_TYPE_EXT_R3;
  368. break;
  369. default:
  370. dev_err(&host->pdev->dev, "Unknown response type %d\n",
  371. mmc_resp_type(cmd));
  372. break;
  373. }
  374. host->cmd = cmd;
  375. if (cmd->opcode == MMC_APP_CMD)
  376. c |= SD_CMD_TYPE_ACMD;
  377. if (cmd->opcode == MMC_GO_IDLE_STATE)
  378. c |= (3 << 8); /* removed from ipaq-asic3.h for some reason */
  379. if (data) {
  380. c |= SD_CMD_DATA_PRESENT;
  381. if (data->blocks > 1) {
  382. iowrite16(SD_STOPINT_AUTO_ISSUE_CMD12,
  383. host->ioaddr + SD_STOPINTERNAL);
  384. c |= SD_CMD_MULTI_BLOCK;
  385. }
  386. if (data->flags & MMC_DATA_READ)
  387. c |= SD_CMD_TRANSFER_READ;
  388. /* MMC_DATA_WRITE does not require a bit to be set */
  389. }
  390. /* Send the command */
  391. iowrite32(cmd->arg, host->ioaddr + SD_ARG0);
  392. iowrite16(c, host->ioaddr + SD_CMD);
  393. }
  394. static void toshsd_start_data(struct toshsd_host *host, struct mmc_data *data)
  395. {
  396. unsigned int flags = SG_MITER_ATOMIC;
  397. dev_dbg(&host->pdev->dev, "setup data transfer: blocksize %08x nr_blocks %d, offset: %08x\n",
  398. data->blksz, data->blocks, data->sg->offset);
  399. host->data = data;
  400. if (data->flags & MMC_DATA_READ)
  401. flags |= SG_MITER_TO_SG;
  402. else
  403. flags |= SG_MITER_FROM_SG;
  404. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  405. /* Set transfer length and blocksize */
  406. iowrite16(data->blocks, host->ioaddr + SD_BLOCKCOUNT);
  407. iowrite16(data->blksz, host->ioaddr + SD_CARDXFERDATALEN);
  408. }
  409. /* Process requests from the MMC layer */
  410. static void toshsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  411. {
  412. struct toshsd_host *host = mmc_priv(mmc);
  413. unsigned long flags;
  414. /* abort if card not present */
  415. if (!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0)) {
  416. mrq->cmd->error = -ENOMEDIUM;
  417. mmc_request_done(mmc, mrq);
  418. return;
  419. }
  420. spin_lock_irqsave(&host->lock, flags);
  421. WARN_ON(host->mrq != NULL);
  422. host->mrq = mrq;
  423. if (mrq->data)
  424. toshsd_start_data(host, mrq->data);
  425. toshsd_set_led(host, 1);
  426. toshsd_start_cmd(host, mrq->cmd);
  427. spin_unlock_irqrestore(&host->lock, flags);
  428. }
  429. static void toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  430. {
  431. struct toshsd_host *host = mmc_priv(mmc);
  432. unsigned long flags;
  433. spin_lock_irqsave(&host->lock, flags);
  434. __toshsd_set_ios(mmc, ios);
  435. spin_unlock_irqrestore(&host->lock, flags);
  436. }
  437. static int toshsd_get_ro(struct mmc_host *mmc)
  438. {
  439. struct toshsd_host *host = mmc_priv(mmc);
  440. /* active low */
  441. return !(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_WRITE_PROTECT);
  442. }
  443. static int toshsd_get_cd(struct mmc_host *mmc)
  444. {
  445. struct toshsd_host *host = mmc_priv(mmc);
  446. return !!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0);
  447. }
  448. static const struct mmc_host_ops toshsd_ops = {
  449. .request = toshsd_request,
  450. .set_ios = toshsd_set_ios,
  451. .get_ro = toshsd_get_ro,
  452. .get_cd = toshsd_get_cd,
  453. };
  454. static void toshsd_powerdown(struct toshsd_host *host)
  455. {
  456. /* mask all interrupts */
  457. iowrite32(0xffffffff, host->ioaddr + SD_INTMASKCARD);
  458. /* disable card clock */
  459. iowrite16(0x000, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
  460. iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
  461. /* power down card */
  462. pci_write_config_byte(host->pdev, SD_PCICFG_POWER1, SD_PCICFG_PWR1_OFF);
  463. /* disable clock */
  464. pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP, 0);
  465. }
  466. #ifdef CONFIG_PM_SLEEP
  467. static int toshsd_pm_suspend(struct device *dev)
  468. {
  469. struct pci_dev *pdev = to_pci_dev(dev);
  470. struct toshsd_host *host = pci_get_drvdata(pdev);
  471. toshsd_powerdown(host);
  472. pci_save_state(pdev);
  473. pci_enable_wake(pdev, PCI_D3hot, 0);
  474. pci_disable_device(pdev);
  475. pci_set_power_state(pdev, PCI_D3hot);
  476. return 0;
  477. }
  478. static int toshsd_pm_resume(struct device *dev)
  479. {
  480. struct pci_dev *pdev = to_pci_dev(dev);
  481. struct toshsd_host *host = pci_get_drvdata(pdev);
  482. int ret;
  483. pci_set_power_state(pdev, PCI_D0);
  484. pci_restore_state(pdev);
  485. ret = pci_enable_device(pdev);
  486. if (ret)
  487. return ret;
  488. toshsd_init(host);
  489. return 0;
  490. }
  491. #endif /* CONFIG_PM_SLEEP */
  492. static int toshsd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  493. {
  494. int ret;
  495. struct toshsd_host *host;
  496. struct mmc_host *mmc;
  497. resource_size_t base;
  498. ret = pci_enable_device(pdev);
  499. if (ret)
  500. return ret;
  501. mmc = mmc_alloc_host(sizeof(struct toshsd_host), &pdev->dev);
  502. if (!mmc) {
  503. ret = -ENOMEM;
  504. goto err;
  505. }
  506. host = mmc_priv(mmc);
  507. host->mmc = mmc;
  508. host->pdev = pdev;
  509. pci_set_drvdata(pdev, host);
  510. ret = pci_request_regions(pdev, DRIVER_NAME);
  511. if (ret)
  512. goto free;
  513. host->ioaddr = pci_iomap(pdev, 0, 0);
  514. if (!host->ioaddr) {
  515. ret = -ENOMEM;
  516. goto release;
  517. }
  518. /* Set MMC host parameters */
  519. mmc->ops = &toshsd_ops;
  520. mmc->caps = MMC_CAP_4_BIT_DATA;
  521. mmc->ocr_avail = MMC_VDD_32_33;
  522. mmc->f_min = HCLK / 512;
  523. mmc->f_max = HCLK;
  524. spin_lock_init(&host->lock);
  525. toshsd_init(host);
  526. ret = request_threaded_irq(pdev->irq, toshsd_irq, toshsd_thread_irq,
  527. IRQF_SHARED, DRIVER_NAME, host);
  528. if (ret)
  529. goto unmap;
  530. mmc_add_host(mmc);
  531. base = pci_resource_start(pdev, 0);
  532. dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq);
  533. pm_suspend_ignore_children(&pdev->dev, 1);
  534. return 0;
  535. unmap:
  536. pci_iounmap(pdev, host->ioaddr);
  537. release:
  538. pci_release_regions(pdev);
  539. free:
  540. mmc_free_host(mmc);
  541. pci_set_drvdata(pdev, NULL);
  542. err:
  543. pci_disable_device(pdev);
  544. return ret;
  545. }
  546. static void toshsd_remove(struct pci_dev *pdev)
  547. {
  548. struct toshsd_host *host = pci_get_drvdata(pdev);
  549. mmc_remove_host(host->mmc);
  550. toshsd_powerdown(host);
  551. free_irq(pdev->irq, host);
  552. pci_iounmap(pdev, host->ioaddr);
  553. pci_release_regions(pdev);
  554. mmc_free_host(host->mmc);
  555. pci_set_drvdata(pdev, NULL);
  556. pci_disable_device(pdev);
  557. }
  558. static const struct dev_pm_ops toshsd_pm_ops = {
  559. SET_SYSTEM_SLEEP_PM_OPS(toshsd_pm_suspend, toshsd_pm_resume)
  560. };
  561. static struct pci_driver toshsd_driver = {
  562. .name = DRIVER_NAME,
  563. .id_table = pci_ids,
  564. .probe = toshsd_probe,
  565. .remove = toshsd_remove,
  566. .driver.pm = &toshsd_pm_ops,
  567. };
  568. module_pci_driver(toshsd_driver);
  569. MODULE_AUTHOR("Ondrej Zary, Richard Betts");
  570. MODULE_DESCRIPTION("Toshiba PCI Secure Digital Host Controller Interface driver");
  571. MODULE_LICENSE("GPL");