sunxi-mmc.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for sunxi SD/MMC host controllers
  4. * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
  5. * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
  6. * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
  7. * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
  8. * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
  9. * (C) Copyright 2017 Sootech SA
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk/sunxi-ng.h>
  13. #include <linux/delay.h>
  14. #include <linux/device.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/err.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/kernel.h>
  20. #include <linux/mmc/card.h>
  21. #include <linux/mmc/core.h>
  22. #include <linux/mmc/host.h>
  23. #include <linux/mmc/mmc.h>
  24. #include <linux/mmc/sd.h>
  25. #include <linux/mmc/sdio.h>
  26. #include <linux/mmc/slot-gpio.h>
  27. #include <linux/module.h>
  28. #include <linux/of_address.h>
  29. #include <linux/of_platform.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/pm_runtime.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/reset.h>
  34. #include <linux/scatterlist.h>
  35. #include <linux/slab.h>
  36. #include <linux/spinlock.h>
  37. /* register offset definitions */
  38. #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
  39. #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
  40. #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
  41. #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
  42. #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
  43. #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
  44. #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
  45. #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
  46. #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
  47. #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
  48. #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
  49. #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
  50. #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
  51. #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
  52. #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
  53. #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
  54. #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
  55. #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
  56. #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
  57. #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
  58. #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
  59. #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
  60. #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
  61. #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
  62. #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
  63. #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
  64. #define SDXC_REG_CHDA (0x90)
  65. #define SDXC_REG_CBDA (0x94)
  66. /* New registers introduced in A64 */
  67. #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
  68. #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
  69. #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
  70. #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
  71. #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
  72. #define mmc_readl(host, reg) \
  73. readl((host)->reg_base + SDXC_##reg)
  74. #define mmc_writel(host, reg, value) \
  75. writel((value), (host)->reg_base + SDXC_##reg)
  76. /* global control register bits */
  77. #define SDXC_SOFT_RESET BIT(0)
  78. #define SDXC_FIFO_RESET BIT(1)
  79. #define SDXC_DMA_RESET BIT(2)
  80. #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
  81. #define SDXC_DMA_ENABLE_BIT BIT(5)
  82. #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
  83. #define SDXC_POSEDGE_LATCH_DATA BIT(9)
  84. #define SDXC_DDR_MODE BIT(10)
  85. #define SDXC_MEMORY_ACCESS_DONE BIT(29)
  86. #define SDXC_ACCESS_DONE_DIRECT BIT(30)
  87. #define SDXC_ACCESS_BY_AHB BIT(31)
  88. #define SDXC_ACCESS_BY_DMA (0 << 31)
  89. #define SDXC_HARDWARE_RESET \
  90. (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
  91. /* clock control bits */
  92. #define SDXC_MASK_DATA0 BIT(31)
  93. #define SDXC_CARD_CLOCK_ON BIT(16)
  94. #define SDXC_LOW_POWER_ON BIT(17)
  95. /* bus width */
  96. #define SDXC_WIDTH1 0
  97. #define SDXC_WIDTH4 1
  98. #define SDXC_WIDTH8 2
  99. /* smc command bits */
  100. #define SDXC_RESP_EXPIRE BIT(6)
  101. #define SDXC_LONG_RESPONSE BIT(7)
  102. #define SDXC_CHECK_RESPONSE_CRC BIT(8)
  103. #define SDXC_DATA_EXPIRE BIT(9)
  104. #define SDXC_WRITE BIT(10)
  105. #define SDXC_SEQUENCE_MODE BIT(11)
  106. #define SDXC_SEND_AUTO_STOP BIT(12)
  107. #define SDXC_WAIT_PRE_OVER BIT(13)
  108. #define SDXC_STOP_ABORT_CMD BIT(14)
  109. #define SDXC_SEND_INIT_SEQUENCE BIT(15)
  110. #define SDXC_UPCLK_ONLY BIT(21)
  111. #define SDXC_READ_CEATA_DEV BIT(22)
  112. #define SDXC_CCS_EXPIRE BIT(23)
  113. #define SDXC_ENABLE_BIT_BOOT BIT(24)
  114. #define SDXC_ALT_BOOT_OPTIONS BIT(25)
  115. #define SDXC_BOOT_ACK_EXPIRE BIT(26)
  116. #define SDXC_BOOT_ABORT BIT(27)
  117. #define SDXC_VOLTAGE_SWITCH BIT(28)
  118. #define SDXC_USE_HOLD_REGISTER BIT(29)
  119. #define SDXC_START BIT(31)
  120. /* interrupt bits */
  121. #define SDXC_RESP_ERROR BIT(1)
  122. #define SDXC_COMMAND_DONE BIT(2)
  123. #define SDXC_DATA_OVER BIT(3)
  124. #define SDXC_TX_DATA_REQUEST BIT(4)
  125. #define SDXC_RX_DATA_REQUEST BIT(5)
  126. #define SDXC_RESP_CRC_ERROR BIT(6)
  127. #define SDXC_DATA_CRC_ERROR BIT(7)
  128. #define SDXC_RESP_TIMEOUT BIT(8)
  129. #define SDXC_DATA_TIMEOUT BIT(9)
  130. #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
  131. #define SDXC_FIFO_RUN_ERROR BIT(11)
  132. #define SDXC_HARD_WARE_LOCKED BIT(12)
  133. #define SDXC_START_BIT_ERROR BIT(13)
  134. #define SDXC_AUTO_COMMAND_DONE BIT(14)
  135. #define SDXC_END_BIT_ERROR BIT(15)
  136. #define SDXC_SDIO_INTERRUPT BIT(16)
  137. #define SDXC_CARD_INSERT BIT(30)
  138. #define SDXC_CARD_REMOVE BIT(31)
  139. #define SDXC_INTERRUPT_ERROR_BIT \
  140. (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
  141. SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
  142. SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
  143. #define SDXC_INTERRUPT_DONE_BIT \
  144. (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
  145. SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
  146. /* status */
  147. #define SDXC_RXWL_FLAG BIT(0)
  148. #define SDXC_TXWL_FLAG BIT(1)
  149. #define SDXC_FIFO_EMPTY BIT(2)
  150. #define SDXC_FIFO_FULL BIT(3)
  151. #define SDXC_CARD_PRESENT BIT(8)
  152. #define SDXC_CARD_DATA_BUSY BIT(9)
  153. #define SDXC_DATA_FSM_BUSY BIT(10)
  154. #define SDXC_DMA_REQUEST BIT(31)
  155. #define SDXC_FIFO_SIZE 16
  156. /* Function select */
  157. #define SDXC_CEATA_ON (0xceaa << 16)
  158. #define SDXC_SEND_IRQ_RESPONSE BIT(0)
  159. #define SDXC_SDIO_READ_WAIT BIT(1)
  160. #define SDXC_ABORT_READ_DATA BIT(2)
  161. #define SDXC_SEND_CCSD BIT(8)
  162. #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
  163. #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
  164. /* IDMA controller bus mod bit field */
  165. #define SDXC_IDMAC_SOFT_RESET BIT(0)
  166. #define SDXC_IDMAC_FIX_BURST BIT(1)
  167. #define SDXC_IDMAC_IDMA_ON BIT(7)
  168. #define SDXC_IDMAC_REFETCH_DES BIT(31)
  169. /* IDMA status bit field */
  170. #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
  171. #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
  172. #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
  173. #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
  174. #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
  175. #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
  176. #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
  177. #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
  178. #define SDXC_IDMAC_IDLE (0 << 13)
  179. #define SDXC_IDMAC_SUSPEND (1 << 13)
  180. #define SDXC_IDMAC_DESC_READ (2 << 13)
  181. #define SDXC_IDMAC_DESC_CHECK (3 << 13)
  182. #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
  183. #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
  184. #define SDXC_IDMAC_READ (6 << 13)
  185. #define SDXC_IDMAC_WRITE (7 << 13)
  186. #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
  187. /*
  188. * If the idma-des-size-bits of property is ie 13, bufsize bits are:
  189. * Bits 0-12: buf1 size
  190. * Bits 13-25: buf2 size
  191. * Bits 26-31: not used
  192. * Since we only ever set buf1 size, we can simply store it directly.
  193. */
  194. #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
  195. #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
  196. #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
  197. #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
  198. #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
  199. #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
  200. #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
  201. #define SDXC_CLK_400K 0
  202. #define SDXC_CLK_25M 1
  203. #define SDXC_CLK_50M 2
  204. #define SDXC_CLK_50M_DDR 3
  205. #define SDXC_CLK_50M_DDR_8BIT 4
  206. #define SDXC_2X_TIMING_MODE BIT(31)
  207. #define SDXC_CAL_START BIT(15)
  208. #define SDXC_CAL_DONE BIT(14)
  209. #define SDXC_CAL_DL_SHIFT 8
  210. #define SDXC_CAL_DL_SW_EN BIT(7)
  211. #define SDXC_CAL_DL_SW_SHIFT 0
  212. #define SDXC_CAL_DL_MASK 0x3f
  213. #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
  214. struct sunxi_mmc_clk_delay {
  215. u32 output;
  216. u32 sample;
  217. };
  218. struct sunxi_idma_des {
  219. __le32 config;
  220. __le32 buf_size;
  221. __le32 buf_addr_ptr1;
  222. __le32 buf_addr_ptr2;
  223. };
  224. struct sunxi_mmc_cfg {
  225. u32 idma_des_size_bits;
  226. const struct sunxi_mmc_clk_delay *clk_delays;
  227. /* does the IP block support autocalibration? */
  228. bool can_calibrate;
  229. /* Does DATA0 needs to be masked while the clock is updated */
  230. bool mask_data0;
  231. /*
  232. * hardware only supports new timing mode, either due to lack of
  233. * a mode switch in the clock controller, or the mmc controller
  234. * is permanently configured in the new timing mode, without the
  235. * NTSR mode switch.
  236. */
  237. bool needs_new_timings;
  238. /* clock hardware can switch between old and new timing modes */
  239. bool ccu_has_timings_switch;
  240. };
  241. struct sunxi_mmc_host {
  242. struct device *dev;
  243. struct mmc_host *mmc;
  244. struct reset_control *reset;
  245. const struct sunxi_mmc_cfg *cfg;
  246. /* IO mapping base */
  247. void __iomem *reg_base;
  248. /* clock management */
  249. struct clk *clk_ahb;
  250. struct clk *clk_mmc;
  251. struct clk *clk_sample;
  252. struct clk *clk_output;
  253. /* irq */
  254. spinlock_t lock;
  255. int irq;
  256. u32 int_sum;
  257. u32 sdio_imask;
  258. /* dma */
  259. dma_addr_t sg_dma;
  260. void *sg_cpu;
  261. bool wait_dma;
  262. struct mmc_request *mrq;
  263. struct mmc_request *manual_stop_mrq;
  264. int ferror;
  265. /* vqmmc */
  266. bool vqmmc_enabled;
  267. /* timings */
  268. bool use_new_timings;
  269. };
  270. static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
  271. {
  272. unsigned long expire = jiffies + msecs_to_jiffies(250);
  273. u32 rval;
  274. mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
  275. do {
  276. rval = mmc_readl(host, REG_GCTRL);
  277. } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
  278. if (rval & SDXC_HARDWARE_RESET) {
  279. dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
  280. return -EIO;
  281. }
  282. return 0;
  283. }
  284. static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
  285. {
  286. u32 rval;
  287. if (sunxi_mmc_reset_host(host))
  288. return -EIO;
  289. /*
  290. * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
  291. *
  292. * TODO: sun9i has a larger FIFO and supports higher trigger values
  293. */
  294. mmc_writel(host, REG_FTRGL, 0x20070008);
  295. /* Maximum timeout value */
  296. mmc_writel(host, REG_TMOUT, 0xffffffff);
  297. /* Unmask SDIO interrupt if needed */
  298. mmc_writel(host, REG_IMASK, host->sdio_imask);
  299. /* Clear all pending interrupts */
  300. mmc_writel(host, REG_RINTR, 0xffffffff);
  301. /* Debug register? undocumented */
  302. mmc_writel(host, REG_DBGC, 0xdeb);
  303. /* Enable CEATA support */
  304. mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
  305. /* Set DMA descriptor list base address */
  306. mmc_writel(host, REG_DLBA, host->sg_dma);
  307. rval = mmc_readl(host, REG_GCTRL);
  308. rval |= SDXC_INTERRUPT_ENABLE_BIT;
  309. /* Undocumented, but found in Allwinner code */
  310. rval &= ~SDXC_ACCESS_DONE_DIRECT;
  311. mmc_writel(host, REG_GCTRL, rval);
  312. return 0;
  313. }
  314. static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
  315. struct mmc_data *data)
  316. {
  317. struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
  318. dma_addr_t next_desc = host->sg_dma;
  319. int i, max_len = (1 << host->cfg->idma_des_size_bits);
  320. for (i = 0; i < data->sg_len; i++) {
  321. pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
  322. SDXC_IDMAC_DES0_OWN |
  323. SDXC_IDMAC_DES0_DIC);
  324. if (data->sg[i].length == max_len)
  325. pdes[i].buf_size = 0; /* 0 == max_len */
  326. else
  327. pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
  328. next_desc += sizeof(struct sunxi_idma_des);
  329. pdes[i].buf_addr_ptr1 =
  330. cpu_to_le32(sg_dma_address(&data->sg[i]));
  331. pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
  332. }
  333. pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
  334. pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
  335. SDXC_IDMAC_DES0_ER);
  336. pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
  337. pdes[i - 1].buf_addr_ptr2 = 0;
  338. /*
  339. * Avoid the io-store starting the idmac hitting io-mem before the
  340. * descriptors hit the main-mem.
  341. */
  342. wmb();
  343. }
  344. static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
  345. struct mmc_data *data)
  346. {
  347. u32 i, dma_len;
  348. struct scatterlist *sg;
  349. dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  350. mmc_get_dma_dir(data));
  351. if (dma_len == 0) {
  352. dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
  353. return -ENOMEM;
  354. }
  355. for_each_sg(data->sg, sg, data->sg_len, i) {
  356. if (sg->offset & 3 || sg->length & 3) {
  357. dev_err(mmc_dev(host->mmc),
  358. "unaligned scatterlist: os %x length %d\n",
  359. sg->offset, sg->length);
  360. return -EINVAL;
  361. }
  362. }
  363. return 0;
  364. }
  365. static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
  366. struct mmc_data *data)
  367. {
  368. u32 rval;
  369. sunxi_mmc_init_idma_des(host, data);
  370. rval = mmc_readl(host, REG_GCTRL);
  371. rval |= SDXC_DMA_ENABLE_BIT;
  372. mmc_writel(host, REG_GCTRL, rval);
  373. rval |= SDXC_DMA_RESET;
  374. mmc_writel(host, REG_GCTRL, rval);
  375. mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
  376. if (!(data->flags & MMC_DATA_WRITE))
  377. mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
  378. mmc_writel(host, REG_DMAC,
  379. SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
  380. }
  381. static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
  382. struct mmc_request *req)
  383. {
  384. u32 arg, cmd_val, ri;
  385. unsigned long expire = jiffies + msecs_to_jiffies(1000);
  386. cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
  387. SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
  388. if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
  389. cmd_val |= SD_IO_RW_DIRECT;
  390. arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
  391. ((req->cmd->arg >> 28) & 0x7);
  392. } else {
  393. cmd_val |= MMC_STOP_TRANSMISSION;
  394. arg = 0;
  395. }
  396. mmc_writel(host, REG_CARG, arg);
  397. mmc_writel(host, REG_CMDR, cmd_val);
  398. do {
  399. ri = mmc_readl(host, REG_RINTR);
  400. } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
  401. time_before(jiffies, expire));
  402. if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
  403. dev_err(mmc_dev(host->mmc), "send stop command failed\n");
  404. if (req->stop)
  405. req->stop->resp[0] = -ETIMEDOUT;
  406. } else {
  407. if (req->stop)
  408. req->stop->resp[0] = mmc_readl(host, REG_RESP0);
  409. }
  410. mmc_writel(host, REG_RINTR, 0xffff);
  411. }
  412. static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
  413. {
  414. struct mmc_command *cmd = host->mrq->cmd;
  415. struct mmc_data *data = host->mrq->data;
  416. /* For some cmds timeout is normal with sd/mmc cards */
  417. if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
  418. SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
  419. cmd->opcode == SD_IO_RW_DIRECT))
  420. return;
  421. dev_dbg(mmc_dev(host->mmc),
  422. "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
  423. host->mmc->index, cmd->opcode,
  424. data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
  425. host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
  426. host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
  427. host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
  428. host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
  429. host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
  430. host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
  431. host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
  432. host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
  433. host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
  434. );
  435. }
  436. /* Called in interrupt context! */
  437. static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
  438. {
  439. struct mmc_request *mrq = host->mrq;
  440. struct mmc_data *data = mrq->data;
  441. u32 rval;
  442. mmc_writel(host, REG_IMASK, host->sdio_imask);
  443. mmc_writel(host, REG_IDIE, 0);
  444. if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
  445. sunxi_mmc_dump_errinfo(host);
  446. mrq->cmd->error = -ETIMEDOUT;
  447. if (data) {
  448. data->error = -ETIMEDOUT;
  449. host->manual_stop_mrq = mrq;
  450. }
  451. if (mrq->stop)
  452. mrq->stop->error = -ETIMEDOUT;
  453. } else {
  454. if (mrq->cmd->flags & MMC_RSP_136) {
  455. mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
  456. mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
  457. mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
  458. mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
  459. } else {
  460. mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
  461. }
  462. if (data)
  463. data->bytes_xfered = data->blocks * data->blksz;
  464. }
  465. if (data) {
  466. mmc_writel(host, REG_IDST, 0x337);
  467. mmc_writel(host, REG_DMAC, 0);
  468. rval = mmc_readl(host, REG_GCTRL);
  469. rval |= SDXC_DMA_RESET;
  470. mmc_writel(host, REG_GCTRL, rval);
  471. rval &= ~SDXC_DMA_ENABLE_BIT;
  472. mmc_writel(host, REG_GCTRL, rval);
  473. rval |= SDXC_FIFO_RESET;
  474. mmc_writel(host, REG_GCTRL, rval);
  475. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  476. mmc_get_dma_dir(data));
  477. }
  478. mmc_writel(host, REG_RINTR, 0xffff);
  479. host->mrq = NULL;
  480. host->int_sum = 0;
  481. host->wait_dma = false;
  482. return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
  483. }
  484. static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
  485. {
  486. struct sunxi_mmc_host *host = dev_id;
  487. struct mmc_request *mrq;
  488. u32 msk_int, idma_int;
  489. bool finalize = false;
  490. bool sdio_int = false;
  491. irqreturn_t ret = IRQ_HANDLED;
  492. spin_lock(&host->lock);
  493. idma_int = mmc_readl(host, REG_IDST);
  494. msk_int = mmc_readl(host, REG_MISTA);
  495. dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
  496. host->mrq, msk_int, idma_int);
  497. mrq = host->mrq;
  498. if (mrq) {
  499. if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
  500. host->wait_dma = false;
  501. host->int_sum |= msk_int;
  502. /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
  503. if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
  504. !(host->int_sum & SDXC_COMMAND_DONE))
  505. mmc_writel(host, REG_IMASK,
  506. host->sdio_imask | SDXC_COMMAND_DONE);
  507. /* Don't wait for dma on error */
  508. else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
  509. finalize = true;
  510. else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
  511. !host->wait_dma)
  512. finalize = true;
  513. }
  514. if (msk_int & SDXC_SDIO_INTERRUPT)
  515. sdio_int = true;
  516. mmc_writel(host, REG_RINTR, msk_int);
  517. mmc_writel(host, REG_IDST, idma_int);
  518. if (finalize)
  519. ret = sunxi_mmc_finalize_request(host);
  520. spin_unlock(&host->lock);
  521. if (finalize && ret == IRQ_HANDLED)
  522. mmc_request_done(host->mmc, mrq);
  523. if (sdio_int)
  524. mmc_signal_sdio_irq(host->mmc);
  525. return ret;
  526. }
  527. static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
  528. {
  529. struct sunxi_mmc_host *host = dev_id;
  530. struct mmc_request *mrq;
  531. unsigned long iflags;
  532. spin_lock_irqsave(&host->lock, iflags);
  533. mrq = host->manual_stop_mrq;
  534. spin_unlock_irqrestore(&host->lock, iflags);
  535. if (!mrq) {
  536. dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
  537. return IRQ_HANDLED;
  538. }
  539. dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
  540. /*
  541. * We will never have more than one outstanding request,
  542. * and we do not complete the request until after
  543. * we've cleared host->manual_stop_mrq so we do not need to
  544. * spin lock this function.
  545. * Additionally we have wait states within this function
  546. * so having it in a lock is a very bad idea.
  547. */
  548. sunxi_mmc_send_manual_stop(host, mrq);
  549. spin_lock_irqsave(&host->lock, iflags);
  550. host->manual_stop_mrq = NULL;
  551. spin_unlock_irqrestore(&host->lock, iflags);
  552. mmc_request_done(host->mmc, mrq);
  553. return IRQ_HANDLED;
  554. }
  555. static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
  556. {
  557. unsigned long expire = jiffies + msecs_to_jiffies(750);
  558. u32 rval;
  559. dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
  560. oclk_en ? "en" : "dis");
  561. rval = mmc_readl(host, REG_CLKCR);
  562. rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
  563. if (oclk_en)
  564. rval |= SDXC_CARD_CLOCK_ON;
  565. if (host->cfg->mask_data0)
  566. rval |= SDXC_MASK_DATA0;
  567. mmc_writel(host, REG_CLKCR, rval);
  568. rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
  569. mmc_writel(host, REG_CMDR, rval);
  570. do {
  571. rval = mmc_readl(host, REG_CMDR);
  572. } while (time_before(jiffies, expire) && (rval & SDXC_START));
  573. /* clear irq status bits set by the command */
  574. mmc_writel(host, REG_RINTR,
  575. mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
  576. if (rval & SDXC_START) {
  577. dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
  578. return -EIO;
  579. }
  580. if (host->cfg->mask_data0) {
  581. rval = mmc_readl(host, REG_CLKCR);
  582. mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
  583. }
  584. return 0;
  585. }
  586. static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
  587. {
  588. if (!host->cfg->can_calibrate)
  589. return 0;
  590. /*
  591. * FIXME:
  592. * This is not clear how the calibration is supposed to work
  593. * yet. The best rate have been obtained by simply setting the
  594. * delay to 0, as Allwinner does in its BSP.
  595. *
  596. * The only mode that doesn't have such a delay is HS400, that
  597. * is in itself a TODO.
  598. */
  599. writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
  600. return 0;
  601. }
  602. static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
  603. struct mmc_ios *ios, u32 rate)
  604. {
  605. int index;
  606. /* clk controller delays not used under new timings mode */
  607. if (host->use_new_timings)
  608. return 0;
  609. /* some old controllers don't support delays */
  610. if (!host->cfg->clk_delays)
  611. return 0;
  612. /* determine delays */
  613. if (rate <= 400000) {
  614. index = SDXC_CLK_400K;
  615. } else if (rate <= 25000000) {
  616. index = SDXC_CLK_25M;
  617. } else if (rate <= 52000000) {
  618. if (ios->timing != MMC_TIMING_UHS_DDR50 &&
  619. ios->timing != MMC_TIMING_MMC_DDR52) {
  620. index = SDXC_CLK_50M;
  621. } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
  622. index = SDXC_CLK_50M_DDR_8BIT;
  623. } else {
  624. index = SDXC_CLK_50M_DDR;
  625. }
  626. } else {
  627. dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
  628. return -EINVAL;
  629. }
  630. clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
  631. clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
  632. return 0;
  633. }
  634. static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
  635. struct mmc_ios *ios)
  636. {
  637. struct mmc_host *mmc = host->mmc;
  638. long rate;
  639. u32 rval, clock = ios->clock, div = 1;
  640. int ret;
  641. ret = sunxi_mmc_oclk_onoff(host, 0);
  642. if (ret)
  643. return ret;
  644. /* Our clock is gated now */
  645. mmc->actual_clock = 0;
  646. if (!ios->clock)
  647. return 0;
  648. /*
  649. * Under the old timing mode, 8 bit DDR requires the module
  650. * clock to be double the card clock. Under the new timing
  651. * mode, all DDR modes require a doubled module clock.
  652. *
  653. * We currently only support the standard MMC DDR52 mode.
  654. * This block should be updated once support for other DDR
  655. * modes is added.
  656. */
  657. if (ios->timing == MMC_TIMING_MMC_DDR52 &&
  658. (host->use_new_timings ||
  659. ios->bus_width == MMC_BUS_WIDTH_8)) {
  660. div = 2;
  661. clock <<= 1;
  662. }
  663. if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
  664. ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
  665. if (ret) {
  666. dev_err(mmc_dev(mmc),
  667. "error setting new timing mode\n");
  668. return ret;
  669. }
  670. }
  671. rate = clk_round_rate(host->clk_mmc, clock);
  672. if (rate < 0) {
  673. dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
  674. clock, rate);
  675. return rate;
  676. }
  677. dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
  678. clock, rate);
  679. /* setting clock rate */
  680. ret = clk_set_rate(host->clk_mmc, rate);
  681. if (ret) {
  682. dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
  683. rate, ret);
  684. return ret;
  685. }
  686. /* set internal divider */
  687. rval = mmc_readl(host, REG_CLKCR);
  688. rval &= ~0xff;
  689. rval |= div - 1;
  690. mmc_writel(host, REG_CLKCR, rval);
  691. /* update card clock rate to account for internal divider */
  692. rate /= div;
  693. /*
  694. * Configure the controller to use the new timing mode if needed.
  695. * On controllers that only support the new timing mode, such as
  696. * the eMMC controller on the A64, this register does not exist,
  697. * and any writes to it are ignored.
  698. */
  699. if (host->use_new_timings) {
  700. /* Don't touch the delay bits */
  701. rval = mmc_readl(host, REG_SD_NTSR);
  702. rval |= SDXC_2X_TIMING_MODE;
  703. mmc_writel(host, REG_SD_NTSR, rval);
  704. }
  705. /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
  706. ret = sunxi_mmc_clk_set_phase(host, ios, rate);
  707. if (ret)
  708. return ret;
  709. ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
  710. if (ret)
  711. return ret;
  712. /*
  713. * FIXME:
  714. *
  715. * In HS400 we'll also need to calibrate the data strobe
  716. * signal. This should only happen on the MMC2 controller (at
  717. * least on the A64).
  718. */
  719. ret = sunxi_mmc_oclk_onoff(host, 1);
  720. if (ret)
  721. return ret;
  722. /* And we just enabled our clock back */
  723. mmc->actual_clock = rate;
  724. return 0;
  725. }
  726. static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
  727. unsigned char width)
  728. {
  729. switch (width) {
  730. case MMC_BUS_WIDTH_1:
  731. mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
  732. break;
  733. case MMC_BUS_WIDTH_4:
  734. mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
  735. break;
  736. case MMC_BUS_WIDTH_8:
  737. mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
  738. break;
  739. }
  740. }
  741. static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
  742. {
  743. u32 rval;
  744. /* set ddr mode */
  745. rval = mmc_readl(host, REG_GCTRL);
  746. if (ios->timing == MMC_TIMING_UHS_DDR50 ||
  747. ios->timing == MMC_TIMING_MMC_DDR52)
  748. rval |= SDXC_DDR_MODE;
  749. else
  750. rval &= ~SDXC_DDR_MODE;
  751. mmc_writel(host, REG_GCTRL, rval);
  752. host->ferror = sunxi_mmc_clk_set_rate(host, ios);
  753. /* Android code had a usleep_range(50000, 55000); here */
  754. }
  755. static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
  756. struct mmc_ios *ios)
  757. {
  758. struct mmc_host *mmc = host->mmc;
  759. switch (ios->power_mode) {
  760. case MMC_POWER_UP:
  761. dev_dbg(mmc_dev(mmc), "Powering card up\n");
  762. if (!IS_ERR(mmc->supply.vmmc)) {
  763. host->ferror = mmc_regulator_set_ocr(mmc,
  764. mmc->supply.vmmc,
  765. ios->vdd);
  766. if (host->ferror)
  767. return;
  768. }
  769. if (!IS_ERR(mmc->supply.vqmmc)) {
  770. host->ferror = regulator_enable(mmc->supply.vqmmc);
  771. if (host->ferror) {
  772. dev_err(mmc_dev(mmc),
  773. "failed to enable vqmmc\n");
  774. return;
  775. }
  776. host->vqmmc_enabled = true;
  777. }
  778. break;
  779. case MMC_POWER_OFF:
  780. dev_dbg(mmc_dev(mmc), "Powering card off\n");
  781. if (!IS_ERR(mmc->supply.vmmc))
  782. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  783. if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
  784. regulator_disable(mmc->supply.vqmmc);
  785. host->vqmmc_enabled = false;
  786. break;
  787. default:
  788. dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
  789. break;
  790. }
  791. }
  792. static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  793. {
  794. struct sunxi_mmc_host *host = mmc_priv(mmc);
  795. sunxi_mmc_card_power(host, ios);
  796. sunxi_mmc_set_bus_width(host, ios->bus_width);
  797. sunxi_mmc_set_clk(host, ios);
  798. }
  799. static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
  800. {
  801. int ret;
  802. /* vqmmc regulator is available */
  803. if (!IS_ERR(mmc->supply.vqmmc)) {
  804. ret = mmc_regulator_set_vqmmc(mmc, ios);
  805. return ret < 0 ? ret : 0;
  806. }
  807. /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
  808. if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  809. return 0;
  810. return -EINVAL;
  811. }
  812. static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  813. {
  814. struct sunxi_mmc_host *host = mmc_priv(mmc);
  815. unsigned long flags;
  816. u32 imask;
  817. if (enable)
  818. pm_runtime_get_noresume(host->dev);
  819. spin_lock_irqsave(&host->lock, flags);
  820. imask = mmc_readl(host, REG_IMASK);
  821. if (enable) {
  822. host->sdio_imask = SDXC_SDIO_INTERRUPT;
  823. imask |= SDXC_SDIO_INTERRUPT;
  824. } else {
  825. host->sdio_imask = 0;
  826. imask &= ~SDXC_SDIO_INTERRUPT;
  827. }
  828. mmc_writel(host, REG_IMASK, imask);
  829. spin_unlock_irqrestore(&host->lock, flags);
  830. if (!enable)
  831. pm_runtime_put_noidle(host->mmc->parent);
  832. }
  833. static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
  834. {
  835. struct sunxi_mmc_host *host = mmc_priv(mmc);
  836. mmc_writel(host, REG_HWRST, 0);
  837. udelay(10);
  838. mmc_writel(host, REG_HWRST, 1);
  839. udelay(300);
  840. }
  841. static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  842. {
  843. struct sunxi_mmc_host *host = mmc_priv(mmc);
  844. struct mmc_command *cmd = mrq->cmd;
  845. struct mmc_data *data = mrq->data;
  846. unsigned long iflags;
  847. u32 imask = SDXC_INTERRUPT_ERROR_BIT;
  848. u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
  849. bool wait_dma = host->wait_dma;
  850. int ret;
  851. /* Check for set_ios errors (should never happen) */
  852. if (host->ferror) {
  853. mrq->cmd->error = host->ferror;
  854. mmc_request_done(mmc, mrq);
  855. return;
  856. }
  857. if (data) {
  858. ret = sunxi_mmc_map_dma(host, data);
  859. if (ret < 0) {
  860. dev_err(mmc_dev(mmc), "map DMA failed\n");
  861. cmd->error = ret;
  862. data->error = ret;
  863. mmc_request_done(mmc, mrq);
  864. return;
  865. }
  866. }
  867. if (cmd->opcode == MMC_GO_IDLE_STATE) {
  868. cmd_val |= SDXC_SEND_INIT_SEQUENCE;
  869. imask |= SDXC_COMMAND_DONE;
  870. }
  871. if (cmd->flags & MMC_RSP_PRESENT) {
  872. cmd_val |= SDXC_RESP_EXPIRE;
  873. if (cmd->flags & MMC_RSP_136)
  874. cmd_val |= SDXC_LONG_RESPONSE;
  875. if (cmd->flags & MMC_RSP_CRC)
  876. cmd_val |= SDXC_CHECK_RESPONSE_CRC;
  877. if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
  878. cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
  879. if (cmd->data->stop) {
  880. imask |= SDXC_AUTO_COMMAND_DONE;
  881. cmd_val |= SDXC_SEND_AUTO_STOP;
  882. } else {
  883. imask |= SDXC_DATA_OVER;
  884. }
  885. if (cmd->data->flags & MMC_DATA_WRITE)
  886. cmd_val |= SDXC_WRITE;
  887. else
  888. wait_dma = true;
  889. } else {
  890. imask |= SDXC_COMMAND_DONE;
  891. }
  892. } else {
  893. imask |= SDXC_COMMAND_DONE;
  894. }
  895. dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
  896. cmd_val & 0x3f, cmd_val, cmd->arg, imask,
  897. mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
  898. spin_lock_irqsave(&host->lock, iflags);
  899. if (host->mrq || host->manual_stop_mrq) {
  900. spin_unlock_irqrestore(&host->lock, iflags);
  901. if (data)
  902. dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
  903. mmc_get_dma_dir(data));
  904. dev_err(mmc_dev(mmc), "request already pending\n");
  905. mrq->cmd->error = -EBUSY;
  906. mmc_request_done(mmc, mrq);
  907. return;
  908. }
  909. if (data) {
  910. mmc_writel(host, REG_BLKSZ, data->blksz);
  911. mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
  912. sunxi_mmc_start_dma(host, data);
  913. }
  914. host->mrq = mrq;
  915. host->wait_dma = wait_dma;
  916. mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
  917. mmc_writel(host, REG_CARG, cmd->arg);
  918. mmc_writel(host, REG_CMDR, cmd_val);
  919. spin_unlock_irqrestore(&host->lock, iflags);
  920. }
  921. static int sunxi_mmc_card_busy(struct mmc_host *mmc)
  922. {
  923. struct sunxi_mmc_host *host = mmc_priv(mmc);
  924. return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
  925. }
  926. static const struct mmc_host_ops sunxi_mmc_ops = {
  927. .request = sunxi_mmc_request,
  928. .set_ios = sunxi_mmc_set_ios,
  929. .get_ro = mmc_gpio_get_ro,
  930. .get_cd = mmc_gpio_get_cd,
  931. .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
  932. .start_signal_voltage_switch = sunxi_mmc_volt_switch,
  933. .hw_reset = sunxi_mmc_hw_reset,
  934. .card_busy = sunxi_mmc_card_busy,
  935. };
  936. static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
  937. [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
  938. [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
  939. [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
  940. [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
  941. /* Value from A83T "new timing mode". Works but might not be right. */
  942. [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
  943. };
  944. static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
  945. [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
  946. [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
  947. [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
  948. [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
  949. [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
  950. };
  951. static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
  952. .idma_des_size_bits = 13,
  953. .clk_delays = NULL,
  954. .can_calibrate = false,
  955. };
  956. static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
  957. .idma_des_size_bits = 16,
  958. .clk_delays = NULL,
  959. .can_calibrate = false,
  960. };
  961. static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
  962. .idma_des_size_bits = 16,
  963. .clk_delays = sunxi_mmc_clk_delays,
  964. .can_calibrate = false,
  965. };
  966. static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
  967. .idma_des_size_bits = 16,
  968. .clk_delays = sunxi_mmc_clk_delays,
  969. .can_calibrate = false,
  970. .ccu_has_timings_switch = true,
  971. };
  972. static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
  973. .idma_des_size_bits = 16,
  974. .clk_delays = sun9i_mmc_clk_delays,
  975. .can_calibrate = false,
  976. };
  977. static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
  978. .idma_des_size_bits = 16,
  979. .clk_delays = NULL,
  980. .can_calibrate = true,
  981. .mask_data0 = true,
  982. .needs_new_timings = true,
  983. };
  984. static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
  985. .idma_des_size_bits = 13,
  986. .clk_delays = NULL,
  987. .can_calibrate = true,
  988. .needs_new_timings = true,
  989. };
  990. static const struct of_device_id sunxi_mmc_of_match[] = {
  991. { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
  992. { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
  993. { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
  994. { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
  995. { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
  996. { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
  997. { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
  998. { /* sentinel */ }
  999. };
  1000. MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
  1001. static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
  1002. {
  1003. int ret;
  1004. if (!IS_ERR(host->reset)) {
  1005. ret = reset_control_reset(host->reset);
  1006. if (ret) {
  1007. dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
  1008. ret);
  1009. return ret;
  1010. }
  1011. }
  1012. ret = clk_prepare_enable(host->clk_ahb);
  1013. if (ret) {
  1014. dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
  1015. goto error_assert_reset;
  1016. }
  1017. ret = clk_prepare_enable(host->clk_mmc);
  1018. if (ret) {
  1019. dev_err(host->dev, "Enable mmc clk err %d\n", ret);
  1020. goto error_disable_clk_ahb;
  1021. }
  1022. ret = clk_prepare_enable(host->clk_output);
  1023. if (ret) {
  1024. dev_err(host->dev, "Enable output clk err %d\n", ret);
  1025. goto error_disable_clk_mmc;
  1026. }
  1027. ret = clk_prepare_enable(host->clk_sample);
  1028. if (ret) {
  1029. dev_err(host->dev, "Enable sample clk err %d\n", ret);
  1030. goto error_disable_clk_output;
  1031. }
  1032. /*
  1033. * Sometimes the controller asserts the irq on boot for some reason,
  1034. * make sure the controller is in a sane state before enabling irqs.
  1035. */
  1036. ret = sunxi_mmc_reset_host(host);
  1037. if (ret)
  1038. goto error_disable_clk_sample;
  1039. return 0;
  1040. error_disable_clk_sample:
  1041. clk_disable_unprepare(host->clk_sample);
  1042. error_disable_clk_output:
  1043. clk_disable_unprepare(host->clk_output);
  1044. error_disable_clk_mmc:
  1045. clk_disable_unprepare(host->clk_mmc);
  1046. error_disable_clk_ahb:
  1047. clk_disable_unprepare(host->clk_ahb);
  1048. error_assert_reset:
  1049. if (!IS_ERR(host->reset))
  1050. reset_control_assert(host->reset);
  1051. return ret;
  1052. }
  1053. static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
  1054. {
  1055. sunxi_mmc_reset_host(host);
  1056. clk_disable_unprepare(host->clk_sample);
  1057. clk_disable_unprepare(host->clk_output);
  1058. clk_disable_unprepare(host->clk_mmc);
  1059. clk_disable_unprepare(host->clk_ahb);
  1060. if (!IS_ERR(host->reset))
  1061. reset_control_assert(host->reset);
  1062. }
  1063. static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
  1064. struct platform_device *pdev)
  1065. {
  1066. int ret;
  1067. host->cfg = of_device_get_match_data(&pdev->dev);
  1068. if (!host->cfg)
  1069. return -EINVAL;
  1070. ret = mmc_regulator_get_supply(host->mmc);
  1071. if (ret)
  1072. return ret;
  1073. host->reg_base = devm_platform_ioremap_resource(pdev, 0);
  1074. if (IS_ERR(host->reg_base))
  1075. return PTR_ERR(host->reg_base);
  1076. host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1077. if (IS_ERR(host->clk_ahb)) {
  1078. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1079. return PTR_ERR(host->clk_ahb);
  1080. }
  1081. host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
  1082. if (IS_ERR(host->clk_mmc)) {
  1083. dev_err(&pdev->dev, "Could not get mmc clock\n");
  1084. return PTR_ERR(host->clk_mmc);
  1085. }
  1086. if (host->cfg->clk_delays) {
  1087. host->clk_output = devm_clk_get(&pdev->dev, "output");
  1088. if (IS_ERR(host->clk_output)) {
  1089. dev_err(&pdev->dev, "Could not get output clock\n");
  1090. return PTR_ERR(host->clk_output);
  1091. }
  1092. host->clk_sample = devm_clk_get(&pdev->dev, "sample");
  1093. if (IS_ERR(host->clk_sample)) {
  1094. dev_err(&pdev->dev, "Could not get sample clock\n");
  1095. return PTR_ERR(host->clk_sample);
  1096. }
  1097. }
  1098. host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
  1099. "ahb");
  1100. if (PTR_ERR(host->reset) == -EPROBE_DEFER)
  1101. return PTR_ERR(host->reset);
  1102. ret = sunxi_mmc_enable(host);
  1103. if (ret)
  1104. return ret;
  1105. host->irq = platform_get_irq(pdev, 0);
  1106. if (host->irq <= 0) {
  1107. ret = -EINVAL;
  1108. goto error_disable_mmc;
  1109. }
  1110. return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
  1111. sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
  1112. error_disable_mmc:
  1113. sunxi_mmc_disable(host);
  1114. return ret;
  1115. }
  1116. static int sunxi_mmc_probe(struct platform_device *pdev)
  1117. {
  1118. struct sunxi_mmc_host *host;
  1119. struct mmc_host *mmc;
  1120. int ret;
  1121. mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
  1122. if (!mmc) {
  1123. dev_err(&pdev->dev, "mmc alloc host failed\n");
  1124. return -ENOMEM;
  1125. }
  1126. platform_set_drvdata(pdev, mmc);
  1127. host = mmc_priv(mmc);
  1128. host->dev = &pdev->dev;
  1129. host->mmc = mmc;
  1130. spin_lock_init(&host->lock);
  1131. ret = sunxi_mmc_resource_request(host, pdev);
  1132. if (ret)
  1133. goto error_free_host;
  1134. host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  1135. &host->sg_dma, GFP_KERNEL);
  1136. if (!host->sg_cpu) {
  1137. dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
  1138. ret = -ENOMEM;
  1139. goto error_free_host;
  1140. }
  1141. if (host->cfg->ccu_has_timings_switch) {
  1142. /*
  1143. * Supports both old and new timing modes.
  1144. * Try setting the clk to new timing mode.
  1145. */
  1146. sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
  1147. /* And check the result */
  1148. ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
  1149. if (ret < 0) {
  1150. /*
  1151. * For whatever reason we were not able to get
  1152. * the current active mode. Default to old mode.
  1153. */
  1154. dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
  1155. host->use_new_timings = false;
  1156. } else {
  1157. host->use_new_timings = !!ret;
  1158. }
  1159. } else if (host->cfg->needs_new_timings) {
  1160. /* Supports new timing mode only */
  1161. host->use_new_timings = true;
  1162. }
  1163. mmc->ops = &sunxi_mmc_ops;
  1164. mmc->max_blk_count = 8192;
  1165. mmc->max_blk_size = 4096;
  1166. mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
  1167. mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
  1168. mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
  1169. /* 400kHz ~ 52MHz */
  1170. mmc->f_min = 400000;
  1171. mmc->f_max = 52000000;
  1172. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1173. MMC_CAP_SDIO_IRQ;
  1174. /*
  1175. * Some H5 devices do not have signal traces precise enough to
  1176. * use HS DDR mode for their eMMC chips.
  1177. *
  1178. * We still enable HS DDR modes for all the other controller
  1179. * variants that support them.
  1180. */
  1181. if ((host->cfg->clk_delays || host->use_new_timings) &&
  1182. !of_device_is_compatible(pdev->dev.of_node,
  1183. "allwinner,sun50i-h5-emmc"))
  1184. mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
  1185. ret = mmc_of_parse(mmc);
  1186. if (ret)
  1187. goto error_free_dma;
  1188. /*
  1189. * If we don't support delay chains in the SoC, we can't use any
  1190. * of the higher speed modes. Mask them out in case the device
  1191. * tree specifies the properties for them, which gets added to
  1192. * the caps by mmc_of_parse() above.
  1193. */
  1194. if (!(host->cfg->clk_delays || host->use_new_timings)) {
  1195. mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
  1196. MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
  1197. mmc->caps2 &= ~MMC_CAP2_HS200;
  1198. }
  1199. /* TODO: This driver doesn't support HS400 mode yet */
  1200. mmc->caps2 &= ~MMC_CAP2_HS400;
  1201. ret = sunxi_mmc_init_host(host);
  1202. if (ret)
  1203. goto error_free_dma;
  1204. pm_runtime_set_active(&pdev->dev);
  1205. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  1206. pm_runtime_use_autosuspend(&pdev->dev);
  1207. pm_runtime_enable(&pdev->dev);
  1208. ret = mmc_add_host(mmc);
  1209. if (ret)
  1210. goto error_free_dma;
  1211. dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",
  1212. mmc->max_req_size >> 10,
  1213. host->use_new_timings ? ", uses new timings mode" : "");
  1214. return 0;
  1215. error_free_dma:
  1216. dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
  1217. error_free_host:
  1218. mmc_free_host(mmc);
  1219. return ret;
  1220. }
  1221. static int sunxi_mmc_remove(struct platform_device *pdev)
  1222. {
  1223. struct mmc_host *mmc = platform_get_drvdata(pdev);
  1224. struct sunxi_mmc_host *host = mmc_priv(mmc);
  1225. mmc_remove_host(mmc);
  1226. pm_runtime_force_suspend(&pdev->dev);
  1227. disable_irq(host->irq);
  1228. sunxi_mmc_disable(host);
  1229. dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
  1230. mmc_free_host(mmc);
  1231. return 0;
  1232. }
  1233. #ifdef CONFIG_PM
  1234. static int sunxi_mmc_runtime_resume(struct device *dev)
  1235. {
  1236. struct mmc_host *mmc = dev_get_drvdata(dev);
  1237. struct sunxi_mmc_host *host = mmc_priv(mmc);
  1238. int ret;
  1239. ret = sunxi_mmc_enable(host);
  1240. if (ret)
  1241. return ret;
  1242. sunxi_mmc_init_host(host);
  1243. sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
  1244. sunxi_mmc_set_clk(host, &mmc->ios);
  1245. enable_irq(host->irq);
  1246. return 0;
  1247. }
  1248. static int sunxi_mmc_runtime_suspend(struct device *dev)
  1249. {
  1250. struct mmc_host *mmc = dev_get_drvdata(dev);
  1251. struct sunxi_mmc_host *host = mmc_priv(mmc);
  1252. /*
  1253. * When clocks are off, it's possible receiving
  1254. * fake interrupts, which will stall the system.
  1255. * Disabling the irq will prevent this.
  1256. */
  1257. disable_irq(host->irq);
  1258. sunxi_mmc_reset_host(host);
  1259. sunxi_mmc_disable(host);
  1260. return 0;
  1261. }
  1262. #endif
  1263. static const struct dev_pm_ops sunxi_mmc_pm_ops = {
  1264. SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
  1265. sunxi_mmc_runtime_resume,
  1266. NULL)
  1267. };
  1268. static struct platform_driver sunxi_mmc_driver = {
  1269. .driver = {
  1270. .name = "sunxi-mmc",
  1271. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1272. .of_match_table = of_match_ptr(sunxi_mmc_of_match),
  1273. .pm = &sunxi_mmc_pm_ops,
  1274. },
  1275. .probe = sunxi_mmc_probe,
  1276. .remove = sunxi_mmc_remove,
  1277. };
  1278. module_platform_driver(sunxi_mmc_driver);
  1279. MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
  1280. MODULE_LICENSE("GPL v2");
  1281. MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
  1282. MODULE_ALIAS("platform:sunxi-mmc");