sdricoh_cs.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sdricoh_cs.c - driver for Ricoh Secure Digital Card Readers that can be
  4. * found on some Ricoh RL5c476 II cardbus bridge
  5. *
  6. * Copyright (C) 2006 - 2008 Sascha Sommer <saschasommer@freenet.de>
  7. */
  8. /*
  9. #define DEBUG
  10. #define VERBOSE_DEBUG
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/highmem.h>
  14. #include <linux/module.h>
  15. #include <linux/pci.h>
  16. #include <linux/ioport.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/scatterlist.h>
  19. #include <pcmcia/cistpl.h>
  20. #include <pcmcia/ds.h>
  21. #include <linux/io.h>
  22. #include <linux/mmc/host.h>
  23. #include <linux/mmc/mmc.h>
  24. #define DRIVER_NAME "sdricoh_cs"
  25. static unsigned int switchlocked;
  26. /* i/o region */
  27. #define SDRICOH_PCI_REGION 0
  28. #define SDRICOH_PCI_REGION_SIZE 0x1000
  29. /* registers */
  30. #define R104_VERSION 0x104
  31. #define R200_CMD 0x200
  32. #define R204_CMD_ARG 0x204
  33. #define R208_DATAIO 0x208
  34. #define R20C_RESP 0x20c
  35. #define R21C_STATUS 0x21c
  36. #define R2E0_INIT 0x2e0
  37. #define R2E4_STATUS_RESP 0x2e4
  38. #define R2F0_RESET 0x2f0
  39. #define R224_MODE 0x224
  40. #define R226_BLOCKSIZE 0x226
  41. #define R228_POWER 0x228
  42. #define R230_DATA 0x230
  43. /* flags for the R21C_STATUS register */
  44. #define STATUS_CMD_FINISHED 0x00000001
  45. #define STATUS_TRANSFER_FINISHED 0x00000004
  46. #define STATUS_CARD_INSERTED 0x00000020
  47. #define STATUS_CARD_LOCKED 0x00000080
  48. #define STATUS_CMD_TIMEOUT 0x00400000
  49. #define STATUS_READY_TO_READ 0x01000000
  50. #define STATUS_READY_TO_WRITE 0x02000000
  51. #define STATUS_BUSY 0x40000000
  52. /* timeouts */
  53. #define SDRICOH_CMD_TIMEOUT_US 1000000
  54. #define SDRICOH_DATA_TIMEOUT_US 1000000
  55. /* list of supported pcmcia devices */
  56. static const struct pcmcia_device_id pcmcia_ids[] = {
  57. /* vendor and device strings followed by their crc32 hashes */
  58. PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay1Controller", 0xd9f522ed,
  59. 0xc3901202),
  60. PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay Controller", 0xd9f522ed,
  61. 0xace80909),
  62. PCMCIA_DEVICE_NULL,
  63. };
  64. MODULE_DEVICE_TABLE(pcmcia, pcmcia_ids);
  65. /* mmc privdata */
  66. struct sdricoh_host {
  67. struct device *dev;
  68. struct mmc_host *mmc; /* MMC structure */
  69. unsigned char __iomem *iobase;
  70. struct pci_dev *pci_dev;
  71. int app_cmd;
  72. };
  73. /***************** register i/o helper functions *****************************/
  74. static inline unsigned int sdricoh_readl(struct sdricoh_host *host,
  75. unsigned int reg)
  76. {
  77. unsigned int value = readl(host->iobase + reg);
  78. dev_vdbg(host->dev, "rl %x 0x%x\n", reg, value);
  79. return value;
  80. }
  81. static inline void sdricoh_writel(struct sdricoh_host *host, unsigned int reg,
  82. unsigned int value)
  83. {
  84. writel(value, host->iobase + reg);
  85. dev_vdbg(host->dev, "wl %x 0x%x\n", reg, value);
  86. }
  87. static inline unsigned int sdricoh_readw(struct sdricoh_host *host,
  88. unsigned int reg)
  89. {
  90. unsigned int value = readw(host->iobase + reg);
  91. dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
  92. return value;
  93. }
  94. static inline void sdricoh_writew(struct sdricoh_host *host, unsigned int reg,
  95. unsigned short value)
  96. {
  97. writew(value, host->iobase + reg);
  98. dev_vdbg(host->dev, "ww %x 0x%x\n", reg, value);
  99. }
  100. static inline unsigned int sdricoh_readb(struct sdricoh_host *host,
  101. unsigned int reg)
  102. {
  103. unsigned int value = readb(host->iobase + reg);
  104. dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
  105. return value;
  106. }
  107. static bool sdricoh_status_ok(struct sdricoh_host *host, unsigned int status,
  108. unsigned int wanted)
  109. {
  110. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  111. return status & wanted;
  112. }
  113. static int sdricoh_query_status(struct sdricoh_host *host, unsigned int wanted)
  114. {
  115. int ret;
  116. unsigned int status = 0;
  117. struct device *dev = host->dev;
  118. ret = read_poll_timeout(sdricoh_readl, status,
  119. sdricoh_status_ok(host, status, wanted),
  120. 32, SDRICOH_DATA_TIMEOUT_US, false,
  121. host, R21C_STATUS);
  122. if (ret) {
  123. dev_err(dev, "query_status: timeout waiting for %x\n", wanted);
  124. return -ETIMEDOUT;
  125. }
  126. /* do not do this check in the loop as some commands fail otherwise */
  127. if (status & 0x7F0000) {
  128. dev_err(dev, "waiting for status bit %x failed\n", wanted);
  129. return -EINVAL;
  130. }
  131. return 0;
  132. }
  133. static int sdricoh_mmc_cmd(struct sdricoh_host *host, struct mmc_command *cmd)
  134. {
  135. unsigned int status, timeout_us;
  136. int ret;
  137. unsigned char opcode = cmd->opcode;
  138. /* reset status reg? */
  139. sdricoh_writel(host, R21C_STATUS, 0x18);
  140. /* MMC_APP_CMDs need some special handling */
  141. if (host->app_cmd) {
  142. opcode |= 64;
  143. host->app_cmd = 0;
  144. } else if (opcode == MMC_APP_CMD)
  145. host->app_cmd = 1;
  146. /* fill parameters */
  147. sdricoh_writel(host, R204_CMD_ARG, cmd->arg);
  148. sdricoh_writel(host, R200_CMD, (0x10000 << 8) | opcode);
  149. /* wait for command completion */
  150. if (!opcode)
  151. return 0;
  152. timeout_us = cmd->busy_timeout ? cmd->busy_timeout * 1000 :
  153. SDRICOH_CMD_TIMEOUT_US;
  154. ret = read_poll_timeout(sdricoh_readl, status,
  155. sdricoh_status_ok(host, status, STATUS_CMD_FINISHED),
  156. 32, timeout_us, false,
  157. host, R21C_STATUS);
  158. /*
  159. * Don't check for timeout status in the loop, as it's not always reset
  160. * correctly.
  161. */
  162. if (ret || status & STATUS_CMD_TIMEOUT)
  163. return -ETIMEDOUT;
  164. return 0;
  165. }
  166. static int sdricoh_reset(struct sdricoh_host *host)
  167. {
  168. dev_dbg(host->dev, "reset\n");
  169. sdricoh_writel(host, R2F0_RESET, 0x10001);
  170. sdricoh_writel(host, R2E0_INIT, 0x10000);
  171. if (sdricoh_readl(host, R2E0_INIT) != 0x10000)
  172. return -EIO;
  173. sdricoh_writel(host, R2E0_INIT, 0x10007);
  174. sdricoh_writel(host, R224_MODE, 0x2000000);
  175. sdricoh_writel(host, R228_POWER, 0xe0);
  176. /* status register ? */
  177. sdricoh_writel(host, R21C_STATUS, 0x18);
  178. return 0;
  179. }
  180. static int sdricoh_blockio(struct sdricoh_host *host, int read,
  181. u8 *buf, int len)
  182. {
  183. int size;
  184. u32 data = 0;
  185. /* wait until the data is available */
  186. if (read) {
  187. if (sdricoh_query_status(host, STATUS_READY_TO_READ))
  188. return -ETIMEDOUT;
  189. sdricoh_writel(host, R21C_STATUS, 0x18);
  190. /* read data */
  191. while (len) {
  192. data = sdricoh_readl(host, R230_DATA);
  193. size = min(len, 4);
  194. len -= size;
  195. while (size) {
  196. *buf = data & 0xFF;
  197. buf++;
  198. data >>= 8;
  199. size--;
  200. }
  201. }
  202. } else {
  203. if (sdricoh_query_status(host, STATUS_READY_TO_WRITE))
  204. return -ETIMEDOUT;
  205. sdricoh_writel(host, R21C_STATUS, 0x18);
  206. /* write data */
  207. while (len) {
  208. size = min(len, 4);
  209. len -= size;
  210. while (size) {
  211. data >>= 8;
  212. data |= (u32)*buf << 24;
  213. buf++;
  214. size--;
  215. }
  216. sdricoh_writel(host, R230_DATA, data);
  217. }
  218. }
  219. return 0;
  220. }
  221. static void sdricoh_request(struct mmc_host *mmc, struct mmc_request *mrq)
  222. {
  223. struct sdricoh_host *host = mmc_priv(mmc);
  224. struct mmc_command *cmd = mrq->cmd;
  225. struct mmc_data *data = cmd->data;
  226. struct device *dev = host->dev;
  227. int i;
  228. dev_dbg(dev, "=============================\n");
  229. dev_dbg(dev, "sdricoh_request opcode=%i\n", cmd->opcode);
  230. sdricoh_writel(host, R21C_STATUS, 0x18);
  231. /* read/write commands seem to require this */
  232. if (data) {
  233. sdricoh_writew(host, R226_BLOCKSIZE, data->blksz);
  234. sdricoh_writel(host, R208_DATAIO, 0);
  235. }
  236. cmd->error = sdricoh_mmc_cmd(host, cmd);
  237. /* read response buffer */
  238. if (cmd->flags & MMC_RSP_PRESENT) {
  239. if (cmd->flags & MMC_RSP_136) {
  240. /* CRC is stripped so we need to do some shifting. */
  241. for (i = 0; i < 4; i++) {
  242. cmd->resp[i] =
  243. sdricoh_readl(host,
  244. R20C_RESP + (3 - i) * 4) << 8;
  245. if (i != 3)
  246. cmd->resp[i] |=
  247. sdricoh_readb(host, R20C_RESP +
  248. (3 - i) * 4 - 1);
  249. }
  250. } else
  251. cmd->resp[0] = sdricoh_readl(host, R20C_RESP);
  252. }
  253. /* transfer data */
  254. if (data && cmd->error == 0) {
  255. dev_dbg(dev, "transfer: blksz %i blocks %i sg_len %i "
  256. "sg length %i\n", data->blksz, data->blocks,
  257. data->sg_len, data->sg->length);
  258. /* enter data reading mode */
  259. sdricoh_writel(host, R21C_STATUS, 0x837f031e);
  260. for (i = 0; i < data->blocks; i++) {
  261. size_t len = data->blksz;
  262. u8 *buf;
  263. struct page *page;
  264. int result;
  265. page = sg_page(data->sg);
  266. buf = kmap(page) + data->sg->offset + (len * i);
  267. result =
  268. sdricoh_blockio(host,
  269. data->flags & MMC_DATA_READ, buf, len);
  270. kunmap(page);
  271. flush_dcache_page(page);
  272. if (result) {
  273. dev_err(dev, "sdricoh_request: cmd %i "
  274. "block transfer failed\n", cmd->opcode);
  275. cmd->error = result;
  276. break;
  277. } else
  278. data->bytes_xfered += len;
  279. }
  280. sdricoh_writel(host, R208_DATAIO, 1);
  281. if (sdricoh_query_status(host, STATUS_TRANSFER_FINISHED)) {
  282. dev_err(dev, "sdricoh_request: transfer end error\n");
  283. cmd->error = -EINVAL;
  284. }
  285. }
  286. /* FIXME check busy flag */
  287. mmc_request_done(mmc, mrq);
  288. dev_dbg(dev, "=============================\n");
  289. }
  290. static void sdricoh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  291. {
  292. struct sdricoh_host *host = mmc_priv(mmc);
  293. dev_dbg(host->dev, "set_ios\n");
  294. if (ios->power_mode == MMC_POWER_ON) {
  295. sdricoh_writel(host, R228_POWER, 0xc0e0);
  296. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  297. sdricoh_writel(host, R224_MODE, 0x2000300);
  298. sdricoh_writel(host, R228_POWER, 0x40e0);
  299. } else {
  300. sdricoh_writel(host, R224_MODE, 0x2000340);
  301. }
  302. } else if (ios->power_mode == MMC_POWER_UP) {
  303. sdricoh_writel(host, R224_MODE, 0x2000320);
  304. sdricoh_writel(host, R228_POWER, 0xe0);
  305. }
  306. }
  307. static int sdricoh_get_ro(struct mmc_host *mmc)
  308. {
  309. struct sdricoh_host *host = mmc_priv(mmc);
  310. unsigned int status;
  311. status = sdricoh_readl(host, R21C_STATUS);
  312. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  313. /* some notebooks seem to have the locked flag switched */
  314. if (switchlocked)
  315. return !(status & STATUS_CARD_LOCKED);
  316. return (status & STATUS_CARD_LOCKED);
  317. }
  318. static const struct mmc_host_ops sdricoh_ops = {
  319. .request = sdricoh_request,
  320. .set_ios = sdricoh_set_ios,
  321. .get_ro = sdricoh_get_ro,
  322. };
  323. /* initialize the control and register it to the mmc framework */
  324. static int sdricoh_init_mmc(struct pci_dev *pci_dev,
  325. struct pcmcia_device *pcmcia_dev)
  326. {
  327. int result;
  328. void __iomem *iobase;
  329. struct mmc_host *mmc;
  330. struct sdricoh_host *host;
  331. struct device *dev = &pcmcia_dev->dev;
  332. /* map iomem */
  333. if (pci_resource_len(pci_dev, SDRICOH_PCI_REGION) !=
  334. SDRICOH_PCI_REGION_SIZE) {
  335. dev_dbg(dev, "unexpected pci resource len\n");
  336. return -ENODEV;
  337. }
  338. iobase =
  339. pci_iomap(pci_dev, SDRICOH_PCI_REGION, SDRICOH_PCI_REGION_SIZE);
  340. if (!iobase) {
  341. dev_err(dev, "unable to map iobase\n");
  342. return -ENODEV;
  343. }
  344. /* check version? */
  345. if (readl(iobase + R104_VERSION) != 0x4000) {
  346. dev_dbg(dev, "no supported mmc controller found\n");
  347. result = -ENODEV;
  348. goto unmap_io;
  349. }
  350. /* allocate privdata */
  351. mmc = pcmcia_dev->priv =
  352. mmc_alloc_host(sizeof(struct sdricoh_host), &pcmcia_dev->dev);
  353. if (!mmc) {
  354. dev_err(dev, "mmc_alloc_host failed\n");
  355. result = -ENOMEM;
  356. goto unmap_io;
  357. }
  358. host = mmc_priv(mmc);
  359. host->iobase = iobase;
  360. host->dev = dev;
  361. host->pci_dev = pci_dev;
  362. mmc->ops = &sdricoh_ops;
  363. /* FIXME: frequency and voltage handling is done by the controller
  364. */
  365. mmc->f_min = 450000;
  366. mmc->f_max = 24000000;
  367. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  368. mmc->caps |= MMC_CAP_4_BIT_DATA;
  369. mmc->max_seg_size = 1024 * 512;
  370. mmc->max_blk_size = 512;
  371. /* reset the controller */
  372. if (sdricoh_reset(host)) {
  373. dev_dbg(dev, "could not reset\n");
  374. result = -EIO;
  375. goto free_host;
  376. }
  377. result = mmc_add_host(mmc);
  378. if (!result) {
  379. dev_dbg(dev, "mmc host registered\n");
  380. return 0;
  381. }
  382. free_host:
  383. mmc_free_host(mmc);
  384. unmap_io:
  385. pci_iounmap(pci_dev, iobase);
  386. return result;
  387. }
  388. /* search for supported mmc controllers */
  389. static int sdricoh_pcmcia_probe(struct pcmcia_device *pcmcia_dev)
  390. {
  391. struct pci_dev *pci_dev = NULL;
  392. dev_info(&pcmcia_dev->dev, "Searching MMC controller for pcmcia device"
  393. " %s %s ...\n", pcmcia_dev->prod_id[0], pcmcia_dev->prod_id[1]);
  394. /* search pci cardbus bridge that contains the mmc controller */
  395. /* the io region is already claimed by yenta_socket... */
  396. while ((pci_dev =
  397. pci_get_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
  398. pci_dev))) {
  399. /* try to init the device */
  400. if (!sdricoh_init_mmc(pci_dev, pcmcia_dev)) {
  401. dev_info(&pcmcia_dev->dev, "MMC controller found\n");
  402. return 0;
  403. }
  404. }
  405. dev_err(&pcmcia_dev->dev, "No MMC controller was found.\n");
  406. return -ENODEV;
  407. }
  408. static void sdricoh_pcmcia_detach(struct pcmcia_device *link)
  409. {
  410. struct mmc_host *mmc = link->priv;
  411. dev_dbg(&link->dev, "detach\n");
  412. /* remove mmc host */
  413. if (mmc) {
  414. struct sdricoh_host *host = mmc_priv(mmc);
  415. mmc_remove_host(mmc);
  416. pci_iounmap(host->pci_dev, host->iobase);
  417. pci_dev_put(host->pci_dev);
  418. mmc_free_host(mmc);
  419. }
  420. pcmcia_disable_device(link);
  421. }
  422. #ifdef CONFIG_PM
  423. static int sdricoh_pcmcia_suspend(struct pcmcia_device *link)
  424. {
  425. dev_dbg(&link->dev, "suspend\n");
  426. return 0;
  427. }
  428. static int sdricoh_pcmcia_resume(struct pcmcia_device *link)
  429. {
  430. struct mmc_host *mmc = link->priv;
  431. dev_dbg(&link->dev, "resume\n");
  432. sdricoh_reset(mmc_priv(mmc));
  433. return 0;
  434. }
  435. #else
  436. #define sdricoh_pcmcia_suspend NULL
  437. #define sdricoh_pcmcia_resume NULL
  438. #endif
  439. static struct pcmcia_driver sdricoh_driver = {
  440. .name = DRIVER_NAME,
  441. .probe = sdricoh_pcmcia_probe,
  442. .remove = sdricoh_pcmcia_detach,
  443. .id_table = pcmcia_ids,
  444. .suspend = sdricoh_pcmcia_suspend,
  445. .resume = sdricoh_pcmcia_resume,
  446. };
  447. module_pcmcia_driver(sdricoh_driver);
  448. module_param(switchlocked, uint, 0444);
  449. MODULE_AUTHOR("Sascha Sommer <saschasommer@freenet.de>");
  450. MODULE_DESCRIPTION("Ricoh PCMCIA Secure Digital Interface driver");
  451. MODULE_LICENSE("GPL");
  452. MODULE_PARM_DESC(switchlocked, "Switch the cards locked status."
  453. "Use this when unlocked cards are shown readonly (default 0)");