sdhci_am654.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
  6. *
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/of.h>
  11. #include <linux/module.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/property.h>
  14. #include <linux/regmap.h>
  15. #include <linux/sys_soc.h>
  16. #include "cqhci.h"
  17. #include "sdhci-pltfm.h"
  18. /* CTL_CFG Registers */
  19. #define CTL_CFG_2 0x14
  20. #define CTL_CFG_3 0x18
  21. #define SLOTTYPE_MASK GENMASK(31, 30)
  22. #define SLOTTYPE_EMBEDDED BIT(30)
  23. #define TUNINGFORSDR50_MASK BIT(13)
  24. /* PHY Registers */
  25. #define PHY_CTRL1 0x100
  26. #define PHY_CTRL2 0x104
  27. #define PHY_CTRL3 0x108
  28. #define PHY_CTRL4 0x10C
  29. #define PHY_CTRL5 0x110
  30. #define PHY_CTRL6 0x114
  31. #define PHY_STAT1 0x130
  32. #define PHY_STAT2 0x134
  33. #define IOMUX_ENABLE_SHIFT 31
  34. #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
  35. #define OTAPDLYENA_SHIFT 20
  36. #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
  37. #define OTAPDLYSEL_SHIFT 12
  38. #define OTAPDLYSEL_MASK GENMASK(15, 12)
  39. #define STRBSEL_SHIFT 24
  40. #define STRBSEL_4BIT_MASK GENMASK(27, 24)
  41. #define STRBSEL_8BIT_MASK GENMASK(31, 24)
  42. #define SEL50_SHIFT 8
  43. #define SEL50_MASK BIT(SEL50_SHIFT)
  44. #define SEL100_SHIFT 9
  45. #define SEL100_MASK BIT(SEL100_SHIFT)
  46. #define FREQSEL_SHIFT 8
  47. #define FREQSEL_MASK GENMASK(10, 8)
  48. #define CLKBUFSEL_SHIFT 0
  49. #define CLKBUFSEL_MASK GENMASK(2, 0)
  50. #define DLL_TRIM_ICP_SHIFT 4
  51. #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
  52. #define DR_TY_SHIFT 20
  53. #define DR_TY_MASK GENMASK(22, 20)
  54. #define ENDLL_SHIFT 1
  55. #define ENDLL_MASK BIT(ENDLL_SHIFT)
  56. #define DLLRDY_SHIFT 0
  57. #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
  58. #define PDB_SHIFT 0
  59. #define PDB_MASK BIT(PDB_SHIFT)
  60. #define CALDONE_SHIFT 1
  61. #define CALDONE_MASK BIT(CALDONE_SHIFT)
  62. #define RETRIM_SHIFT 17
  63. #define RETRIM_MASK BIT(RETRIM_SHIFT)
  64. #define SELDLYTXCLK_SHIFT 17
  65. #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
  66. #define SELDLYRXCLK_SHIFT 16
  67. #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
  68. #define ITAPDLYSEL_SHIFT 0
  69. #define ITAPDLYSEL_MASK GENMASK(4, 0)
  70. #define ITAPDLYENA_SHIFT 8
  71. #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
  72. #define ITAPCHGWIN_SHIFT 9
  73. #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
  74. #define DRIVER_STRENGTH_50_OHM 0x0
  75. #define DRIVER_STRENGTH_33_OHM 0x1
  76. #define DRIVER_STRENGTH_66_OHM 0x2
  77. #define DRIVER_STRENGTH_100_OHM 0x3
  78. #define DRIVER_STRENGTH_40_OHM 0x4
  79. #define CLOCK_TOO_SLOW_HZ 50000000
  80. /* Command Queue Host Controller Interface Base address */
  81. #define SDHCI_AM654_CQE_BASE_ADDR 0x200
  82. static struct regmap_config sdhci_am654_regmap_config = {
  83. .reg_bits = 32,
  84. .val_bits = 32,
  85. .reg_stride = 4,
  86. .fast_io = true,
  87. };
  88. struct timing_data {
  89. const char *otap_binding;
  90. const char *itap_binding;
  91. u32 capability;
  92. };
  93. static const struct timing_data td[] = {
  94. [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
  95. "ti,itap-del-sel-legacy",
  96. 0},
  97. [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
  98. "ti,itap-del-sel-mmc-hs",
  99. MMC_CAP_MMC_HIGHSPEED},
  100. [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
  101. "ti,itap-del-sel-sd-hs",
  102. MMC_CAP_SD_HIGHSPEED},
  103. [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
  104. "ti,itap-del-sel-sdr12",
  105. MMC_CAP_UHS_SDR12},
  106. [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
  107. "ti,itap-del-sel-sdr25",
  108. MMC_CAP_UHS_SDR25},
  109. [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
  110. NULL,
  111. MMC_CAP_UHS_SDR50},
  112. [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
  113. NULL,
  114. MMC_CAP_UHS_SDR104},
  115. [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
  116. NULL,
  117. MMC_CAP_UHS_DDR50},
  118. [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
  119. "ti,itap-del-sel-ddr52",
  120. MMC_CAP_DDR},
  121. [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
  122. NULL,
  123. MMC_CAP2_HS200},
  124. [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
  125. NULL,
  126. MMC_CAP2_HS400},
  127. };
  128. struct sdhci_am654_data {
  129. struct regmap *base;
  130. bool legacy_otapdly;
  131. int otap_del_sel[ARRAY_SIZE(td)];
  132. int itap_del_sel[ARRAY_SIZE(td)];
  133. int clkbuf_sel;
  134. int trm_icp;
  135. int drv_strength;
  136. int strb_sel;
  137. u32 flags;
  138. };
  139. struct sdhci_am654_driver_data {
  140. const struct sdhci_pltfm_data *pdata;
  141. u32 flags;
  142. #define IOMUX_PRESENT (1 << 0)
  143. #define FREQSEL_2_BIT (1 << 1)
  144. #define STRBSEL_4_BIT (1 << 2)
  145. #define DLL_PRESENT (1 << 3)
  146. #define DLL_CALIB (1 << 4)
  147. };
  148. static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
  149. {
  150. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  151. struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  152. int sel50, sel100, freqsel;
  153. u32 mask, val;
  154. int ret;
  155. /* Disable delay chain mode */
  156. regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
  157. SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
  158. if (sdhci_am654->flags & FREQSEL_2_BIT) {
  159. switch (clock) {
  160. case 200000000:
  161. sel50 = 0;
  162. sel100 = 0;
  163. break;
  164. case 100000000:
  165. sel50 = 0;
  166. sel100 = 1;
  167. break;
  168. default:
  169. sel50 = 1;
  170. sel100 = 0;
  171. }
  172. /* Configure PHY DLL frequency */
  173. mask = SEL50_MASK | SEL100_MASK;
  174. val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
  175. regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
  176. } else {
  177. switch (clock) {
  178. case 200000000:
  179. freqsel = 0x0;
  180. break;
  181. default:
  182. freqsel = 0x4;
  183. }
  184. regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
  185. freqsel << FREQSEL_SHIFT);
  186. }
  187. /* Configure DLL TRIM */
  188. mask = DLL_TRIM_ICP_MASK;
  189. val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
  190. /* Configure DLL driver strength */
  191. mask |= DR_TY_MASK;
  192. val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
  193. regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
  194. /* Enable DLL */
  195. regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
  196. 0x1 << ENDLL_SHIFT);
  197. /*
  198. * Poll for DLL ready. Use a one second timeout.
  199. * Works in all experiments done so far
  200. */
  201. ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
  202. val & DLLRDY_MASK, 1000, 1000000);
  203. if (ret) {
  204. dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
  205. return;
  206. }
  207. }
  208. static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
  209. u32 itapdly)
  210. {
  211. /* Set ITAPCHGWIN before writing to ITAPDLY */
  212. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
  213. 1 << ITAPCHGWIN_SHIFT);
  214. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
  215. itapdly << ITAPDLYSEL_SHIFT);
  216. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
  217. }
  218. static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
  219. unsigned char timing)
  220. {
  221. u32 mask, val;
  222. regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
  223. val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
  224. mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
  225. regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
  226. sdhci_am654_write_itapdly(sdhci_am654,
  227. sdhci_am654->itap_del_sel[timing]);
  228. }
  229. static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
  230. {
  231. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  232. struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  233. unsigned char timing = host->mmc->ios.timing;
  234. u32 otap_del_sel;
  235. u32 otap_del_ena;
  236. u32 mask, val;
  237. regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
  238. sdhci_set_clock(host, clock);
  239. /* Setup DLL Output TAP delay */
  240. if (sdhci_am654->legacy_otapdly)
  241. otap_del_sel = sdhci_am654->otap_del_sel[0];
  242. else
  243. otap_del_sel = sdhci_am654->otap_del_sel[timing];
  244. otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
  245. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  246. val = (otap_del_ena << OTAPDLYENA_SHIFT) |
  247. (otap_del_sel << OTAPDLYSEL_SHIFT);
  248. /* Write to STRBSEL for HS400 speed mode */
  249. if (timing == MMC_TIMING_MMC_HS400) {
  250. if (sdhci_am654->flags & STRBSEL_4_BIT)
  251. mask |= STRBSEL_4BIT_MASK;
  252. else
  253. mask |= STRBSEL_8BIT_MASK;
  254. val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
  255. }
  256. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
  257. if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
  258. sdhci_am654_setup_dll(host, clock);
  259. else
  260. sdhci_am654_setup_delay_chain(sdhci_am654, timing);
  261. regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
  262. sdhci_am654->clkbuf_sel);
  263. }
  264. static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
  265. unsigned int clock)
  266. {
  267. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  268. struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  269. unsigned char timing = host->mmc->ios.timing;
  270. u32 otap_del_sel;
  271. u32 mask, val;
  272. /* Setup DLL Output TAP delay */
  273. if (sdhci_am654->legacy_otapdly)
  274. otap_del_sel = sdhci_am654->otap_del_sel[0];
  275. else
  276. otap_del_sel = sdhci_am654->otap_del_sel[timing];
  277. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  278. val = (0x1 << OTAPDLYENA_SHIFT) |
  279. (otap_del_sel << OTAPDLYSEL_SHIFT);
  280. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
  281. regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
  282. sdhci_am654->clkbuf_sel);
  283. sdhci_set_clock(host, clock);
  284. }
  285. static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
  286. {
  287. writeb(val, host->ioaddr + reg);
  288. usleep_range(1000, 10000);
  289. return readb(host->ioaddr + reg);
  290. }
  291. #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
  292. static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
  293. {
  294. unsigned char timing = host->mmc->ios.timing;
  295. u8 pwr;
  296. int ret;
  297. if (reg == SDHCI_HOST_CONTROL) {
  298. switch (timing) {
  299. /*
  300. * According to the data manual, HISPD bit
  301. * should not be set in these speed modes.
  302. */
  303. case MMC_TIMING_SD_HS:
  304. case MMC_TIMING_MMC_HS:
  305. case MMC_TIMING_UHS_SDR12:
  306. case MMC_TIMING_UHS_SDR25:
  307. val &= ~SDHCI_CTRL_HISPD;
  308. }
  309. }
  310. writeb(val, host->ioaddr + reg);
  311. if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
  312. /*
  313. * Power on will not happen until the card detect debounce
  314. * timer expires. Wait at least 1.5 seconds for the power on
  315. * bit to be set
  316. */
  317. ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
  318. pwr & SDHCI_POWER_ON, 0,
  319. MAX_POWER_ON_TIMEOUT, false, host, val,
  320. reg);
  321. if (ret)
  322. dev_warn(mmc_dev(host->mmc), "Power on failed\n");
  323. }
  324. }
  325. static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
  326. {
  327. struct sdhci_host *host = mmc_priv(mmc);
  328. int err = sdhci_execute_tuning(mmc, opcode);
  329. if (err)
  330. return err;
  331. /*
  332. * Tuning data remains in the buffer after tuning.
  333. * Do a command and data reset to get rid of it
  334. */
  335. sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
  336. return 0;
  337. }
  338. static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
  339. {
  340. int cmd_error = 0;
  341. int data_error = 0;
  342. if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
  343. return intmask;
  344. cqhci_irq(host->mmc, intmask, cmd_error, data_error);
  345. return 0;
  346. }
  347. #define ITAP_MAX 32
  348. static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
  349. u32 opcode)
  350. {
  351. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  352. struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  353. int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
  354. u32 itap;
  355. /* Enable ITAPDLY */
  356. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
  357. 1 << ITAPDLYENA_SHIFT);
  358. for (itap = 0; itap < ITAP_MAX; itap++) {
  359. sdhci_am654_write_itapdly(sdhci_am654, itap);
  360. cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
  361. if (cur_val && !prev_val)
  362. pass_window = itap;
  363. if (!cur_val)
  364. fail_len++;
  365. prev_val = cur_val;
  366. }
  367. /*
  368. * Having determined the length of the failing window and start of
  369. * the passing window calculate the length of the passing window and
  370. * set the final value halfway through it considering the range as a
  371. * circular buffer
  372. */
  373. pass_len = ITAP_MAX - fail_len;
  374. itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
  375. sdhci_am654_write_itapdly(sdhci_am654, itap);
  376. return 0;
  377. }
  378. static struct sdhci_ops sdhci_am654_ops = {
  379. .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
  380. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  381. .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
  382. .set_uhs_signaling = sdhci_set_uhs_signaling,
  383. .set_bus_width = sdhci_set_bus_width,
  384. .set_power = sdhci_set_power_and_bus_voltage,
  385. .set_clock = sdhci_am654_set_clock,
  386. .write_b = sdhci_am654_write_b,
  387. .irq = sdhci_am654_cqhci_irq,
  388. .reset = sdhci_reset,
  389. };
  390. static const struct sdhci_pltfm_data sdhci_am654_pdata = {
  391. .ops = &sdhci_am654_ops,
  392. .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
  393. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  394. };
  395. static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
  396. .pdata = &sdhci_am654_pdata,
  397. .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
  398. DLL_CALIB,
  399. };
  400. static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
  401. .pdata = &sdhci_am654_pdata,
  402. .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
  403. };
  404. static struct sdhci_ops sdhci_j721e_8bit_ops = {
  405. .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
  406. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  407. .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
  408. .set_uhs_signaling = sdhci_set_uhs_signaling,
  409. .set_bus_width = sdhci_set_bus_width,
  410. .set_power = sdhci_set_power_and_bus_voltage,
  411. .set_clock = sdhci_am654_set_clock,
  412. .write_b = sdhci_am654_write_b,
  413. .irq = sdhci_am654_cqhci_irq,
  414. .reset = sdhci_reset,
  415. };
  416. static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
  417. .ops = &sdhci_j721e_8bit_ops,
  418. .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
  419. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  420. };
  421. static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
  422. .pdata = &sdhci_j721e_8bit_pdata,
  423. .flags = DLL_PRESENT | DLL_CALIB,
  424. };
  425. static struct sdhci_ops sdhci_j721e_4bit_ops = {
  426. .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
  427. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  428. .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
  429. .set_uhs_signaling = sdhci_set_uhs_signaling,
  430. .set_bus_width = sdhci_set_bus_width,
  431. .set_power = sdhci_set_power_and_bus_voltage,
  432. .set_clock = sdhci_j721e_4bit_set_clock,
  433. .write_b = sdhci_am654_write_b,
  434. .irq = sdhci_am654_cqhci_irq,
  435. .reset = sdhci_reset,
  436. };
  437. static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
  438. .ops = &sdhci_j721e_4bit_ops,
  439. .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
  440. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  441. };
  442. static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
  443. .pdata = &sdhci_j721e_4bit_pdata,
  444. .flags = IOMUX_PRESENT,
  445. };
  446. static const struct soc_device_attribute sdhci_am654_devices[] = {
  447. { .family = "AM65X",
  448. .revision = "SR1.0",
  449. .data = &sdhci_am654_sr1_drvdata
  450. },
  451. {/* sentinel */}
  452. };
  453. static void sdhci_am654_dumpregs(struct mmc_host *mmc)
  454. {
  455. sdhci_dumpregs(mmc_priv(mmc));
  456. }
  457. static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
  458. .enable = sdhci_cqe_enable,
  459. .disable = sdhci_cqe_disable,
  460. .dumpregs = sdhci_am654_dumpregs,
  461. };
  462. static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
  463. {
  464. struct cqhci_host *cq_host;
  465. int ret;
  466. cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host),
  467. GFP_KERNEL);
  468. if (!cq_host)
  469. return -ENOMEM;
  470. cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
  471. cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
  472. cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  473. cq_host->ops = &sdhci_am654_cqhci_ops;
  474. host->mmc->caps2 |= MMC_CAP2_CQE;
  475. ret = cqhci_init(cq_host, host->mmc, 1);
  476. return ret;
  477. }
  478. static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
  479. struct sdhci_am654_data *sdhci_am654)
  480. {
  481. struct device *dev = mmc_dev(host->mmc);
  482. int i;
  483. int ret;
  484. ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
  485. &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
  486. if (ret) {
  487. /*
  488. * ti,otap-del-sel-legacy is mandatory, look for old binding
  489. * if not found.
  490. */
  491. ret = device_property_read_u32(dev, "ti,otap-del-sel",
  492. &sdhci_am654->otap_del_sel[0]);
  493. if (ret) {
  494. dev_err(dev, "Couldn't find otap-del-sel\n");
  495. return ret;
  496. }
  497. dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
  498. sdhci_am654->legacy_otapdly = true;
  499. return 0;
  500. }
  501. for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
  502. ret = device_property_read_u32(dev, td[i].otap_binding,
  503. &sdhci_am654->otap_del_sel[i]);
  504. if (ret) {
  505. dev_dbg(dev, "Couldn't find %s\n",
  506. td[i].otap_binding);
  507. /*
  508. * Remove the corresponding capability
  509. * if an otap-del-sel value is not found
  510. */
  511. if (i <= MMC_TIMING_MMC_DDR52)
  512. host->mmc->caps &= ~td[i].capability;
  513. else
  514. host->mmc->caps2 &= ~td[i].capability;
  515. }
  516. if (td[i].itap_binding)
  517. device_property_read_u32(dev, td[i].itap_binding,
  518. &sdhci_am654->itap_del_sel[i]);
  519. }
  520. return 0;
  521. }
  522. static int sdhci_am654_init(struct sdhci_host *host)
  523. {
  524. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  525. struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  526. u32 ctl_cfg_2 = 0;
  527. u32 mask;
  528. u32 val;
  529. int ret;
  530. /* Reset OTAP to default value */
  531. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  532. regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
  533. if (sdhci_am654->flags & DLL_CALIB) {
  534. regmap_read(sdhci_am654->base, PHY_STAT1, &val);
  535. if (~val & CALDONE_MASK) {
  536. /* Calibrate IO lines */
  537. regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
  538. PDB_MASK, PDB_MASK);
  539. ret = regmap_read_poll_timeout(sdhci_am654->base,
  540. PHY_STAT1, val,
  541. val & CALDONE_MASK,
  542. 1, 20);
  543. if (ret)
  544. return ret;
  545. }
  546. }
  547. /* Enable pins by setting IO mux to 0 */
  548. if (sdhci_am654->flags & IOMUX_PRESENT)
  549. regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
  550. IOMUX_ENABLE_MASK, 0);
  551. /* Set slot type based on SD or eMMC */
  552. if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
  553. ctl_cfg_2 = SLOTTYPE_EMBEDDED;
  554. regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
  555. ctl_cfg_2);
  556. /* Enable tuning for SDR50 */
  557. regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
  558. TUNINGFORSDR50_MASK);
  559. ret = sdhci_setup_host(host);
  560. if (ret)
  561. return ret;
  562. ret = sdhci_am654_cqe_add_host(host);
  563. if (ret)
  564. goto err_cleanup_host;
  565. ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
  566. if (ret)
  567. goto err_cleanup_host;
  568. ret = __sdhci_add_host(host);
  569. if (ret)
  570. goto err_cleanup_host;
  571. return 0;
  572. err_cleanup_host:
  573. sdhci_cleanup_host(host);
  574. return ret;
  575. }
  576. static int sdhci_am654_get_of_property(struct platform_device *pdev,
  577. struct sdhci_am654_data *sdhci_am654)
  578. {
  579. struct device *dev = &pdev->dev;
  580. int drv_strength;
  581. int ret;
  582. if (sdhci_am654->flags & DLL_PRESENT) {
  583. ret = device_property_read_u32(dev, "ti,trm-icp",
  584. &sdhci_am654->trm_icp);
  585. if (ret)
  586. return ret;
  587. ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
  588. &drv_strength);
  589. if (ret)
  590. return ret;
  591. switch (drv_strength) {
  592. case 50:
  593. sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
  594. break;
  595. case 33:
  596. sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
  597. break;
  598. case 66:
  599. sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
  600. break;
  601. case 100:
  602. sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
  603. break;
  604. case 40:
  605. sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
  606. break;
  607. default:
  608. dev_err(dev, "Invalid driver strength\n");
  609. return -EINVAL;
  610. }
  611. }
  612. device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
  613. device_property_read_u32(dev, "ti,clkbuf-sel",
  614. &sdhci_am654->clkbuf_sel);
  615. sdhci_get_of_property(pdev);
  616. return 0;
  617. }
  618. static const struct of_device_id sdhci_am654_of_match[] = {
  619. {
  620. .compatible = "ti,am654-sdhci-5.1",
  621. .data = &sdhci_am654_drvdata,
  622. },
  623. {
  624. .compatible = "ti,j721e-sdhci-8bit",
  625. .data = &sdhci_j721e_8bit_drvdata,
  626. },
  627. {
  628. .compatible = "ti,j721e-sdhci-4bit",
  629. .data = &sdhci_j721e_4bit_drvdata,
  630. },
  631. { /* sentinel */ }
  632. };
  633. MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
  634. static int sdhci_am654_probe(struct platform_device *pdev)
  635. {
  636. const struct sdhci_am654_driver_data *drvdata;
  637. const struct soc_device_attribute *soc;
  638. struct sdhci_pltfm_host *pltfm_host;
  639. struct sdhci_am654_data *sdhci_am654;
  640. const struct of_device_id *match;
  641. struct sdhci_host *host;
  642. struct clk *clk_xin;
  643. struct device *dev = &pdev->dev;
  644. void __iomem *base;
  645. int ret;
  646. match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
  647. drvdata = match->data;
  648. /* Update drvdata based on SoC revision */
  649. soc = soc_device_match(sdhci_am654_devices);
  650. if (soc && soc->data)
  651. drvdata = soc->data;
  652. host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
  653. if (IS_ERR(host))
  654. return PTR_ERR(host);
  655. pltfm_host = sdhci_priv(host);
  656. sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
  657. sdhci_am654->flags = drvdata->flags;
  658. clk_xin = devm_clk_get(dev, "clk_xin");
  659. if (IS_ERR(clk_xin)) {
  660. dev_err(dev, "clk_xin clock not found.\n");
  661. ret = PTR_ERR(clk_xin);
  662. goto err_pltfm_free;
  663. }
  664. pltfm_host->clk = clk_xin;
  665. /* Clocks are enabled using pm_runtime */
  666. pm_runtime_enable(dev);
  667. ret = pm_runtime_get_sync(dev);
  668. if (ret < 0) {
  669. pm_runtime_put_noidle(dev);
  670. goto pm_runtime_disable;
  671. }
  672. base = devm_platform_ioremap_resource(pdev, 1);
  673. if (IS_ERR(base)) {
  674. ret = PTR_ERR(base);
  675. goto pm_runtime_put;
  676. }
  677. sdhci_am654->base = devm_regmap_init_mmio(dev, base,
  678. &sdhci_am654_regmap_config);
  679. if (IS_ERR(sdhci_am654->base)) {
  680. dev_err(dev, "Failed to initialize regmap\n");
  681. ret = PTR_ERR(sdhci_am654->base);
  682. goto pm_runtime_put;
  683. }
  684. ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
  685. if (ret)
  686. goto pm_runtime_put;
  687. ret = mmc_of_parse(host->mmc);
  688. if (ret) {
  689. dev_err(dev, "parsing dt failed (%d)\n", ret);
  690. goto pm_runtime_put;
  691. }
  692. host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
  693. ret = sdhci_am654_init(host);
  694. if (ret)
  695. goto pm_runtime_put;
  696. return 0;
  697. pm_runtime_put:
  698. pm_runtime_put_sync(dev);
  699. pm_runtime_disable:
  700. pm_runtime_disable(dev);
  701. err_pltfm_free:
  702. sdhci_pltfm_free(pdev);
  703. return ret;
  704. }
  705. static int sdhci_am654_remove(struct platform_device *pdev)
  706. {
  707. struct sdhci_host *host = platform_get_drvdata(pdev);
  708. int ret;
  709. sdhci_remove_host(host, true);
  710. ret = pm_runtime_put_sync(&pdev->dev);
  711. if (ret < 0)
  712. return ret;
  713. pm_runtime_disable(&pdev->dev);
  714. sdhci_pltfm_free(pdev);
  715. return 0;
  716. }
  717. static struct platform_driver sdhci_am654_driver = {
  718. .driver = {
  719. .name = "sdhci-am654",
  720. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  721. .of_match_table = sdhci_am654_of_match,
  722. },
  723. .probe = sdhci_am654_probe,
  724. .remove = sdhci_am654_remove,
  725. };
  726. module_platform_driver(sdhci_am654_driver);
  727. MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
  728. MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
  729. MODULE_LICENSE("GPL");