sdhci.h 28 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
  4. *
  5. * Header file for Host Controller registers and I/O accessors.
  6. *
  7. * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
  8. */
  9. #ifndef __SDHCI_HW_H
  10. #define __SDHCI_HW_H
  11. #include <linux/bits.h>
  12. #include <linux/scatterlist.h>
  13. #include <linux/compiler.h>
  14. #include <linux/types.h>
  15. #include <linux/io.h>
  16. #include <linux/leds.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/android_kabi.h>
  19. #include <linux/mmc/host.h>
  20. /*
  21. * Controller registers
  22. */
  23. #define SDHCI_DMA_ADDRESS 0x00
  24. #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
  25. #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
  26. #define SDHCI_BLOCK_SIZE 0x04
  27. #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  28. #define SDHCI_BLOCK_COUNT 0x06
  29. #define SDHCI_ARGUMENT 0x08
  30. #define SDHCI_TRANSFER_MODE 0x0C
  31. #define SDHCI_TRNS_DMA 0x01
  32. #define SDHCI_TRNS_BLK_CNT_EN 0x02
  33. #define SDHCI_TRNS_AUTO_CMD12 0x04
  34. #define SDHCI_TRNS_AUTO_CMD23 0x08
  35. #define SDHCI_TRNS_AUTO_SEL 0x0C
  36. #define SDHCI_TRNS_READ 0x10
  37. #define SDHCI_TRNS_MULTI 0x20
  38. #define SDHCI_COMMAND 0x0E
  39. #define SDHCI_CMD_RESP_MASK 0x03
  40. #define SDHCI_CMD_CRC 0x08
  41. #define SDHCI_CMD_INDEX 0x10
  42. #define SDHCI_CMD_DATA 0x20
  43. #define SDHCI_CMD_ABORTCMD 0xC0
  44. #define SDHCI_CMD_RESP_NONE 0x00
  45. #define SDHCI_CMD_RESP_LONG 0x01
  46. #define SDHCI_CMD_RESP_SHORT 0x02
  47. #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
  48. #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  49. #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  50. #define SDHCI_RESPONSE 0x10
  51. #define SDHCI_BUFFER 0x20
  52. #define SDHCI_PRESENT_STATE 0x24
  53. #define SDHCI_CMD_INHIBIT 0x00000001
  54. #define SDHCI_DATA_INHIBIT 0x00000002
  55. #define SDHCI_DOING_WRITE 0x00000100
  56. #define SDHCI_DOING_READ 0x00000200
  57. #define SDHCI_SPACE_AVAILABLE 0x00000400
  58. #define SDHCI_DATA_AVAILABLE 0x00000800
  59. #define SDHCI_CARD_PRESENT 0x00010000
  60. #define SDHCI_CARD_PRES_SHIFT 16
  61. #define SDHCI_CD_STABLE 0x00020000
  62. #define SDHCI_CD_LVL 0x00040000
  63. #define SDHCI_CD_LVL_SHIFT 18
  64. #define SDHCI_WRITE_PROTECT 0x00080000
  65. #define SDHCI_DATA_LVL_MASK 0x00F00000
  66. #define SDHCI_DATA_LVL_SHIFT 20
  67. #define SDHCI_DATA_0_LVL_MASK 0x00100000
  68. #define SDHCI_CMD_LVL 0x01000000
  69. #define SDHCI_HOST_CONTROL 0x28
  70. #define SDHCI_CTRL_LED 0x01
  71. #define SDHCI_CTRL_4BITBUS 0x02
  72. #define SDHCI_CTRL_HISPD 0x04
  73. #define SDHCI_CTRL_DMA_MASK 0x18
  74. #define SDHCI_CTRL_SDMA 0x00
  75. #define SDHCI_CTRL_ADMA1 0x08
  76. #define SDHCI_CTRL_ADMA32 0x10
  77. #define SDHCI_CTRL_ADMA64 0x18
  78. #define SDHCI_CTRL_ADMA3 0x18
  79. #define SDHCI_CTRL_8BITBUS 0x20
  80. #define SDHCI_CTRL_CDTEST_INS 0x40
  81. #define SDHCI_CTRL_CDTEST_EN 0x80
  82. #define SDHCI_POWER_CONTROL 0x29
  83. #define SDHCI_POWER_ON 0x01
  84. #define SDHCI_POWER_180 0x0A
  85. #define SDHCI_POWER_300 0x0C
  86. #define SDHCI_POWER_330 0x0E
  87. #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  88. #define SDHCI_WAKE_UP_CONTROL 0x2B
  89. #define SDHCI_WAKE_ON_INT 0x01
  90. #define SDHCI_WAKE_ON_INSERT 0x02
  91. #define SDHCI_WAKE_ON_REMOVE 0x04
  92. #define SDHCI_CLOCK_CONTROL 0x2C
  93. #define SDHCI_DIVIDER_SHIFT 8
  94. #define SDHCI_DIVIDER_HI_SHIFT 6
  95. #define SDHCI_DIV_MASK 0xFF
  96. #define SDHCI_DIV_MASK_LEN 8
  97. #define SDHCI_DIV_HI_MASK 0x300
  98. #define SDHCI_PROG_CLOCK_MODE 0x0020
  99. #define SDHCI_CLOCK_CARD_EN 0x0004
  100. #define SDHCI_CLOCK_PLL_EN 0x0008
  101. #define SDHCI_CLOCK_INT_STABLE 0x0002
  102. #define SDHCI_CLOCK_INT_EN 0x0001
  103. #define SDHCI_TIMEOUT_CONTROL 0x2E
  104. #define SDHCI_SOFTWARE_RESET 0x2F
  105. #define SDHCI_RESET_ALL 0x01
  106. #define SDHCI_RESET_CMD 0x02
  107. #define SDHCI_RESET_DATA 0x04
  108. #define SDHCI_INT_STATUS 0x30
  109. #define SDHCI_INT_ENABLE 0x34
  110. #define SDHCI_SIGNAL_ENABLE 0x38
  111. #define SDHCI_INT_RESPONSE 0x00000001
  112. #define SDHCI_INT_DATA_END 0x00000002
  113. #define SDHCI_INT_BLK_GAP 0x00000004
  114. #define SDHCI_INT_DMA_END 0x00000008
  115. #define SDHCI_INT_SPACE_AVAIL 0x00000010
  116. #define SDHCI_INT_DATA_AVAIL 0x00000020
  117. #define SDHCI_INT_CARD_INSERT 0x00000040
  118. #define SDHCI_INT_CARD_REMOVE 0x00000080
  119. #define SDHCI_INT_CARD_INT 0x00000100
  120. #define SDHCI_INT_RETUNE 0x00001000
  121. #define SDHCI_INT_CQE 0x00004000
  122. #define SDHCI_INT_ERROR 0x00008000
  123. #define SDHCI_INT_TIMEOUT 0x00010000
  124. #define SDHCI_INT_CRC 0x00020000
  125. #define SDHCI_INT_END_BIT 0x00040000
  126. #define SDHCI_INT_INDEX 0x00080000
  127. #define SDHCI_INT_DATA_TIMEOUT 0x00100000
  128. #define SDHCI_INT_DATA_CRC 0x00200000
  129. #define SDHCI_INT_DATA_END_BIT 0x00400000
  130. #define SDHCI_INT_BUS_POWER 0x00800000
  131. #define SDHCI_INT_AUTO_CMD_ERR 0x01000000
  132. #define SDHCI_INT_ADMA_ERROR 0x02000000
  133. #define SDHCI_INT_NORMAL_MASK 0x00007FFF
  134. #define SDHCI_INT_ERROR_MASK 0xFFFF8000
  135. #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
  136. SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
  137. SDHCI_INT_AUTO_CMD_ERR)
  138. #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
  139. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
  140. SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
  141. SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
  142. SDHCI_INT_BLK_GAP)
  143. #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
  144. #define SDHCI_CQE_INT_ERR_MASK ( \
  145. SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
  146. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
  147. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
  148. #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
  149. #define SDHCI_AUTO_CMD_STATUS 0x3C
  150. #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
  151. #define SDHCI_AUTO_CMD_CRC 0x00000004
  152. #define SDHCI_AUTO_CMD_END_BIT 0x00000008
  153. #define SDHCI_AUTO_CMD_INDEX 0x00000010
  154. #define SDHCI_HOST_CONTROL2 0x3E
  155. #define SDHCI_CTRL_UHS_MASK 0x0007
  156. #define SDHCI_CTRL_UHS_SDR12 0x0000
  157. #define SDHCI_CTRL_UHS_SDR25 0x0001
  158. #define SDHCI_CTRL_UHS_SDR50 0x0002
  159. #define SDHCI_CTRL_UHS_SDR104 0x0003
  160. #define SDHCI_CTRL_UHS_DDR50 0x0004
  161. #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
  162. #define SDHCI_CTRL_VDD_180 0x0008
  163. #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
  164. #define SDHCI_CTRL_DRV_TYPE_B 0x0000
  165. #define SDHCI_CTRL_DRV_TYPE_A 0x0010
  166. #define SDHCI_CTRL_DRV_TYPE_C 0x0020
  167. #define SDHCI_CTRL_DRV_TYPE_D 0x0030
  168. #define SDHCI_CTRL_EXEC_TUNING 0x0040
  169. #define SDHCI_CTRL_TUNED_CLK 0x0080
  170. #define SDHCI_CMD23_ENABLE 0x0800
  171. #define SDHCI_CTRL_V4_MODE 0x1000
  172. #define SDHCI_CTRL_64BIT_ADDR 0x2000
  173. #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
  174. #define SDHCI_CAPABILITIES 0x40
  175. #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0)
  176. #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
  177. #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8)
  178. #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8)
  179. #define SDHCI_MAX_BLOCK_MASK 0x00030000
  180. #define SDHCI_MAX_BLOCK_SHIFT 16
  181. #define SDHCI_CAN_DO_8BIT 0x00040000
  182. #define SDHCI_CAN_DO_ADMA2 0x00080000
  183. #define SDHCI_CAN_DO_ADMA1 0x00100000
  184. #define SDHCI_CAN_DO_HISPD 0x00200000
  185. #define SDHCI_CAN_DO_SDMA 0x00400000
  186. #define SDHCI_CAN_DO_SUSPEND 0x00800000
  187. #define SDHCI_CAN_VDD_330 0x01000000
  188. #define SDHCI_CAN_VDD_300 0x02000000
  189. #define SDHCI_CAN_VDD_180 0x04000000
  190. #define SDHCI_CAN_64BIT_V4 0x08000000
  191. #define SDHCI_CAN_64BIT 0x10000000
  192. #define SDHCI_CAPABILITIES_1 0x44
  193. #define SDHCI_SUPPORT_SDR50 0x00000001
  194. #define SDHCI_SUPPORT_SDR104 0x00000002
  195. #define SDHCI_SUPPORT_DDR50 0x00000004
  196. #define SDHCI_DRIVER_TYPE_A 0x00000010
  197. #define SDHCI_DRIVER_TYPE_C 0x00000020
  198. #define SDHCI_DRIVER_TYPE_D 0x00000040
  199. #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8)
  200. #define SDHCI_USE_SDR50_TUNING 0x00002000
  201. #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14)
  202. #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16)
  203. #define SDHCI_CAN_DO_ADMA3 0x08000000
  204. #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
  205. #define SDHCI_MAX_CURRENT 0x48
  206. #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0)
  207. #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)
  208. #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)
  209. #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)
  210. #define SDHCI_MAX_CURRENT_MULTIPLIER 4
  211. /* 4C-4F reserved for more max current */
  212. #define SDHCI_SET_ACMD12_ERROR 0x50
  213. #define SDHCI_SET_INT_ERROR 0x52
  214. #define SDHCI_ADMA_ERROR 0x54
  215. /* 55-57 reserved */
  216. #define SDHCI_ADMA_ADDRESS 0x58
  217. #define SDHCI_ADMA_ADDRESS_HI 0x5C
  218. /* 60-FB reserved */
  219. #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
  220. #define SDHCI_PRESET_FOR_SDR12 0x66
  221. #define SDHCI_PRESET_FOR_SDR25 0x68
  222. #define SDHCI_PRESET_FOR_SDR50 0x6A
  223. #define SDHCI_PRESET_FOR_SDR104 0x6C
  224. #define SDHCI_PRESET_FOR_DDR50 0x6E
  225. #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
  226. #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)
  227. #define SDHCI_PRESET_CLKGEN_SEL BIT(10)
  228. #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
  229. #define SDHCI_SLOT_INT_STATUS 0xFC
  230. #define SDHCI_HOST_VERSION 0xFE
  231. #define SDHCI_VENDOR_VER_MASK 0xFF00
  232. #define SDHCI_VENDOR_VER_SHIFT 8
  233. #define SDHCI_SPEC_VER_MASK 0x00FF
  234. #define SDHCI_SPEC_VER_SHIFT 0
  235. #define SDHCI_SPEC_100 0
  236. #define SDHCI_SPEC_200 1
  237. #define SDHCI_SPEC_300 2
  238. #define SDHCI_SPEC_400 3
  239. #define SDHCI_SPEC_410 4
  240. #define SDHCI_SPEC_420 5
  241. /*
  242. * End of controller registers.
  243. */
  244. #define SDHCI_MAX_DIV_SPEC_200 256
  245. #define SDHCI_MAX_DIV_SPEC_300 2046
  246. /*
  247. * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
  248. */
  249. #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
  250. #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
  251. /* ADMA2 32-bit DMA descriptor size */
  252. #define SDHCI_ADMA2_32_DESC_SZ 8
  253. /* ADMA2 32-bit descriptor */
  254. struct sdhci_adma2_32_desc {
  255. __le16 cmd;
  256. __le16 len;
  257. __le32 addr;
  258. } __packed __aligned(4);
  259. /* ADMA2 data alignment */
  260. #define SDHCI_ADMA2_ALIGN 4
  261. #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
  262. /*
  263. * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
  264. * alignment for the descriptor table even in 32-bit DMA mode. Memory
  265. * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
  266. */
  267. #define SDHCI_ADMA2_DESC_ALIGN 8
  268. /*
  269. * ADMA2 64-bit DMA descriptor size
  270. * According to SD Host Controller spec v4.10, there are two kinds of
  271. * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
  272. * Descriptor, if Host Version 4 Enable is set in the Host Control 2
  273. * register, 128-bit Descriptor will be selected.
  274. */
  275. #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
  276. /*
  277. * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
  278. * aligned.
  279. */
  280. struct sdhci_adma2_64_desc {
  281. __le16 cmd;
  282. __le16 len;
  283. __le32 addr_lo;
  284. __le32 addr_hi;
  285. } __packed __aligned(4);
  286. #define ADMA2_TRAN_VALID 0x21
  287. #define ADMA2_NOP_END_VALID 0x3
  288. #define ADMA2_END 0x2
  289. /*
  290. * Maximum segments assuming a 512KiB maximum requisition size and a minimum
  291. * 4KiB page size.
  292. */
  293. #define SDHCI_MAX_SEGS 128
  294. /* Allow for a a command request and a data request at the same time */
  295. #define SDHCI_MAX_MRQS 2
  296. /*
  297. * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
  298. * However since the start time of the command, the time between
  299. * command and response, and the time between response and start of data is
  300. * not known, set the command transfer time to 10ms.
  301. */
  302. #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */
  303. enum sdhci_cookie {
  304. COOKIE_UNMAPPED,
  305. COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
  306. COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
  307. };
  308. struct sdhci_host {
  309. /* Data set by hardware interface driver */
  310. const char *hw_name; /* Hardware bus name */
  311. unsigned int quirks; /* Deviations from spec. */
  312. /* Controller doesn't honor resets unless we touch the clock register */
  313. #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
  314. /* Controller has bad caps bits, but really supports DMA */
  315. #define SDHCI_QUIRK_FORCE_DMA (1<<1)
  316. /* Controller doesn't like to be reset when there is no card inserted. */
  317. #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
  318. /* Controller doesn't like clearing the power reg before a change */
  319. #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
  320. /* Controller has flaky internal state so reset it on each ios change */
  321. #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
  322. /* Controller has an unusable DMA engine */
  323. #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
  324. /* Controller has an unusable ADMA engine */
  325. #define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
  326. /* Controller can only DMA from 32-bit aligned addresses */
  327. #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
  328. /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
  329. #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
  330. /* Controller can only ADMA chunks that are a multiple of 32 bits */
  331. #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
  332. /* Controller needs to be reset after each request to stay stable */
  333. #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
  334. /* Controller needs voltage and power writes to happen separately */
  335. #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
  336. /* Controller provides an incorrect timeout value for transfers */
  337. #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
  338. /* Controller has an issue with buffer bits for small transfers */
  339. #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
  340. /* Controller does not provide transfer-complete interrupt when not busy */
  341. #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
  342. /* Controller has unreliable card detection */
  343. #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
  344. /* Controller reports inverted write-protect state */
  345. #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
  346. /* Controller has unusable command queue engine */
  347. #define SDHCI_QUIRK_BROKEN_CQE (1<<17)
  348. /* Controller does not like fast PIO transfers */
  349. #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
  350. /* Controller does not have a LED */
  351. #define SDHCI_QUIRK_NO_LED (1<<19)
  352. /* Controller has to be forced to use block size of 2048 bytes */
  353. #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
  354. /* Controller cannot do multi-block transfers */
  355. #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
  356. /* Controller can only handle 1-bit data transfers */
  357. #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
  358. /* Controller needs 10ms delay between applying power and clock */
  359. #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
  360. /* Controller uses SDCLK instead of TMCLK for data timeouts */
  361. #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
  362. /* Controller reports wrong base clock capability */
  363. #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
  364. /* Controller cannot support End Attribute in NOP ADMA descriptor */
  365. #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
  366. /* Controller is missing device caps. Use caps provided by host */
  367. #define SDHCI_QUIRK_MISSING_CAPS (1<<27)
  368. /* Controller uses Auto CMD12 command to stop the transfer */
  369. #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
  370. /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
  371. #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
  372. /* Controller treats ADMA descriptors with length 0000h incorrectly */
  373. #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
  374. /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
  375. #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
  376. unsigned int quirks2; /* More deviations from spec. */
  377. #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
  378. #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
  379. /* The system physically doesn't support 1.8v, even if the host does */
  380. #define SDHCI_QUIRK2_NO_1_8_V (1<<2)
  381. #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
  382. #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
  383. /* Controller has a non-standard host control register */
  384. #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
  385. /* Controller does not support HS200 */
  386. #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
  387. /* Controller does not support DDR50 */
  388. #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
  389. /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
  390. #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
  391. /* Controller does not support 64-bit DMA */
  392. #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
  393. /* need clear transfer mode register before send cmd */
  394. #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
  395. /* Capability register bit-63 indicates HS400 support */
  396. #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
  397. /* forced tuned clock */
  398. #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
  399. /* disable the block count for single block transactions */
  400. #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
  401. /* Controller broken with using ACMD23 */
  402. #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
  403. /* Broken Clock divider zero in controller */
  404. #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
  405. /* Controller has CRC in 136 bit Command Response */
  406. #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
  407. /*
  408. * Disable HW timeout if the requested timeout is more than the maximum
  409. * obtainable timeout.
  410. */
  411. #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
  412. /*
  413. * 32-bit block count may not support eMMC where upper bits of CMD23 are used
  414. * for other purposes. Consequently we support 16-bit block count by default.
  415. * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
  416. * block count.
  417. */
  418. #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
  419. int irq; /* Device IRQ */
  420. void __iomem *ioaddr; /* Mapped address */
  421. phys_addr_t mapbase; /* physical address base */
  422. char *bounce_buffer; /* For packing SDMA reads/writes */
  423. dma_addr_t bounce_addr;
  424. unsigned int bounce_buffer_size;
  425. const struct sdhci_ops *ops; /* Low level hw interface */
  426. /* Internal data */
  427. struct mmc_host *mmc; /* MMC structure */
  428. struct mmc_host_ops mmc_host_ops; /* MMC host ops */
  429. u64 dma_mask; /* custom DMA mask */
  430. #if IS_ENABLED(CONFIG_LEDS_CLASS)
  431. struct led_classdev led; /* LED control */
  432. char led_name[32];
  433. #endif
  434. spinlock_t lock; /* Mutex */
  435. int flags; /* Host attributes */
  436. #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
  437. #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
  438. #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
  439. #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
  440. #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
  441. #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
  442. #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
  443. #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
  444. #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
  445. #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
  446. #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
  447. #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
  448. #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
  449. unsigned int version; /* SDHCI spec. version */
  450. unsigned int max_clk; /* Max possible freq (MHz) */
  451. unsigned int timeout_clk; /* Timeout freq (KHz) */
  452. unsigned int clk_mul; /* Clock Muliplier value */
  453. unsigned int clock; /* Current clock (MHz) */
  454. u8 pwr; /* Current voltage */
  455. bool runtime_suspended; /* Host is runtime suspended */
  456. bool bus_on; /* Bus power prevents runtime suspend */
  457. bool preset_enabled; /* Preset is enabled */
  458. bool pending_reset; /* Cmd/data reset is pending */
  459. bool irq_wake_enabled; /* IRQ wakeup is enabled */
  460. bool v4_mode; /* Host Version 4 Enable */
  461. bool use_external_dma; /* Host selects to use external DMA */
  462. bool always_defer_done; /* Always defer to complete requests */
  463. struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
  464. struct mmc_command *cmd; /* Current command */
  465. struct mmc_command *data_cmd; /* Current data command */
  466. struct mmc_command *deferred_cmd; /* Deferred command */
  467. struct mmc_data *data; /* Current data request */
  468. unsigned int data_early:1; /* Data finished before cmd */
  469. struct sg_mapping_iter sg_miter; /* SG state for PIO */
  470. unsigned int blocks; /* remaining PIO blocks */
  471. int sg_count; /* Mapped sg entries */
  472. void *adma_table; /* ADMA descriptor table */
  473. void *align_buffer; /* Bounce buffer */
  474. size_t adma_table_sz; /* ADMA descriptor table size */
  475. size_t align_buffer_sz; /* Bounce buffer size */
  476. dma_addr_t adma_addr; /* Mapped ADMA descr. table */
  477. dma_addr_t align_addr; /* Mapped bounce buffer */
  478. unsigned int desc_sz; /* ADMA current descriptor size */
  479. unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
  480. struct workqueue_struct *complete_wq; /* Request completion wq */
  481. struct work_struct complete_work; /* Request completion work */
  482. struct timer_list timer; /* Timer for timeouts */
  483. struct timer_list data_timer; /* Timer for data timeouts */
  484. #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
  485. struct dma_chan *rx_chan;
  486. struct dma_chan *tx_chan;
  487. #endif
  488. u32 caps; /* CAPABILITY_0 */
  489. u32 caps1; /* CAPABILITY_1 */
  490. bool read_caps; /* Capability flags have been read */
  491. bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
  492. unsigned int ocr_avail_sdio; /* OCR bit masks */
  493. unsigned int ocr_avail_sd;
  494. unsigned int ocr_avail_mmc;
  495. u32 ocr_mask; /* available voltages */
  496. unsigned timing; /* Current timing */
  497. u32 thread_isr;
  498. /* cached registers */
  499. u32 ier;
  500. bool cqe_on; /* CQE is operating */
  501. u32 cqe_ier; /* CQE interrupt mask */
  502. u32 cqe_err_ier; /* CQE error interrupt mask */
  503. wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
  504. unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
  505. unsigned int tuning_count; /* Timer count for re-tuning */
  506. unsigned int tuning_mode; /* Re-tuning mode supported by host */
  507. unsigned int tuning_err; /* Error code for re-tuning */
  508. #define SDHCI_TUNING_MODE_1 0
  509. #define SDHCI_TUNING_MODE_2 1
  510. #define SDHCI_TUNING_MODE_3 2
  511. /* Delay (ms) between tuning commands */
  512. int tuning_delay;
  513. int tuning_loop_count;
  514. /* Host SDMA buffer boundary. */
  515. u32 sdma_boundary;
  516. /* Host ADMA table count */
  517. u32 adma_table_cnt;
  518. u64 data_timeout;
  519. ANDROID_KABI_RESERVE(1);
  520. unsigned long private[] ____cacheline_aligned;
  521. };
  522. struct sdhci_ops {
  523. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  524. u32 (*read_l)(struct sdhci_host *host, int reg);
  525. u16 (*read_w)(struct sdhci_host *host, int reg);
  526. u8 (*read_b)(struct sdhci_host *host, int reg);
  527. void (*write_l)(struct sdhci_host *host, u32 val, int reg);
  528. void (*write_w)(struct sdhci_host *host, u16 val, int reg);
  529. void (*write_b)(struct sdhci_host *host, u8 val, int reg);
  530. #endif
  531. void (*set_clock)(struct sdhci_host *host, unsigned int clock);
  532. void (*set_power)(struct sdhci_host *host, unsigned char mode,
  533. unsigned short vdd);
  534. u32 (*irq)(struct sdhci_host *host, u32 intmask);
  535. int (*set_dma_mask)(struct sdhci_host *host);
  536. int (*enable_dma)(struct sdhci_host *host);
  537. unsigned int (*get_max_clock)(struct sdhci_host *host);
  538. unsigned int (*get_min_clock)(struct sdhci_host *host);
  539. /* get_timeout_clock should return clk rate in unit of Hz */
  540. unsigned int (*get_timeout_clock)(struct sdhci_host *host);
  541. unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
  542. void (*set_timeout)(struct sdhci_host *host,
  543. struct mmc_command *cmd);
  544. void (*set_bus_width)(struct sdhci_host *host, int width);
  545. void (*platform_send_init_74_clocks)(struct sdhci_host *host,
  546. u8 power_mode);
  547. unsigned int (*get_ro)(struct sdhci_host *host);
  548. void (*reset)(struct sdhci_host *host, u8 mask);
  549. int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
  550. void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
  551. void (*hw_reset)(struct sdhci_host *host);
  552. void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
  553. void (*card_event)(struct sdhci_host *host);
  554. void (*voltage_switch)(struct sdhci_host *host);
  555. void (*adma_write_desc)(struct sdhci_host *host, void **desc,
  556. dma_addr_t addr, int len, unsigned int cmd);
  557. void (*copy_to_bounce_buffer)(struct sdhci_host *host,
  558. struct mmc_data *data,
  559. unsigned int length);
  560. void (*request_done)(struct sdhci_host *host,
  561. struct mmc_request *mrq);
  562. void (*dump_vendor_regs)(struct sdhci_host *host);
  563. ANDROID_KABI_RESERVE(1);
  564. };
  565. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  566. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  567. {
  568. if (unlikely(host->ops->write_l))
  569. host->ops->write_l(host, val, reg);
  570. else
  571. writel(val, host->ioaddr + reg);
  572. }
  573. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  574. {
  575. if (unlikely(host->ops->write_w))
  576. host->ops->write_w(host, val, reg);
  577. else
  578. writew(val, host->ioaddr + reg);
  579. }
  580. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  581. {
  582. if (unlikely(host->ops->write_b))
  583. host->ops->write_b(host, val, reg);
  584. else
  585. writeb(val, host->ioaddr + reg);
  586. }
  587. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  588. {
  589. if (unlikely(host->ops->read_l))
  590. return host->ops->read_l(host, reg);
  591. else
  592. return readl(host->ioaddr + reg);
  593. }
  594. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  595. {
  596. if (unlikely(host->ops->read_w))
  597. return host->ops->read_w(host, reg);
  598. else
  599. return readw(host->ioaddr + reg);
  600. }
  601. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  602. {
  603. if (unlikely(host->ops->read_b))
  604. return host->ops->read_b(host, reg);
  605. else
  606. return readb(host->ioaddr + reg);
  607. }
  608. #else
  609. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  610. {
  611. writel(val, host->ioaddr + reg);
  612. }
  613. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  614. {
  615. writew(val, host->ioaddr + reg);
  616. }
  617. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  618. {
  619. writeb(val, host->ioaddr + reg);
  620. }
  621. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  622. {
  623. return readl(host->ioaddr + reg);
  624. }
  625. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  626. {
  627. return readw(host->ioaddr + reg);
  628. }
  629. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  630. {
  631. return readb(host->ioaddr + reg);
  632. }
  633. #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
  634. struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
  635. void sdhci_free_host(struct sdhci_host *host);
  636. static inline void *sdhci_priv(struct sdhci_host *host)
  637. {
  638. return host->private;
  639. }
  640. void sdhci_card_detect(struct sdhci_host *host);
  641. void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
  642. const u32 *caps, const u32 *caps1);
  643. int sdhci_setup_host(struct sdhci_host *host);
  644. void sdhci_cleanup_host(struct sdhci_host *host);
  645. int __sdhci_add_host(struct sdhci_host *host);
  646. int sdhci_add_host(struct sdhci_host *host);
  647. void sdhci_remove_host(struct sdhci_host *host, int dead);
  648. static inline void sdhci_read_caps(struct sdhci_host *host)
  649. {
  650. __sdhci_read_caps(host, NULL, NULL, NULL);
  651. }
  652. u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
  653. unsigned int *actual_clock);
  654. void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
  655. void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
  656. void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
  657. unsigned short vdd);
  658. void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
  659. unsigned char mode,
  660. unsigned short vdd);
  661. void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
  662. unsigned short vdd);
  663. void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
  664. int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
  665. void sdhci_set_bus_width(struct sdhci_host *host, int width);
  666. void sdhci_reset(struct sdhci_host *host, u8 mask);
  667. void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
  668. int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  669. void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
  670. int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
  671. struct mmc_ios *ios);
  672. void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
  673. void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
  674. dma_addr_t addr, int len, unsigned int cmd);
  675. #ifdef CONFIG_PM
  676. int sdhci_suspend_host(struct sdhci_host *host);
  677. int sdhci_resume_host(struct sdhci_host *host);
  678. int sdhci_runtime_suspend_host(struct sdhci_host *host);
  679. int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
  680. #endif
  681. void sdhci_cqe_enable(struct mmc_host *mmc);
  682. void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
  683. bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
  684. int *data_error);
  685. void sdhci_dumpregs(struct sdhci_host *host);
  686. void sdhci_enable_v4_mode(struct sdhci_host *host);
  687. void sdhci_start_tuning(struct sdhci_host *host);
  688. void sdhci_end_tuning(struct sdhci_host *host);
  689. void sdhci_reset_tuning(struct sdhci_host *host);
  690. void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
  691. void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
  692. void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
  693. void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
  694. void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
  695. #endif /* __SDHCI_HW_H */