sdhci-xenon.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2016 Marvell, All Rights Reserved.
  4. *
  5. * Author: Hu Ziji <huziji@marvell.com>
  6. * Date: 2016-8-24
  7. */
  8. #ifndef SDHCI_XENON_H_
  9. #define SDHCI_XENON_H_
  10. /* Register Offset of Xenon SDHC self-defined register */
  11. #define XENON_SYS_CFG_INFO 0x0104
  12. #define XENON_SLOT_TYPE_SDIO_SHIFT 24
  13. #define XENON_NR_SUPPORTED_SLOT_MASK 0x7
  14. #define XENON_SYS_OP_CTRL 0x0108
  15. #define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)
  16. #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
  17. #define XENON_SLOT_ENABLE_SHIFT 0
  18. #define XENON_SYS_EXT_OP_CTRL 0x010C
  19. #define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
  20. #define XENON_SLOT_OP_STATUS_CTRL 0x0128
  21. #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16
  22. #define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7
  23. #define XENON_TUN_CONSECUTIVE_TIMES 0x4
  24. #define XENON_TUNING_STEP_SHIFT 12
  25. #define XENON_TUNING_STEP_MASK 0xF
  26. #define XENON_TUNING_STEP_DIVIDER BIT(6)
  27. #define XENON_SLOT_EMMC_CTRL 0x0130
  28. #define XENON_ENABLE_RESP_STROBE BIT(25)
  29. #define XENON_ENABLE_DATA_STROBE BIT(24)
  30. #define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
  31. /* retuning compatible */
  32. #define XENON_RETUNING_COMPATIBLE 0x1
  33. #define XENON_SLOT_EXT_PRESENT_STATE 0x014C
  34. #define XENON_DLL_LOCK_STATE 0x1
  35. #define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150
  36. /* Tuning Parameter */
  37. #define XENON_TMR_RETUN_NO_PRESENT 0xF
  38. #define XENON_DEF_TUNING_COUNT 0x9
  39. #define XENON_DEFAULT_SDCLK_FREQ 400000
  40. #define XENON_LOWEST_SDCLK_FREQ 100000
  41. /* Xenon specific Mode Select value */
  42. #define XENON_CTRL_HS200 0x5
  43. #define XENON_CTRL_HS400 0x6
  44. struct xenon_priv {
  45. unsigned char tuning_count;
  46. /* idx of SDHC */
  47. u8 sdhc_id;
  48. /*
  49. * eMMC/SD/SDIO require different register settings.
  50. * Xenon driver has to recognize card type
  51. * before mmc_host->card is not available.
  52. * This field records the card type during init.
  53. * It is updated in xenon_init_card().
  54. *
  55. * It is only valid during initialization after it is updated.
  56. * Do not access this variable in normal transfers after
  57. * initialization completes.
  58. */
  59. unsigned int init_card_type;
  60. /*
  61. * The bus_width, timing, and clock fields in below
  62. * record the current ios setting of Xenon SDHC.
  63. * Driver will adjust PHY setting if any change to
  64. * ios affects PHY timing.
  65. */
  66. unsigned char bus_width;
  67. unsigned char timing;
  68. unsigned int clock;
  69. struct clk *axi_clk;
  70. int phy_type;
  71. /*
  72. * Contains board-specific PHY parameters
  73. * passed from device tree.
  74. */
  75. void *phy_params;
  76. struct xenon_emmc_phy_regs *emmc_phy_regs;
  77. bool restore_needed;
  78. };
  79. int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
  80. int xenon_phy_parse_dt(struct device_node *np,
  81. struct sdhci_host *host);
  82. void xenon_soc_pad_ctrl(struct sdhci_host *host,
  83. unsigned char signal_voltage);
  84. #endif