sdhci-xenon.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Marvell Xenon SDHC as a platform device
  4. *
  5. * Copyright (C) 2016 Marvell, All Rights Reserved.
  6. *
  7. * Author: Hu Ziji <huziji@marvell.com>
  8. * Date: 2016-8-24
  9. *
  10. * Inspired by Jisheng Zhang <jszhang@marvell.com>
  11. * Special thanks to Video BG4 project team.
  12. */
  13. #include <linux/delay.h>
  14. #include <linux/ktime.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/pm.h>
  18. #include <linux/pm_runtime.h>
  19. #include "sdhci-pltfm.h"
  20. #include "sdhci-xenon.h"
  21. static int xenon_enable_internal_clk(struct sdhci_host *host)
  22. {
  23. u32 reg;
  24. ktime_t timeout;
  25. reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  26. reg |= SDHCI_CLOCK_INT_EN;
  27. sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
  28. /* Wait max 20 ms */
  29. timeout = ktime_add_ms(ktime_get(), 20);
  30. while (1) {
  31. bool timedout = ktime_after(ktime_get(), timeout);
  32. reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  33. if (reg & SDHCI_CLOCK_INT_STABLE)
  34. break;
  35. if (timedout) {
  36. dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
  37. return -ETIMEDOUT;
  38. }
  39. usleep_range(900, 1100);
  40. }
  41. return 0;
  42. }
  43. /* Set SDCLK-off-while-idle */
  44. static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
  45. unsigned char sdhc_id, bool enable)
  46. {
  47. u32 reg;
  48. u32 mask;
  49. reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  50. /* Get the bit shift basing on the SDHC index */
  51. mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
  52. if (enable)
  53. reg |= mask;
  54. else
  55. reg &= ~mask;
  56. sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  57. }
  58. /* Enable/Disable the Auto Clock Gating function */
  59. static void xenon_set_acg(struct sdhci_host *host, bool enable)
  60. {
  61. u32 reg;
  62. reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  63. if (enable)
  64. reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
  65. else
  66. reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
  67. sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  68. }
  69. /* Enable this SDHC */
  70. static void xenon_enable_sdhc(struct sdhci_host *host,
  71. unsigned char sdhc_id)
  72. {
  73. u32 reg;
  74. reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  75. reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
  76. sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  77. host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  78. /*
  79. * Force to clear BUS_TEST to
  80. * skip bus_test_pre and bus_test_post
  81. */
  82. host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
  83. }
  84. /* Disable this SDHC */
  85. static void xenon_disable_sdhc(struct sdhci_host *host,
  86. unsigned char sdhc_id)
  87. {
  88. u32 reg;
  89. reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  90. reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
  91. sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  92. }
  93. /* Enable Parallel Transfer Mode */
  94. static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
  95. unsigned char sdhc_id)
  96. {
  97. u32 reg;
  98. reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
  99. reg |= BIT(sdhc_id);
  100. sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
  101. }
  102. /* Mask command conflict error */
  103. static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
  104. {
  105. u32 reg;
  106. reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
  107. reg |= XENON_MASK_CMD_CONFLICT_ERR;
  108. sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
  109. }
  110. static void xenon_retune_setup(struct sdhci_host *host)
  111. {
  112. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  113. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  114. u32 reg;
  115. /* Disable the Re-Tuning Request functionality */
  116. reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
  117. reg &= ~XENON_RETUNING_COMPATIBLE;
  118. sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
  119. /* Disable the Re-tuning Interrupt */
  120. reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
  121. reg &= ~SDHCI_INT_RETUNE;
  122. sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
  123. reg = sdhci_readl(host, SDHCI_INT_ENABLE);
  124. reg &= ~SDHCI_INT_RETUNE;
  125. sdhci_writel(host, reg, SDHCI_INT_ENABLE);
  126. /* Force to use Tuning Mode 1 */
  127. host->tuning_mode = SDHCI_TUNING_MODE_1;
  128. /* Set re-tuning period */
  129. host->tuning_count = 1 << (priv->tuning_count - 1);
  130. }
  131. /*
  132. * Operations inside struct sdhci_ops
  133. */
  134. /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
  135. static void xenon_reset_exit(struct sdhci_host *host,
  136. unsigned char sdhc_id, u8 mask)
  137. {
  138. /* Only SOFTWARE RESET ALL will clear the register setting */
  139. if (!(mask & SDHCI_RESET_ALL))
  140. return;
  141. /* Disable tuning request and auto-retuning again */
  142. xenon_retune_setup(host);
  143. /*
  144. * The ACG should be turned off at the early init time, in order
  145. * to solve a possible issues with the 1.8V regulator stabilization.
  146. * The feature is enabled in later stage.
  147. */
  148. xenon_set_acg(host, false);
  149. xenon_set_sdclk_off_idle(host, sdhc_id, false);
  150. xenon_mask_cmd_conflict_err(host);
  151. }
  152. static void xenon_reset(struct sdhci_host *host, u8 mask)
  153. {
  154. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  155. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  156. sdhci_reset(host, mask);
  157. xenon_reset_exit(host, priv->sdhc_id, mask);
  158. }
  159. /*
  160. * Xenon defines different values for HS200 and HS400
  161. * in Host_Control_2
  162. */
  163. static void xenon_set_uhs_signaling(struct sdhci_host *host,
  164. unsigned int timing)
  165. {
  166. u16 ctrl_2;
  167. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  168. /* Select Bus Speed Mode for host */
  169. ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
  170. if (timing == MMC_TIMING_MMC_HS200)
  171. ctrl_2 |= XENON_CTRL_HS200;
  172. else if (timing == MMC_TIMING_UHS_SDR104)
  173. ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
  174. else if (timing == MMC_TIMING_UHS_SDR12)
  175. ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
  176. else if (timing == MMC_TIMING_UHS_SDR25)
  177. ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
  178. else if (timing == MMC_TIMING_UHS_SDR50)
  179. ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
  180. else if ((timing == MMC_TIMING_UHS_DDR50) ||
  181. (timing == MMC_TIMING_MMC_DDR52))
  182. ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
  183. else if (timing == MMC_TIMING_MMC_HS400)
  184. ctrl_2 |= XENON_CTRL_HS400;
  185. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  186. }
  187. static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
  188. unsigned short vdd)
  189. {
  190. struct mmc_host *mmc = host->mmc;
  191. u8 pwr = host->pwr;
  192. sdhci_set_power_noreg(host, mode, vdd);
  193. if (host->pwr == pwr)
  194. return;
  195. if (host->pwr == 0)
  196. vdd = 0;
  197. if (!IS_ERR(mmc->supply.vmmc))
  198. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
  199. }
  200. static void xenon_voltage_switch(struct sdhci_host *host)
  201. {
  202. /* Wait for 5ms after set 1.8V signal enable bit */
  203. usleep_range(5000, 5500);
  204. }
  205. static const struct sdhci_ops sdhci_xenon_ops = {
  206. .voltage_switch = xenon_voltage_switch,
  207. .set_clock = sdhci_set_clock,
  208. .set_power = xenon_set_power,
  209. .set_bus_width = sdhci_set_bus_width,
  210. .reset = xenon_reset,
  211. .set_uhs_signaling = xenon_set_uhs_signaling,
  212. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  213. };
  214. static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
  215. .ops = &sdhci_xenon_ops,
  216. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  217. SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
  218. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  219. };
  220. /*
  221. * Xenon Specific Operations in mmc_host_ops
  222. */
  223. static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  224. {
  225. struct sdhci_host *host = mmc_priv(mmc);
  226. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  227. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  228. u32 reg;
  229. /*
  230. * HS400/HS200/eMMC HS doesn't have Preset Value register.
  231. * However, sdhci_set_ios will read HS400/HS200 Preset register.
  232. * Disable Preset Value register for HS400/HS200.
  233. * eMMC HS with preset_enabled set will trigger a bug in
  234. * get_preset_value().
  235. */
  236. if ((ios->timing == MMC_TIMING_MMC_HS400) ||
  237. (ios->timing == MMC_TIMING_MMC_HS200) ||
  238. (ios->timing == MMC_TIMING_MMC_HS)) {
  239. host->preset_enabled = false;
  240. host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
  241. host->flags &= ~SDHCI_PV_ENABLED;
  242. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  243. reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
  244. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  245. } else {
  246. host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
  247. }
  248. sdhci_set_ios(mmc, ios);
  249. xenon_phy_adj(host, ios);
  250. if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
  251. xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
  252. }
  253. static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
  254. struct mmc_ios *ios)
  255. {
  256. struct sdhci_host *host = mmc_priv(mmc);
  257. /*
  258. * Before SD/SDIO set signal voltage, SD bus clock should be
  259. * disabled. However, sdhci_set_clock will also disable the Internal
  260. * clock in mmc_set_signal_voltage().
  261. * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
  262. * Thus here manually enable internal clock.
  263. *
  264. * After switch completes, it is unnecessary to disable internal clock,
  265. * since keeping internal clock active obeys SD spec.
  266. */
  267. xenon_enable_internal_clk(host);
  268. xenon_soc_pad_ctrl(host, ios->signal_voltage);
  269. /*
  270. * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
  271. * Thus SDHCI_CTRL_VDD_180 bit might not work then.
  272. * Skip the standard voltage switch to avoid any issue.
  273. */
  274. if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
  275. return 0;
  276. return sdhci_start_signal_voltage_switch(mmc, ios);
  277. }
  278. /*
  279. * Update card type.
  280. * priv->init_card_type will be used in PHY timing adjustment.
  281. */
  282. static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
  283. {
  284. struct sdhci_host *host = mmc_priv(mmc);
  285. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  286. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  287. /* Update card type*/
  288. priv->init_card_type = card->type;
  289. }
  290. static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
  291. {
  292. struct sdhci_host *host = mmc_priv(mmc);
  293. if (host->timing == MMC_TIMING_UHS_DDR50 ||
  294. host->timing == MMC_TIMING_MMC_DDR52)
  295. return 0;
  296. /*
  297. * Currently force Xenon driver back to support mode 1 only,
  298. * even though Xenon might claim to support mode 2 or mode 3.
  299. * It requires more time to test mode 2/mode 3 on more platforms.
  300. */
  301. if (host->tuning_mode != SDHCI_TUNING_MODE_1)
  302. xenon_retune_setup(host);
  303. return sdhci_execute_tuning(mmc, opcode);
  304. }
  305. static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
  306. {
  307. struct sdhci_host *host = mmc_priv(mmc);
  308. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  309. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  310. u32 reg;
  311. u8 sdhc_id = priv->sdhc_id;
  312. sdhci_enable_sdio_irq(mmc, enable);
  313. if (enable) {
  314. /*
  315. * Set SDIO Card Inserted indication
  316. * to enable detecting SDIO async irq.
  317. */
  318. reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
  319. reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
  320. sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
  321. } else {
  322. /* Clear SDIO Card Inserted indication */
  323. reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
  324. reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
  325. sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
  326. }
  327. }
  328. static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
  329. {
  330. host->mmc_host_ops.set_ios = xenon_set_ios;
  331. host->mmc_host_ops.start_signal_voltage_switch =
  332. xenon_start_signal_voltage_switch;
  333. host->mmc_host_ops.init_card = xenon_init_card;
  334. host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
  335. host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
  336. }
  337. /*
  338. * Parse Xenon specific DT properties:
  339. * sdhc-id: the index of current SDHC.
  340. * Refer to XENON_SYS_CFG_INFO register
  341. * tun-count: the interval between re-tuning
  342. */
  343. static int xenon_probe_dt(struct platform_device *pdev)
  344. {
  345. struct device_node *np = pdev->dev.of_node;
  346. struct sdhci_host *host = platform_get_drvdata(pdev);
  347. struct mmc_host *mmc = host->mmc;
  348. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  349. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  350. u32 sdhc_id, nr_sdhc;
  351. u32 tuning_count;
  352. /* Disable HS200 on Armada AP806 */
  353. if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
  354. host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
  355. sdhc_id = 0x0;
  356. if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
  357. nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
  358. nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
  359. if (unlikely(sdhc_id > nr_sdhc)) {
  360. dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
  361. sdhc_id, nr_sdhc);
  362. return -EINVAL;
  363. }
  364. }
  365. priv->sdhc_id = sdhc_id;
  366. tuning_count = XENON_DEF_TUNING_COUNT;
  367. if (!of_property_read_u32(np, "marvell,xenon-tun-count",
  368. &tuning_count)) {
  369. if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
  370. dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
  371. XENON_DEF_TUNING_COUNT);
  372. tuning_count = XENON_DEF_TUNING_COUNT;
  373. }
  374. }
  375. priv->tuning_count = tuning_count;
  376. return xenon_phy_parse_dt(np, host);
  377. }
  378. static int xenon_sdhc_prepare(struct sdhci_host *host)
  379. {
  380. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  381. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  382. u8 sdhc_id = priv->sdhc_id;
  383. /* Enable SDHC */
  384. xenon_enable_sdhc(host, sdhc_id);
  385. /* Enable ACG */
  386. xenon_set_acg(host, true);
  387. /* Enable Parallel Transfer Mode */
  388. xenon_enable_sdhc_parallel_tran(host, sdhc_id);
  389. /* Disable SDCLK-Off-While-Idle before card init */
  390. xenon_set_sdclk_off_idle(host, sdhc_id, false);
  391. xenon_mask_cmd_conflict_err(host);
  392. return 0;
  393. }
  394. static void xenon_sdhc_unprepare(struct sdhci_host *host)
  395. {
  396. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  397. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  398. u8 sdhc_id = priv->sdhc_id;
  399. /* disable SDHC */
  400. xenon_disable_sdhc(host, sdhc_id);
  401. }
  402. static int xenon_probe(struct platform_device *pdev)
  403. {
  404. struct sdhci_pltfm_host *pltfm_host;
  405. struct sdhci_host *host;
  406. struct xenon_priv *priv;
  407. int err;
  408. host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
  409. sizeof(struct xenon_priv));
  410. if (IS_ERR(host))
  411. return PTR_ERR(host);
  412. pltfm_host = sdhci_priv(host);
  413. priv = sdhci_pltfm_priv(pltfm_host);
  414. /*
  415. * Link Xenon specific mmc_host_ops function,
  416. * to replace standard ones in sdhci_ops.
  417. */
  418. xenon_replace_mmc_host_ops(host);
  419. pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
  420. if (IS_ERR(pltfm_host->clk)) {
  421. err = PTR_ERR(pltfm_host->clk);
  422. dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
  423. goto free_pltfm;
  424. }
  425. err = clk_prepare_enable(pltfm_host->clk);
  426. if (err)
  427. goto free_pltfm;
  428. priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
  429. if (IS_ERR(priv->axi_clk)) {
  430. err = PTR_ERR(priv->axi_clk);
  431. if (err == -EPROBE_DEFER)
  432. goto err_clk;
  433. } else {
  434. err = clk_prepare_enable(priv->axi_clk);
  435. if (err)
  436. goto err_clk;
  437. }
  438. err = mmc_of_parse(host->mmc);
  439. if (err)
  440. goto err_clk_axi;
  441. sdhci_get_of_property(pdev);
  442. xenon_set_acg(host, false);
  443. /* Xenon specific dt parse */
  444. err = xenon_probe_dt(pdev);
  445. if (err)
  446. goto err_clk_axi;
  447. err = xenon_sdhc_prepare(host);
  448. if (err)
  449. goto err_clk_axi;
  450. pm_runtime_get_noresume(&pdev->dev);
  451. pm_runtime_set_active(&pdev->dev);
  452. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  453. pm_runtime_use_autosuspend(&pdev->dev);
  454. pm_runtime_enable(&pdev->dev);
  455. pm_suspend_ignore_children(&pdev->dev, 1);
  456. err = sdhci_add_host(host);
  457. if (err)
  458. goto remove_sdhc;
  459. pm_runtime_put_autosuspend(&pdev->dev);
  460. return 0;
  461. remove_sdhc:
  462. pm_runtime_disable(&pdev->dev);
  463. pm_runtime_put_noidle(&pdev->dev);
  464. xenon_sdhc_unprepare(host);
  465. err_clk_axi:
  466. clk_disable_unprepare(priv->axi_clk);
  467. err_clk:
  468. clk_disable_unprepare(pltfm_host->clk);
  469. free_pltfm:
  470. sdhci_pltfm_free(pdev);
  471. return err;
  472. }
  473. static int xenon_remove(struct platform_device *pdev)
  474. {
  475. struct sdhci_host *host = platform_get_drvdata(pdev);
  476. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  477. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  478. pm_runtime_get_sync(&pdev->dev);
  479. pm_runtime_disable(&pdev->dev);
  480. pm_runtime_put_noidle(&pdev->dev);
  481. sdhci_remove_host(host, 0);
  482. xenon_sdhc_unprepare(host);
  483. clk_disable_unprepare(priv->axi_clk);
  484. clk_disable_unprepare(pltfm_host->clk);
  485. sdhci_pltfm_free(pdev);
  486. return 0;
  487. }
  488. #ifdef CONFIG_PM_SLEEP
  489. static int xenon_suspend(struct device *dev)
  490. {
  491. struct sdhci_host *host = dev_get_drvdata(dev);
  492. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  493. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  494. int ret;
  495. ret = pm_runtime_force_suspend(dev);
  496. priv->restore_needed = true;
  497. return ret;
  498. }
  499. #endif
  500. #ifdef CONFIG_PM
  501. static int xenon_runtime_suspend(struct device *dev)
  502. {
  503. struct sdhci_host *host = dev_get_drvdata(dev);
  504. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  505. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  506. int ret;
  507. ret = sdhci_runtime_suspend_host(host);
  508. if (ret)
  509. return ret;
  510. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  511. mmc_retune_needed(host->mmc);
  512. clk_disable_unprepare(pltfm_host->clk);
  513. /*
  514. * Need to update the priv->clock here, or when runtime resume
  515. * back, phy don't aware the clock change and won't adjust phy
  516. * which will cause cmd err
  517. */
  518. priv->clock = 0;
  519. return 0;
  520. }
  521. static int xenon_runtime_resume(struct device *dev)
  522. {
  523. struct sdhci_host *host = dev_get_drvdata(dev);
  524. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  525. struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
  526. int ret;
  527. ret = clk_prepare_enable(pltfm_host->clk);
  528. if (ret) {
  529. dev_err(dev, "can't enable mainck\n");
  530. return ret;
  531. }
  532. if (priv->restore_needed) {
  533. ret = xenon_sdhc_prepare(host);
  534. if (ret)
  535. goto out;
  536. priv->restore_needed = false;
  537. }
  538. ret = sdhci_runtime_resume_host(host, 0);
  539. if (ret)
  540. goto out;
  541. return 0;
  542. out:
  543. clk_disable_unprepare(pltfm_host->clk);
  544. return ret;
  545. }
  546. #endif /* CONFIG_PM */
  547. static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
  548. SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
  549. pm_runtime_force_resume)
  550. SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
  551. xenon_runtime_resume,
  552. NULL)
  553. };
  554. static const struct of_device_id sdhci_xenon_dt_ids[] = {
  555. { .compatible = "marvell,armada-ap806-sdhci",},
  556. { .compatible = "marvell,armada-cp110-sdhci",},
  557. { .compatible = "marvell,armada-3700-sdhci",},
  558. {}
  559. };
  560. MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
  561. static struct platform_driver sdhci_xenon_driver = {
  562. .driver = {
  563. .name = "xenon-sdhci",
  564. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  565. .of_match_table = sdhci_xenon_dt_ids,
  566. .pm = &sdhci_xenon_dev_pm_ops,
  567. },
  568. .probe = xenon_probe,
  569. .remove = xenon_remove,
  570. };
  571. module_platform_driver(sdhci_xenon_driver);
  572. MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
  573. MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
  574. MODULE_LICENSE("GPL v2");