sdhci-tegra.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010 Google, Inc.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/err.h>
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/clk.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/reset.h>
  19. #include <linux/mmc/card.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/mmc/mmc.h>
  22. #include <linux/mmc/slot-gpio.h>
  23. #include <linux/gpio/consumer.h>
  24. #include <linux/ktime.h>
  25. #include "sdhci-pltfm.h"
  26. #include "cqhci.h"
  27. /* Tegra SDHOST controller vendor register definitions */
  28. #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
  29. #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
  30. #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
  31. #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000
  32. #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24
  33. #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
  34. #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
  35. #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
  36. #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104
  37. #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31)
  38. #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c
  39. #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00
  40. #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8
  41. #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
  42. #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0)
  43. #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
  44. #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
  45. #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
  46. #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
  47. #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0
  48. #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31)
  49. #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc
  50. #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31)
  51. #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0
  52. #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000
  53. #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000
  54. #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18
  55. #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0
  56. #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6
  57. #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000
  58. #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13
  59. #define TRIES_128 2
  60. #define TRIES_256 4
  61. #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7
  62. #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4
  63. #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8
  64. #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC
  65. #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF
  66. #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8
  67. #define TUNING_WORD_BIT_SIZE 32
  68. #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
  69. #define SDHCI_AUTO_CAL_START BIT(31)
  70. #define SDHCI_AUTO_CAL_ENABLE BIT(29)
  71. #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff
  72. #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0
  73. #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f
  74. #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7
  75. #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31)
  76. #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000
  77. #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
  78. #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
  79. #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
  80. #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
  81. #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
  82. #define NVQUIRK_ENABLE_SDR50 BIT(3)
  83. #define NVQUIRK_ENABLE_SDR104 BIT(4)
  84. #define NVQUIRK_ENABLE_DDR50 BIT(5)
  85. /*
  86. * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads
  87. * drive strength.
  88. */
  89. #define NVQUIRK_HAS_PADCALIB BIT(6)
  90. /*
  91. * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
  92. * 3V3/1V8 pad selection happens through pinctrl state selection depending
  93. * on the signaling mode.
  94. */
  95. #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7)
  96. #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8)
  97. #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9)
  98. /*
  99. * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
  100. * SDMMC hardware data timeout.
  101. */
  102. #define NVQUIRK_HAS_TMCLK BIT(10)
  103. /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
  104. #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
  105. #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
  106. SDHCI_TRNS_BLK_CNT_EN | \
  107. SDHCI_TRNS_DMA)
  108. struct sdhci_tegra_soc_data {
  109. const struct sdhci_pltfm_data *pdata;
  110. u64 dma_mask;
  111. u32 nvquirks;
  112. u8 min_tap_delay;
  113. u8 max_tap_delay;
  114. };
  115. /* Magic pull up and pull down pad calibration offsets */
  116. struct sdhci_tegra_autocal_offsets {
  117. u32 pull_up_3v3;
  118. u32 pull_down_3v3;
  119. u32 pull_up_3v3_timeout;
  120. u32 pull_down_3v3_timeout;
  121. u32 pull_up_1v8;
  122. u32 pull_down_1v8;
  123. u32 pull_up_1v8_timeout;
  124. u32 pull_down_1v8_timeout;
  125. u32 pull_up_sdr104;
  126. u32 pull_down_sdr104;
  127. u32 pull_up_hs400;
  128. u32 pull_down_hs400;
  129. };
  130. struct sdhci_tegra {
  131. const struct sdhci_tegra_soc_data *soc_data;
  132. struct gpio_desc *power_gpio;
  133. struct clk *tmclk;
  134. bool ddr_signaling;
  135. bool pad_calib_required;
  136. bool pad_control_available;
  137. struct reset_control *rst;
  138. struct pinctrl *pinctrl_sdmmc;
  139. struct pinctrl_state *pinctrl_state_3v3;
  140. struct pinctrl_state *pinctrl_state_1v8;
  141. struct pinctrl_state *pinctrl_state_3v3_drv;
  142. struct pinctrl_state *pinctrl_state_1v8_drv;
  143. struct sdhci_tegra_autocal_offsets autocal_offsets;
  144. ktime_t last_calib;
  145. u32 default_tap;
  146. u32 default_trim;
  147. u32 dqs_trim;
  148. bool enable_hwcq;
  149. unsigned long curr_clk_rate;
  150. u8 tuned_tap_delay;
  151. };
  152. static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  153. {
  154. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  155. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  156. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  157. if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  158. (reg == SDHCI_HOST_VERSION))) {
  159. /* Erratum: Version register is invalid in HW. */
  160. return SDHCI_SPEC_200;
  161. }
  162. return readw(host->ioaddr + reg);
  163. }
  164. static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  165. {
  166. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  167. switch (reg) {
  168. case SDHCI_TRANSFER_MODE:
  169. /*
  170. * Postpone this write, we must do it together with a
  171. * command write that is down below.
  172. */
  173. pltfm_host->xfer_mode_shadow = val;
  174. return;
  175. case SDHCI_COMMAND:
  176. writel((val << 16) | pltfm_host->xfer_mode_shadow,
  177. host->ioaddr + SDHCI_TRANSFER_MODE);
  178. return;
  179. }
  180. writew(val, host->ioaddr + reg);
  181. }
  182. static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  183. {
  184. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  185. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  186. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  187. /* Seems like we're getting spurious timeout and crc errors, so
  188. * disable signalling of them. In case of real errors software
  189. * timers should take care of eventually detecting them.
  190. */
  191. if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  192. val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  193. writel(val, host->ioaddr + reg);
  194. if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
  195. (reg == SDHCI_INT_ENABLE))) {
  196. /* Erratum: Must enable block gap interrupt detection */
  197. u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  198. if (val & SDHCI_INT_CARD_INT)
  199. gap_ctrl |= 0x8;
  200. else
  201. gap_ctrl &= ~0x8;
  202. writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  203. }
  204. }
  205. static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
  206. {
  207. bool status;
  208. u32 reg;
  209. reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  210. status = !!(reg & SDHCI_CLOCK_CARD_EN);
  211. if (status == enable)
  212. return status;
  213. if (enable)
  214. reg |= SDHCI_CLOCK_CARD_EN;
  215. else
  216. reg &= ~SDHCI_CLOCK_CARD_EN;
  217. sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
  218. return status;
  219. }
  220. static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  221. {
  222. bool is_tuning_cmd = 0;
  223. bool clk_enabled;
  224. u8 cmd;
  225. if (reg == SDHCI_COMMAND) {
  226. cmd = SDHCI_GET_CMD(val);
  227. is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK ||
  228. cmd == MMC_SEND_TUNING_BLOCK_HS200;
  229. }
  230. if (is_tuning_cmd)
  231. clk_enabled = tegra_sdhci_configure_card_clk(host, 0);
  232. writew(val, host->ioaddr + reg);
  233. if (is_tuning_cmd) {
  234. udelay(1);
  235. sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
  236. tegra_sdhci_configure_card_clk(host, clk_enabled);
  237. }
  238. }
  239. static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
  240. {
  241. /*
  242. * Write-enable shall be assumed if GPIO is missing in a board's
  243. * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
  244. * Tegra.
  245. */
  246. return mmc_gpio_get_ro(host->mmc);
  247. }
  248. static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
  249. {
  250. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  251. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  252. int has_1v8, has_3v3;
  253. /*
  254. * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
  255. * voltage configuration in order to perform voltage switching. This
  256. * means that valid pinctrl info is required on SDHCI instances capable
  257. * of performing voltage switching. Whether or not an SDHCI instance is
  258. * capable of voltage switching is determined based on the regulator.
  259. */
  260. if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
  261. return true;
  262. if (IS_ERR(host->mmc->supply.vqmmc))
  263. return false;
  264. has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
  265. 1700000, 1950000);
  266. has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
  267. 2700000, 3600000);
  268. if (has_1v8 == 1 && has_3v3 == 1)
  269. return tegra_host->pad_control_available;
  270. /* Fixed voltage, no pad control required. */
  271. return true;
  272. }
  273. static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
  274. {
  275. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  276. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  277. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  278. bool card_clk_enabled = false;
  279. u32 reg;
  280. /*
  281. * Touching the tap values is a bit tricky on some SoC generations.
  282. * The quirk enables a workaround for a glitch that sometimes occurs if
  283. * the tap values are changed.
  284. */
  285. if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
  286. card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
  287. reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  288. reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
  289. reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
  290. sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  291. if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
  292. card_clk_enabled) {
  293. udelay(1);
  294. sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
  295. tegra_sdhci_configure_card_clk(host, card_clk_enabled);
  296. }
  297. }
  298. static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
  299. {
  300. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  301. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  302. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  303. u32 misc_ctrl, clk_ctrl, pad_ctrl;
  304. sdhci_reset(host, mask);
  305. if (!(mask & SDHCI_RESET_ALL))
  306. return;
  307. tegra_sdhci_set_tap(host, tegra_host->default_tap);
  308. misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  309. clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  310. misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
  311. SDHCI_MISC_CTRL_ENABLE_SDR50 |
  312. SDHCI_MISC_CTRL_ENABLE_DDR50 |
  313. SDHCI_MISC_CTRL_ENABLE_SDR104);
  314. clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
  315. SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
  316. if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
  317. /* Erratum: Enable SDHCI spec v3.00 support */
  318. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
  319. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
  320. /* Advertise UHS modes as supported by host */
  321. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
  322. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
  323. if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
  324. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
  325. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
  326. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
  327. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
  328. clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
  329. }
  330. clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
  331. sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  332. sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  333. if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
  334. pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
  335. pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
  336. pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
  337. sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
  338. tegra_host->pad_calib_required = true;
  339. }
  340. tegra_host->ddr_signaling = false;
  341. }
  342. static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
  343. {
  344. u32 val;
  345. /*
  346. * Enable or disable the additional I/O pad used by the drive strength
  347. * calibration process.
  348. */
  349. val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
  350. if (enable)
  351. val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
  352. else
  353. val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
  354. sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
  355. if (enable)
  356. usleep_range(1, 2);
  357. }
  358. static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
  359. u16 pdpu)
  360. {
  361. u32 reg;
  362. reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  363. reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
  364. reg |= pdpu;
  365. sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  366. }
  367. static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
  368. bool state_drvupdn)
  369. {
  370. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  371. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  372. struct sdhci_tegra_autocal_offsets *offsets =
  373. &tegra_host->autocal_offsets;
  374. struct pinctrl_state *pinctrl_drvupdn = NULL;
  375. int ret = 0;
  376. u8 drvup = 0, drvdn = 0;
  377. u32 reg;
  378. if (!state_drvupdn) {
  379. /* PADS Drive Strength */
  380. if (voltage == MMC_SIGNAL_VOLTAGE_180) {
  381. if (tegra_host->pinctrl_state_1v8_drv) {
  382. pinctrl_drvupdn =
  383. tegra_host->pinctrl_state_1v8_drv;
  384. } else {
  385. drvup = offsets->pull_up_1v8_timeout;
  386. drvdn = offsets->pull_down_1v8_timeout;
  387. }
  388. } else {
  389. if (tegra_host->pinctrl_state_3v3_drv) {
  390. pinctrl_drvupdn =
  391. tegra_host->pinctrl_state_3v3_drv;
  392. } else {
  393. drvup = offsets->pull_up_3v3_timeout;
  394. drvdn = offsets->pull_down_3v3_timeout;
  395. }
  396. }
  397. if (pinctrl_drvupdn != NULL) {
  398. ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
  399. pinctrl_drvupdn);
  400. if (ret < 0)
  401. dev_err(mmc_dev(host->mmc),
  402. "failed pads drvupdn, ret: %d\n", ret);
  403. } else if ((drvup) || (drvdn)) {
  404. reg = sdhci_readl(host,
  405. SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
  406. reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
  407. reg |= (drvup << 20) | (drvdn << 12);
  408. sdhci_writel(host, reg,
  409. SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
  410. }
  411. } else {
  412. /* Dual Voltage PADS Voltage selection */
  413. if (!tegra_host->pad_control_available)
  414. return 0;
  415. if (voltage == MMC_SIGNAL_VOLTAGE_180) {
  416. ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
  417. tegra_host->pinctrl_state_1v8);
  418. if (ret < 0)
  419. dev_err(mmc_dev(host->mmc),
  420. "setting 1.8V failed, ret: %d\n", ret);
  421. } else {
  422. ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
  423. tegra_host->pinctrl_state_3v3);
  424. if (ret < 0)
  425. dev_err(mmc_dev(host->mmc),
  426. "setting 3.3V failed, ret: %d\n", ret);
  427. }
  428. }
  429. return ret;
  430. }
  431. static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
  432. {
  433. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  434. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  435. struct sdhci_tegra_autocal_offsets offsets =
  436. tegra_host->autocal_offsets;
  437. struct mmc_ios *ios = &host->mmc->ios;
  438. bool card_clk_enabled;
  439. u16 pdpu;
  440. u32 reg;
  441. int ret;
  442. switch (ios->timing) {
  443. case MMC_TIMING_UHS_SDR104:
  444. pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
  445. break;
  446. case MMC_TIMING_MMC_HS400:
  447. pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
  448. break;
  449. default:
  450. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  451. pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
  452. else
  453. pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
  454. }
  455. /* Set initial offset before auto-calibration */
  456. tegra_sdhci_set_pad_autocal_offset(host, pdpu);
  457. card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
  458. tegra_sdhci_configure_cal_pad(host, true);
  459. reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  460. reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
  461. sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  462. usleep_range(1, 2);
  463. /* 10 ms timeout */
  464. ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
  465. reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
  466. 1000, 10000);
  467. tegra_sdhci_configure_cal_pad(host, false);
  468. tegra_sdhci_configure_card_clk(host, card_clk_enabled);
  469. if (ret) {
  470. dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
  471. /* Disable automatic cal and use fixed Drive Strengths */
  472. reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  473. reg &= ~SDHCI_AUTO_CAL_ENABLE;
  474. sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
  475. ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
  476. if (ret < 0)
  477. dev_err(mmc_dev(host->mmc),
  478. "Setting drive strengths failed: %d\n", ret);
  479. }
  480. }
  481. static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
  482. {
  483. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  484. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  485. struct sdhci_tegra_autocal_offsets *autocal =
  486. &tegra_host->autocal_offsets;
  487. int err;
  488. err = device_property_read_u32(host->mmc->parent,
  489. "nvidia,pad-autocal-pull-up-offset-3v3",
  490. &autocal->pull_up_3v3);
  491. if (err)
  492. autocal->pull_up_3v3 = 0;
  493. err = device_property_read_u32(host->mmc->parent,
  494. "nvidia,pad-autocal-pull-down-offset-3v3",
  495. &autocal->pull_down_3v3);
  496. if (err)
  497. autocal->pull_down_3v3 = 0;
  498. err = device_property_read_u32(host->mmc->parent,
  499. "nvidia,pad-autocal-pull-up-offset-1v8",
  500. &autocal->pull_up_1v8);
  501. if (err)
  502. autocal->pull_up_1v8 = 0;
  503. err = device_property_read_u32(host->mmc->parent,
  504. "nvidia,pad-autocal-pull-down-offset-1v8",
  505. &autocal->pull_down_1v8);
  506. if (err)
  507. autocal->pull_down_1v8 = 0;
  508. err = device_property_read_u32(host->mmc->parent,
  509. "nvidia,pad-autocal-pull-up-offset-sdr104",
  510. &autocal->pull_up_sdr104);
  511. if (err)
  512. autocal->pull_up_sdr104 = autocal->pull_up_1v8;
  513. err = device_property_read_u32(host->mmc->parent,
  514. "nvidia,pad-autocal-pull-down-offset-sdr104",
  515. &autocal->pull_down_sdr104);
  516. if (err)
  517. autocal->pull_down_sdr104 = autocal->pull_down_1v8;
  518. err = device_property_read_u32(host->mmc->parent,
  519. "nvidia,pad-autocal-pull-up-offset-hs400",
  520. &autocal->pull_up_hs400);
  521. if (err)
  522. autocal->pull_up_hs400 = autocal->pull_up_1v8;
  523. err = device_property_read_u32(host->mmc->parent,
  524. "nvidia,pad-autocal-pull-down-offset-hs400",
  525. &autocal->pull_down_hs400);
  526. if (err)
  527. autocal->pull_down_hs400 = autocal->pull_down_1v8;
  528. /*
  529. * Different fail-safe drive strength values based on the signaling
  530. * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls.
  531. * So, avoid reading below device tree properties for SoCs that don't
  532. * have NVQUIRK_NEEDS_PAD_CONTROL.
  533. */
  534. if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
  535. return;
  536. err = device_property_read_u32(host->mmc->parent,
  537. "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
  538. &autocal->pull_up_3v3_timeout);
  539. if (err) {
  540. if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
  541. (tegra_host->pinctrl_state_3v3_drv == NULL))
  542. pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
  543. mmc_hostname(host->mmc));
  544. autocal->pull_up_3v3_timeout = 0;
  545. }
  546. err = device_property_read_u32(host->mmc->parent,
  547. "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
  548. &autocal->pull_down_3v3_timeout);
  549. if (err) {
  550. if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
  551. (tegra_host->pinctrl_state_3v3_drv == NULL))
  552. pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
  553. mmc_hostname(host->mmc));
  554. autocal->pull_down_3v3_timeout = 0;
  555. }
  556. err = device_property_read_u32(host->mmc->parent,
  557. "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
  558. &autocal->pull_up_1v8_timeout);
  559. if (err) {
  560. if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
  561. (tegra_host->pinctrl_state_1v8_drv == NULL))
  562. pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
  563. mmc_hostname(host->mmc));
  564. autocal->pull_up_1v8_timeout = 0;
  565. }
  566. err = device_property_read_u32(host->mmc->parent,
  567. "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
  568. &autocal->pull_down_1v8_timeout);
  569. if (err) {
  570. if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
  571. (tegra_host->pinctrl_state_1v8_drv == NULL))
  572. pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
  573. mmc_hostname(host->mmc));
  574. autocal->pull_down_1v8_timeout = 0;
  575. }
  576. }
  577. static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  578. {
  579. struct sdhci_host *host = mmc_priv(mmc);
  580. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  581. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  582. ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
  583. /* 100 ms calibration interval is specified in the TRM */
  584. if (ktime_to_ms(since_calib) > 100) {
  585. tegra_sdhci_pad_autocalib(host);
  586. tegra_host->last_calib = ktime_get();
  587. }
  588. sdhci_request(mmc, mrq);
  589. }
  590. static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
  591. {
  592. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  593. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  594. int err;
  595. err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap",
  596. &tegra_host->default_tap);
  597. if (err)
  598. tegra_host->default_tap = 0;
  599. err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim",
  600. &tegra_host->default_trim);
  601. if (err)
  602. tegra_host->default_trim = 0;
  603. err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim",
  604. &tegra_host->dqs_trim);
  605. if (err)
  606. tegra_host->dqs_trim = 0x11;
  607. }
  608. static void tegra_sdhci_parse_dt(struct sdhci_host *host)
  609. {
  610. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  611. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  612. if (device_property_read_bool(host->mmc->parent, "supports-cqe"))
  613. tegra_host->enable_hwcq = true;
  614. else
  615. tegra_host->enable_hwcq = false;
  616. tegra_sdhci_parse_pad_autocal_dt(host);
  617. tegra_sdhci_parse_tap_and_trim(host);
  618. }
  619. static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  620. {
  621. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  622. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  623. unsigned long host_clk;
  624. if (!clock)
  625. return sdhci_set_clock(host, clock);
  626. /*
  627. * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
  628. * divider to be configured to divided the host clock by two. The SDHCI
  629. * clock divider is calculated as part of sdhci_set_clock() by
  630. * sdhci_calc_clk(). The divider is calculated from host->max_clk and
  631. * the requested clock rate.
  632. *
  633. * By setting the host->max_clk to clock * 2 the divider calculation
  634. * will always result in the correct value for DDR50/52 modes,
  635. * regardless of clock rate rounding, which may happen if the value
  636. * from clk_get_rate() is used.
  637. */
  638. host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
  639. clk_set_rate(pltfm_host->clk, host_clk);
  640. tegra_host->curr_clk_rate = host_clk;
  641. if (tegra_host->ddr_signaling)
  642. host->max_clk = host_clk;
  643. else
  644. host->max_clk = clk_get_rate(pltfm_host->clk);
  645. sdhci_set_clock(host, clock);
  646. if (tegra_host->pad_calib_required) {
  647. tegra_sdhci_pad_autocalib(host);
  648. tegra_host->pad_calib_required = false;
  649. }
  650. }
  651. static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
  652. struct mmc_ios *ios)
  653. {
  654. struct sdhci_host *host = mmc_priv(mmc);
  655. u32 val;
  656. val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
  657. if (ios->enhanced_strobe) {
  658. val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
  659. /*
  660. * When CMD13 is sent from mmc_select_hs400es() after
  661. * switching to HS400ES mode, the bus is operating at
  662. * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
  663. * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
  664. * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
  665. * controller CAR clock and the interface clock are rate matched.
  666. */
  667. tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
  668. } else {
  669. val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
  670. }
  671. sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
  672. }
  673. static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
  674. {
  675. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  676. return clk_round_rate(pltfm_host->clk, UINT_MAX);
  677. }
  678. static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
  679. {
  680. u32 val;
  681. val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
  682. val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
  683. val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
  684. sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
  685. }
  686. static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
  687. {
  688. u32 reg;
  689. int err;
  690. reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
  691. reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
  692. sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
  693. /* 1 ms sleep, 5 ms timeout */
  694. err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
  695. reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
  696. 1000, 5000);
  697. if (err)
  698. dev_err(mmc_dev(host->mmc),
  699. "HS400 delay line calibration timed out\n");
  700. }
  701. static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
  702. u8 thd_low, u8 fixed_tap)
  703. {
  704. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  705. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  706. u32 val, tun_status;
  707. u8 word, bit, edge1, tap, window;
  708. bool tap_result;
  709. bool start_fail = false;
  710. bool start_pass = false;
  711. bool end_pass = false;
  712. bool first_fail = false;
  713. bool first_pass = false;
  714. u8 start_pass_tap = 0;
  715. u8 end_pass_tap = 0;
  716. u8 first_fail_tap = 0;
  717. u8 first_pass_tap = 0;
  718. u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
  719. /*
  720. * Read auto-tuned results and extract good valid passing window by
  721. * filtering out un-wanted bubble/partial/merged windows.
  722. */
  723. for (word = 0; word < total_tuning_words; word++) {
  724. val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
  725. val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK;
  726. val |= word;
  727. sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
  728. tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);
  729. bit = 0;
  730. while (bit < TUNING_WORD_BIT_SIZE) {
  731. tap = word * TUNING_WORD_BIT_SIZE + bit;
  732. tap_result = tun_status & (1 << bit);
  733. if (!tap_result && !start_fail) {
  734. start_fail = true;
  735. if (!first_fail) {
  736. first_fail_tap = tap;
  737. first_fail = true;
  738. }
  739. } else if (tap_result && start_fail && !start_pass) {
  740. start_pass_tap = tap;
  741. start_pass = true;
  742. if (!first_pass) {
  743. first_pass_tap = tap;
  744. first_pass = true;
  745. }
  746. } else if (!tap_result && start_fail && start_pass &&
  747. !end_pass) {
  748. end_pass_tap = tap - 1;
  749. end_pass = true;
  750. } else if (tap_result && start_pass && start_fail &&
  751. end_pass) {
  752. window = end_pass_tap - start_pass_tap;
  753. /* discard merged window and bubble window */
  754. if (window >= thd_up || window < thd_low) {
  755. start_pass_tap = tap;
  756. end_pass = false;
  757. } else {
  758. /* set tap at middle of valid window */
  759. tap = start_pass_tap + window / 2;
  760. tegra_host->tuned_tap_delay = tap;
  761. return;
  762. }
  763. }
  764. bit++;
  765. }
  766. }
  767. if (!first_fail) {
  768. WARN(1, "no edge detected, continue with hw tuned delay.\n");
  769. } else if (first_pass) {
  770. /* set tap location at fixed tap relative to the first edge */
  771. edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
  772. if (edge1 - 1 > fixed_tap)
  773. tegra_host->tuned_tap_delay = edge1 - fixed_tap;
  774. else
  775. tegra_host->tuned_tap_delay = edge1 + fixed_tap;
  776. }
  777. }
  778. static void tegra_sdhci_post_tuning(struct sdhci_host *host)
  779. {
  780. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  781. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  782. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  783. u32 avg_tap_dly, val, min_tap_dly, max_tap_dly;
  784. u8 fixed_tap, start_tap, end_tap, window_width;
  785. u8 thdupper, thdlower;
  786. u8 num_iter;
  787. u32 clk_rate_mhz, period_ps, bestcase, worstcase;
  788. /* retain HW tuned tap to use incase if no correction is needed */
  789. val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
  790. tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
  791. SDHCI_CLOCK_CTRL_TAP_SHIFT;
  792. if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
  793. min_tap_dly = soc_data->min_tap_delay;
  794. max_tap_dly = soc_data->max_tap_delay;
  795. clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
  796. period_ps = USEC_PER_SEC / clk_rate_mhz;
  797. bestcase = period_ps / min_tap_dly;
  798. worstcase = period_ps / max_tap_dly;
  799. /*
  800. * Upper and Lower bound thresholds used to detect merged and
  801. * bubble windows
  802. */
  803. thdupper = (2 * worstcase + bestcase) / 2;
  804. thdlower = worstcase / 4;
  805. /*
  806. * fixed tap is used when HW tuning result contains single edge
  807. * and tap is set at fixed tap delay relative to the first edge
  808. */
  809. avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly);
  810. fixed_tap = avg_tap_dly / 2;
  811. val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);
  812. start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
  813. end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) &
  814. SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
  815. window_width = end_tap - start_tap;
  816. num_iter = host->tuning_loop_count;
  817. /*
  818. * partial window includes edges of the tuning range.
  819. * merged window includes more taps so window width is higher
  820. * than upper threshold.
  821. */
  822. if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
  823. (end_tap == num_iter - 2) || window_width >= thdupper) {
  824. pr_debug("%s: Apply tuning correction\n",
  825. mmc_hostname(host->mmc));
  826. tegra_sdhci_tap_correction(host, thdupper, thdlower,
  827. fixed_tap);
  828. }
  829. }
  830. tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
  831. }
  832. static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
  833. {
  834. struct sdhci_host *host = mmc_priv(mmc);
  835. int err;
  836. err = sdhci_execute_tuning(mmc, opcode);
  837. if (!err && !host->tuning_err)
  838. tegra_sdhci_post_tuning(host);
  839. return err;
  840. }
  841. static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
  842. unsigned timing)
  843. {
  844. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  845. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  846. bool set_default_tap = false;
  847. bool set_dqs_trim = false;
  848. bool do_hs400_dll_cal = false;
  849. u8 iter = TRIES_256;
  850. u32 val;
  851. tegra_host->ddr_signaling = false;
  852. switch (timing) {
  853. case MMC_TIMING_UHS_SDR50:
  854. break;
  855. case MMC_TIMING_UHS_SDR104:
  856. case MMC_TIMING_MMC_HS200:
  857. /* Don't set default tap on tunable modes. */
  858. iter = TRIES_128;
  859. break;
  860. case MMC_TIMING_MMC_HS400:
  861. set_dqs_trim = true;
  862. do_hs400_dll_cal = true;
  863. iter = TRIES_128;
  864. break;
  865. case MMC_TIMING_MMC_DDR52:
  866. case MMC_TIMING_UHS_DDR50:
  867. tegra_host->ddr_signaling = true;
  868. set_default_tap = true;
  869. break;
  870. default:
  871. set_default_tap = true;
  872. break;
  873. }
  874. val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
  875. val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK |
  876. SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK |
  877. SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK);
  878. val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT |
  879. 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT |
  880. 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT);
  881. sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
  882. sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0);
  883. host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
  884. sdhci_set_uhs_signaling(host, timing);
  885. tegra_sdhci_pad_autocalib(host);
  886. if (tegra_host->tuned_tap_delay && !set_default_tap)
  887. tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
  888. else
  889. tegra_sdhci_set_tap(host, tegra_host->default_tap);
  890. if (set_dqs_trim)
  891. tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
  892. if (do_hs400_dll_cal)
  893. tegra_sdhci_hs400_dll_cal(host);
  894. }
  895. static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
  896. {
  897. unsigned int min, max;
  898. /*
  899. * Start search for minimum tap value at 10, as smaller values are
  900. * may wrongly be reported as working but fail at higher speeds,
  901. * according to the TRM.
  902. */
  903. min = 10;
  904. while (min < 255) {
  905. tegra_sdhci_set_tap(host, min);
  906. if (!mmc_send_tuning(host->mmc, opcode, NULL))
  907. break;
  908. min++;
  909. }
  910. /* Find the maximum tap value that still passes. */
  911. max = min + 1;
  912. while (max < 255) {
  913. tegra_sdhci_set_tap(host, max);
  914. if (mmc_send_tuning(host->mmc, opcode, NULL)) {
  915. max--;
  916. break;
  917. }
  918. max++;
  919. }
  920. /* The TRM states the ideal tap value is at 75% in the passing range. */
  921. tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
  922. return mmc_send_tuning(host->mmc, opcode, NULL);
  923. }
  924. static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
  925. struct mmc_ios *ios)
  926. {
  927. struct sdhci_host *host = mmc_priv(mmc);
  928. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  929. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  930. int ret = 0;
  931. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
  932. ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
  933. if (ret < 0)
  934. return ret;
  935. ret = sdhci_start_signal_voltage_switch(mmc, ios);
  936. } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  937. ret = sdhci_start_signal_voltage_switch(mmc, ios);
  938. if (ret < 0)
  939. return ret;
  940. ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
  941. }
  942. if (tegra_host->pad_calib_required)
  943. tegra_sdhci_pad_autocalib(host);
  944. return ret;
  945. }
  946. static int tegra_sdhci_init_pinctrl_info(struct device *dev,
  947. struct sdhci_tegra *tegra_host)
  948. {
  949. tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
  950. if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
  951. dev_dbg(dev, "No pinctrl info, err: %ld\n",
  952. PTR_ERR(tegra_host->pinctrl_sdmmc));
  953. return -1;
  954. }
  955. tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
  956. tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
  957. if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
  958. if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
  959. tegra_host->pinctrl_state_1v8_drv = NULL;
  960. }
  961. tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
  962. tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
  963. if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
  964. if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
  965. tegra_host->pinctrl_state_3v3_drv = NULL;
  966. }
  967. tegra_host->pinctrl_state_3v3 =
  968. pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
  969. if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
  970. dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
  971. PTR_ERR(tegra_host->pinctrl_state_3v3));
  972. return -1;
  973. }
  974. tegra_host->pinctrl_state_1v8 =
  975. pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
  976. if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
  977. dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
  978. PTR_ERR(tegra_host->pinctrl_state_1v8));
  979. return -1;
  980. }
  981. tegra_host->pad_control_available = true;
  982. return 0;
  983. }
  984. static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
  985. {
  986. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  987. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  988. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  989. if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
  990. tegra_host->pad_calib_required = true;
  991. }
  992. static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
  993. {
  994. struct mmc_host *mmc = cq_host->mmc;
  995. struct sdhci_host *host = mmc_priv(mmc);
  996. u8 ctrl;
  997. ktime_t timeout;
  998. bool timed_out;
  999. /*
  1000. * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to
  1001. * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need
  1002. * to be re-configured.
  1003. * Tegra CQHCI/SDHCI prevents write access to block size register when
  1004. * CQE is unhalted. So handling CQE resume sequence here to configure
  1005. * SDHCI block registers prior to exiting CQE halt state.
  1006. */
  1007. if (reg == CQHCI_CTL && !(val & CQHCI_HALT) &&
  1008. cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
  1009. sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
  1010. sdhci_cqe_enable(mmc);
  1011. writel(val, cq_host->mmio + reg);
  1012. timeout = ktime_add_us(ktime_get(), 50);
  1013. while (1) {
  1014. timed_out = ktime_compare(ktime_get(), timeout) > 0;
  1015. ctrl = cqhci_readl(cq_host, CQHCI_CTL);
  1016. if (!(ctrl & CQHCI_HALT) || timed_out)
  1017. break;
  1018. }
  1019. /*
  1020. * CQE usually resumes very quick, but incase if Tegra CQE
  1021. * doesn't resume retry unhalt.
  1022. */
  1023. if (timed_out)
  1024. writel(val, cq_host->mmio + reg);
  1025. } else {
  1026. writel(val, cq_host->mmio + reg);
  1027. }
  1028. }
  1029. static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
  1030. struct mmc_request *mrq, u64 *data)
  1031. {
  1032. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc));
  1033. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  1034. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  1035. if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
  1036. mrq->cmd->flags & MMC_RSP_R1B)
  1037. *data |= CQHCI_CMD_TIMING(1);
  1038. }
  1039. static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
  1040. {
  1041. struct cqhci_host *cq_host = mmc->cqe_private;
  1042. struct sdhci_host *host = mmc_priv(mmc);
  1043. u32 val;
  1044. /*
  1045. * Tegra CQHCI/SDMMC design prevents write access to sdhci block size
  1046. * register when CQE is enabled and unhalted.
  1047. * CQHCI driver enables CQE prior to activation, so disable CQE before
  1048. * programming block size in sdhci controller and enable it back.
  1049. */
  1050. if (!cq_host->activated) {
  1051. val = cqhci_readl(cq_host, CQHCI_CFG);
  1052. if (val & CQHCI_ENABLE)
  1053. cqhci_writel(cq_host, (val & ~CQHCI_ENABLE),
  1054. CQHCI_CFG);
  1055. sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
  1056. sdhci_cqe_enable(mmc);
  1057. if (val & CQHCI_ENABLE)
  1058. cqhci_writel(cq_host, val, CQHCI_CFG);
  1059. }
  1060. /*
  1061. * CMD CRC errors are seen sometimes with some eMMC devices when status
  1062. * command is sent during transfer of last data block which is the
  1063. * default case as send status command block counter (CBC) is 1.
  1064. * Recommended fix to set CBC to 0 allowing send status command only
  1065. * when data lines are idle.
  1066. */
  1067. val = cqhci_readl(cq_host, CQHCI_SSC1);
  1068. val &= ~CQHCI_SSC1_CBC_MASK;
  1069. cqhci_writel(cq_host, val, CQHCI_SSC1);
  1070. }
  1071. static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
  1072. {
  1073. sdhci_dumpregs(mmc_priv(mmc));
  1074. }
  1075. static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
  1076. {
  1077. int cmd_error = 0;
  1078. int data_error = 0;
  1079. if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
  1080. return intmask;
  1081. cqhci_irq(host->mmc, intmask, cmd_error, data_error);
  1082. return 0;
  1083. }
  1084. static void tegra_sdhci_set_timeout(struct sdhci_host *host,
  1085. struct mmc_command *cmd)
  1086. {
  1087. u32 val;
  1088. /*
  1089. * HW busy detection timeout is based on programmed data timeout
  1090. * counter and maximum supported timeout is 11s which may not be
  1091. * enough for long operations like cache flush, sleep awake, erase.
  1092. *
  1093. * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows
  1094. * host controller to wait for busy state until the card is busy
  1095. * without HW timeout.
  1096. *
  1097. * So, use infinite busy wait mode for operations that may take
  1098. * more than maximum HW busy timeout of 11s otherwise use finite
  1099. * busy wait mode.
  1100. */
  1101. val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  1102. if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC)
  1103. val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
  1104. else
  1105. val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
  1106. sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  1107. __sdhci_set_timeout(host, cmd);
  1108. }
  1109. static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc)
  1110. {
  1111. struct cqhci_host *cq_host = mmc->cqe_private;
  1112. u32 reg;
  1113. reg = cqhci_readl(cq_host, CQHCI_CFG);
  1114. reg |= CQHCI_ENABLE;
  1115. cqhci_writel(cq_host, reg, CQHCI_CFG);
  1116. }
  1117. static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc)
  1118. {
  1119. struct cqhci_host *cq_host = mmc->cqe_private;
  1120. struct sdhci_host *host = mmc_priv(mmc);
  1121. u32 reg;
  1122. reg = cqhci_readl(cq_host, CQHCI_CFG);
  1123. reg &= ~CQHCI_ENABLE;
  1124. cqhci_writel(cq_host, reg, CQHCI_CFG);
  1125. sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
  1126. }
  1127. static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
  1128. .write_l = tegra_cqhci_writel,
  1129. .enable = sdhci_tegra_cqe_enable,
  1130. .disable = sdhci_cqe_disable,
  1131. .dumpregs = sdhci_tegra_dumpregs,
  1132. .update_dcmd_desc = sdhci_tegra_update_dcmd_desc,
  1133. .pre_enable = sdhci_tegra_cqe_pre_enable,
  1134. .post_disable = sdhci_tegra_cqe_post_disable,
  1135. };
  1136. static int tegra_sdhci_set_dma_mask(struct sdhci_host *host)
  1137. {
  1138. struct sdhci_pltfm_host *platform = sdhci_priv(host);
  1139. struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform);
  1140. const struct sdhci_tegra_soc_data *soc = tegra->soc_data;
  1141. struct device *dev = mmc_dev(host->mmc);
  1142. if (soc->dma_mask)
  1143. return dma_set_mask_and_coherent(dev, soc->dma_mask);
  1144. return 0;
  1145. }
  1146. static const struct sdhci_ops tegra_sdhci_ops = {
  1147. .get_ro = tegra_sdhci_get_ro,
  1148. .read_w = tegra_sdhci_readw,
  1149. .write_l = tegra_sdhci_writel,
  1150. .set_clock = tegra_sdhci_set_clock,
  1151. .set_dma_mask = tegra_sdhci_set_dma_mask,
  1152. .set_bus_width = sdhci_set_bus_width,
  1153. .reset = tegra_sdhci_reset,
  1154. .platform_execute_tuning = tegra_sdhci_execute_tuning,
  1155. .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
  1156. .voltage_switch = tegra_sdhci_voltage_switch,
  1157. .get_max_clock = tegra_sdhci_get_max_clock,
  1158. };
  1159. static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
  1160. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  1161. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  1162. SDHCI_QUIRK_NO_HISPD_BIT |
  1163. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  1164. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  1165. .ops = &tegra_sdhci_ops,
  1166. };
  1167. static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
  1168. .pdata = &sdhci_tegra20_pdata,
  1169. .dma_mask = DMA_BIT_MASK(32),
  1170. .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
  1171. NVQUIRK_ENABLE_BLOCK_GAP_DET,
  1172. };
  1173. static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
  1174. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  1175. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  1176. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  1177. SDHCI_QUIRK_NO_HISPD_BIT |
  1178. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  1179. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  1180. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  1181. SDHCI_QUIRK2_BROKEN_HS200 |
  1182. /*
  1183. * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
  1184. * though no command operation was in progress."
  1185. *
  1186. * The exact reason is unknown, as the same hardware seems
  1187. * to support Auto CMD23 on a downstream 3.1 kernel.
  1188. */
  1189. SDHCI_QUIRK2_ACMD23_BROKEN,
  1190. .ops = &tegra_sdhci_ops,
  1191. };
  1192. static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
  1193. .pdata = &sdhci_tegra30_pdata,
  1194. .dma_mask = DMA_BIT_MASK(32),
  1195. .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
  1196. NVQUIRK_ENABLE_SDR50 |
  1197. NVQUIRK_ENABLE_SDR104 |
  1198. NVQUIRK_HAS_PADCALIB,
  1199. };
  1200. static const struct sdhci_ops tegra114_sdhci_ops = {
  1201. .get_ro = tegra_sdhci_get_ro,
  1202. .read_w = tegra_sdhci_readw,
  1203. .write_w = tegra_sdhci_writew,
  1204. .write_l = tegra_sdhci_writel,
  1205. .set_clock = tegra_sdhci_set_clock,
  1206. .set_dma_mask = tegra_sdhci_set_dma_mask,
  1207. .set_bus_width = sdhci_set_bus_width,
  1208. .reset = tegra_sdhci_reset,
  1209. .platform_execute_tuning = tegra_sdhci_execute_tuning,
  1210. .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
  1211. .voltage_switch = tegra_sdhci_voltage_switch,
  1212. .get_max_clock = tegra_sdhci_get_max_clock,
  1213. };
  1214. static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
  1215. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  1216. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  1217. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  1218. SDHCI_QUIRK_NO_HISPD_BIT |
  1219. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  1220. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  1221. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  1222. .ops = &tegra114_sdhci_ops,
  1223. };
  1224. static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
  1225. .pdata = &sdhci_tegra114_pdata,
  1226. .dma_mask = DMA_BIT_MASK(32),
  1227. };
  1228. static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
  1229. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  1230. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  1231. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  1232. SDHCI_QUIRK_NO_HISPD_BIT |
  1233. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  1234. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  1235. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  1236. .ops = &tegra114_sdhci_ops,
  1237. };
  1238. static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
  1239. .pdata = &sdhci_tegra124_pdata,
  1240. .dma_mask = DMA_BIT_MASK(34),
  1241. };
  1242. static const struct sdhci_ops tegra210_sdhci_ops = {
  1243. .get_ro = tegra_sdhci_get_ro,
  1244. .read_w = tegra_sdhci_readw,
  1245. .write_w = tegra210_sdhci_writew,
  1246. .write_l = tegra_sdhci_writel,
  1247. .set_clock = tegra_sdhci_set_clock,
  1248. .set_dma_mask = tegra_sdhci_set_dma_mask,
  1249. .set_bus_width = sdhci_set_bus_width,
  1250. .reset = tegra_sdhci_reset,
  1251. .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
  1252. .voltage_switch = tegra_sdhci_voltage_switch,
  1253. .get_max_clock = tegra_sdhci_get_max_clock,
  1254. .set_timeout = tegra_sdhci_set_timeout,
  1255. };
  1256. static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
  1257. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  1258. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  1259. SDHCI_QUIRK_NO_HISPD_BIT |
  1260. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  1261. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  1262. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  1263. .ops = &tegra210_sdhci_ops,
  1264. };
  1265. static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
  1266. .pdata = &sdhci_tegra210_pdata,
  1267. .dma_mask = DMA_BIT_MASK(34),
  1268. .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
  1269. NVQUIRK_HAS_PADCALIB |
  1270. NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
  1271. NVQUIRK_ENABLE_SDR50 |
  1272. NVQUIRK_ENABLE_SDR104 |
  1273. NVQUIRK_HAS_TMCLK,
  1274. .min_tap_delay = 106,
  1275. .max_tap_delay = 185,
  1276. };
  1277. static const struct sdhci_ops tegra186_sdhci_ops = {
  1278. .get_ro = tegra_sdhci_get_ro,
  1279. .read_w = tegra_sdhci_readw,
  1280. .write_l = tegra_sdhci_writel,
  1281. .set_clock = tegra_sdhci_set_clock,
  1282. .set_dma_mask = tegra_sdhci_set_dma_mask,
  1283. .set_bus_width = sdhci_set_bus_width,
  1284. .reset = tegra_sdhci_reset,
  1285. .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
  1286. .voltage_switch = tegra_sdhci_voltage_switch,
  1287. .get_max_clock = tegra_sdhci_get_max_clock,
  1288. .irq = sdhci_tegra_cqhci_irq,
  1289. .set_timeout = tegra_sdhci_set_timeout,
  1290. };
  1291. static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
  1292. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  1293. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  1294. SDHCI_QUIRK_NO_HISPD_BIT |
  1295. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
  1296. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  1297. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  1298. .ops = &tegra186_sdhci_ops,
  1299. };
  1300. static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
  1301. .pdata = &sdhci_tegra186_pdata,
  1302. .dma_mask = DMA_BIT_MASK(40),
  1303. .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
  1304. NVQUIRK_HAS_PADCALIB |
  1305. NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
  1306. NVQUIRK_ENABLE_SDR50 |
  1307. NVQUIRK_ENABLE_SDR104 |
  1308. NVQUIRK_HAS_TMCLK |
  1309. NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING,
  1310. .min_tap_delay = 84,
  1311. .max_tap_delay = 136,
  1312. };
  1313. static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
  1314. .pdata = &sdhci_tegra186_pdata,
  1315. .dma_mask = DMA_BIT_MASK(39),
  1316. .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
  1317. NVQUIRK_HAS_PADCALIB |
  1318. NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
  1319. NVQUIRK_ENABLE_SDR50 |
  1320. NVQUIRK_ENABLE_SDR104 |
  1321. NVQUIRK_HAS_TMCLK,
  1322. .min_tap_delay = 96,
  1323. .max_tap_delay = 139,
  1324. };
  1325. static const struct of_device_id sdhci_tegra_dt_match[] = {
  1326. { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
  1327. { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
  1328. { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
  1329. { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
  1330. { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
  1331. { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
  1332. { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
  1333. {}
  1334. };
  1335. MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
  1336. static int sdhci_tegra_add_host(struct sdhci_host *host)
  1337. {
  1338. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1339. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  1340. struct cqhci_host *cq_host;
  1341. bool dma64;
  1342. int ret;
  1343. if (!tegra_host->enable_hwcq)
  1344. return sdhci_add_host(host);
  1345. sdhci_enable_v4_mode(host);
  1346. ret = sdhci_setup_host(host);
  1347. if (ret)
  1348. return ret;
  1349. host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
  1350. cq_host = devm_kzalloc(host->mmc->parent,
  1351. sizeof(*cq_host), GFP_KERNEL);
  1352. if (!cq_host) {
  1353. ret = -ENOMEM;
  1354. goto cleanup;
  1355. }
  1356. cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
  1357. cq_host->ops = &sdhci_tegra_cqhci_ops;
  1358. dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
  1359. if (dma64)
  1360. cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  1361. ret = cqhci_init(cq_host, host->mmc, dma64);
  1362. if (ret)
  1363. goto cleanup;
  1364. ret = __sdhci_add_host(host);
  1365. if (ret)
  1366. goto cleanup;
  1367. return 0;
  1368. cleanup:
  1369. sdhci_cleanup_host(host);
  1370. return ret;
  1371. }
  1372. static int sdhci_tegra_probe(struct platform_device *pdev)
  1373. {
  1374. const struct of_device_id *match;
  1375. const struct sdhci_tegra_soc_data *soc_data;
  1376. struct sdhci_host *host;
  1377. struct sdhci_pltfm_host *pltfm_host;
  1378. struct sdhci_tegra *tegra_host;
  1379. struct clk *clk;
  1380. int rc;
  1381. match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
  1382. if (!match)
  1383. return -EINVAL;
  1384. soc_data = match->data;
  1385. host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
  1386. if (IS_ERR(host))
  1387. return PTR_ERR(host);
  1388. pltfm_host = sdhci_priv(host);
  1389. tegra_host = sdhci_pltfm_priv(pltfm_host);
  1390. tegra_host->ddr_signaling = false;
  1391. tegra_host->pad_calib_required = false;
  1392. tegra_host->pad_control_available = false;
  1393. tegra_host->soc_data = soc_data;
  1394. if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
  1395. rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
  1396. if (rc == 0)
  1397. host->mmc_host_ops.start_signal_voltage_switch =
  1398. sdhci_tegra_start_signal_voltage_switch;
  1399. }
  1400. /* Hook to periodically rerun pad calibration */
  1401. if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
  1402. host->mmc_host_ops.request = tegra_sdhci_request;
  1403. host->mmc_host_ops.hs400_enhanced_strobe =
  1404. tegra_sdhci_hs400_enhanced_strobe;
  1405. if (!host->ops->platform_execute_tuning)
  1406. host->mmc_host_ops.execute_tuning =
  1407. tegra_sdhci_execute_hw_tuning;
  1408. rc = mmc_of_parse(host->mmc);
  1409. if (rc)
  1410. goto err_parse_dt;
  1411. if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
  1412. host->mmc->caps |= MMC_CAP_1_8V_DDR;
  1413. /* HW busy detection is supported, but R1B responses are required. */
  1414. host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
  1415. tegra_sdhci_parse_dt(host);
  1416. tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
  1417. GPIOD_OUT_HIGH);
  1418. if (IS_ERR(tegra_host->power_gpio)) {
  1419. rc = PTR_ERR(tegra_host->power_gpio);
  1420. goto err_power_req;
  1421. }
  1422. /*
  1423. * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
  1424. * timeout clock and SW can choose TMCLK or SDCLK for hardware
  1425. * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
  1426. * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
  1427. *
  1428. * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
  1429. * 12Mhz TMCLK which is advertised in host capability register.
  1430. * With TMCLK of 12Mhz provides maximum data timeout period that can
  1431. * be achieved is 11s better than using SDCLK for data timeout.
  1432. *
  1433. * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
  1434. * supporting separate TMCLK.
  1435. */
  1436. if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {
  1437. clk = devm_clk_get(&pdev->dev, "tmclk");
  1438. if (IS_ERR(clk)) {
  1439. rc = PTR_ERR(clk);
  1440. if (rc == -EPROBE_DEFER)
  1441. goto err_power_req;
  1442. dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
  1443. clk = NULL;
  1444. }
  1445. clk_set_rate(clk, 12000000);
  1446. rc = clk_prepare_enable(clk);
  1447. if (rc) {
  1448. dev_err(&pdev->dev,
  1449. "failed to enable tmclk: %d\n", rc);
  1450. goto err_power_req;
  1451. }
  1452. tegra_host->tmclk = clk;
  1453. }
  1454. clk = devm_clk_get(mmc_dev(host->mmc), NULL);
  1455. if (IS_ERR(clk)) {
  1456. rc = dev_err_probe(&pdev->dev, PTR_ERR(clk),
  1457. "failed to get clock\n");
  1458. goto err_clk_get;
  1459. }
  1460. clk_prepare_enable(clk);
  1461. pltfm_host->clk = clk;
  1462. tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
  1463. "sdhci");
  1464. if (IS_ERR(tegra_host->rst)) {
  1465. rc = PTR_ERR(tegra_host->rst);
  1466. dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
  1467. goto err_rst_get;
  1468. }
  1469. rc = reset_control_assert(tegra_host->rst);
  1470. if (rc)
  1471. goto err_rst_get;
  1472. usleep_range(2000, 4000);
  1473. rc = reset_control_deassert(tegra_host->rst);
  1474. if (rc)
  1475. goto err_rst_get;
  1476. usleep_range(2000, 4000);
  1477. rc = sdhci_tegra_add_host(host);
  1478. if (rc)
  1479. goto err_add_host;
  1480. return 0;
  1481. err_add_host:
  1482. reset_control_assert(tegra_host->rst);
  1483. err_rst_get:
  1484. clk_disable_unprepare(pltfm_host->clk);
  1485. err_clk_get:
  1486. clk_disable_unprepare(tegra_host->tmclk);
  1487. err_power_req:
  1488. err_parse_dt:
  1489. sdhci_pltfm_free(pdev);
  1490. return rc;
  1491. }
  1492. static int sdhci_tegra_remove(struct platform_device *pdev)
  1493. {
  1494. struct sdhci_host *host = platform_get_drvdata(pdev);
  1495. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1496. struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
  1497. sdhci_remove_host(host, 0);
  1498. reset_control_assert(tegra_host->rst);
  1499. usleep_range(2000, 4000);
  1500. clk_disable_unprepare(pltfm_host->clk);
  1501. clk_disable_unprepare(tegra_host->tmclk);
  1502. sdhci_pltfm_free(pdev);
  1503. return 0;
  1504. }
  1505. #ifdef CONFIG_PM_SLEEP
  1506. static int __maybe_unused sdhci_tegra_suspend(struct device *dev)
  1507. {
  1508. struct sdhci_host *host = dev_get_drvdata(dev);
  1509. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1510. int ret;
  1511. if (host->mmc->caps2 & MMC_CAP2_CQE) {
  1512. ret = cqhci_suspend(host->mmc);
  1513. if (ret)
  1514. return ret;
  1515. }
  1516. ret = sdhci_suspend_host(host);
  1517. if (ret) {
  1518. cqhci_resume(host->mmc);
  1519. return ret;
  1520. }
  1521. clk_disable_unprepare(pltfm_host->clk);
  1522. return 0;
  1523. }
  1524. static int __maybe_unused sdhci_tegra_resume(struct device *dev)
  1525. {
  1526. struct sdhci_host *host = dev_get_drvdata(dev);
  1527. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1528. int ret;
  1529. ret = clk_prepare_enable(pltfm_host->clk);
  1530. if (ret)
  1531. return ret;
  1532. ret = sdhci_resume_host(host);
  1533. if (ret)
  1534. goto disable_clk;
  1535. if (host->mmc->caps2 & MMC_CAP2_CQE) {
  1536. ret = cqhci_resume(host->mmc);
  1537. if (ret)
  1538. goto suspend_host;
  1539. }
  1540. return 0;
  1541. suspend_host:
  1542. sdhci_suspend_host(host);
  1543. disable_clk:
  1544. clk_disable_unprepare(pltfm_host->clk);
  1545. return ret;
  1546. }
  1547. #endif
  1548. static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend,
  1549. sdhci_tegra_resume);
  1550. static struct platform_driver sdhci_tegra_driver = {
  1551. .driver = {
  1552. .name = "sdhci-tegra",
  1553. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1554. .of_match_table = sdhci_tegra_dt_match,
  1555. .pm = &sdhci_tegra_dev_pm_ops,
  1556. },
  1557. .probe = sdhci_tegra_probe,
  1558. .remove = sdhci_tegra_remove,
  1559. };
  1560. module_platform_driver(sdhci_tegra_driver);
  1561. MODULE_DESCRIPTION("SDHCI driver for Tegra");
  1562. MODULE_AUTHOR("Google, Inc.");
  1563. MODULE_LICENSE("GPL v2");