sdhci-pic32.c 6.6 KB

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  1. /*
  2. * Support of SDHCI platform devices for Microchip PIC32.
  3. *
  4. * Copyright (C) 2015 Microchip
  5. * Andrei Pistirica, Paul Thacker
  6. *
  7. * Inspired by sdhci-pltfm.c
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/highmem.h>
  16. #include <linux/module.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm.h>
  22. #include <linux/slab.h>
  23. #include <linux/mmc/host.h>
  24. #include <linux/io.h>
  25. #include "sdhci.h"
  26. #include "sdhci-pltfm.h"
  27. #include <linux/platform_data/sdhci-pic32.h>
  28. #define SDH_SHARED_BUS_CTRL 0x000000E0
  29. #define SDH_SHARED_BUS_NR_CLK_PINS_MASK 0x7
  30. #define SDH_SHARED_BUS_NR_IRQ_PINS_MASK 0x30
  31. #define SDH_SHARED_BUS_CLK_PINS 0x10
  32. #define SDH_SHARED_BUS_IRQ_PINS 0x14
  33. #define SDH_CAPS_SDH_SLOT_TYPE_MASK 0xC0000000
  34. #define SDH_SLOT_TYPE_REMOVABLE 0x0
  35. #define SDH_SLOT_TYPE_EMBEDDED 0x1
  36. #define SDH_SLOT_TYPE_SHARED_BUS 0x2
  37. #define SDHCI_CTRL_CDSSEL 0x80
  38. #define SDHCI_CTRL_CDTLVL 0x40
  39. #define ADMA_FIFO_RD_THSHLD 512
  40. #define ADMA_FIFO_WR_THSHLD 512
  41. struct pic32_sdhci_priv {
  42. struct platform_device *pdev;
  43. struct clk *sys_clk;
  44. struct clk *base_clk;
  45. };
  46. static unsigned int pic32_sdhci_get_max_clock(struct sdhci_host *host)
  47. {
  48. struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
  49. return clk_get_rate(sdhci_pdata->base_clk);
  50. }
  51. static void pic32_sdhci_set_bus_width(struct sdhci_host *host, int width)
  52. {
  53. u8 ctrl;
  54. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  55. if (width == MMC_BUS_WIDTH_8) {
  56. ctrl &= ~SDHCI_CTRL_4BITBUS;
  57. if (host->version >= SDHCI_SPEC_300)
  58. ctrl |= SDHCI_CTRL_8BITBUS;
  59. } else {
  60. if (host->version >= SDHCI_SPEC_300)
  61. ctrl &= ~SDHCI_CTRL_8BITBUS;
  62. if (width == MMC_BUS_WIDTH_4)
  63. ctrl |= SDHCI_CTRL_4BITBUS;
  64. else
  65. ctrl &= ~SDHCI_CTRL_4BITBUS;
  66. }
  67. /* CD select and test bits must be set for errata workaround. */
  68. ctrl &= ~SDHCI_CTRL_CDTLVL;
  69. ctrl |= SDHCI_CTRL_CDSSEL;
  70. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  71. }
  72. static unsigned int pic32_sdhci_get_ro(struct sdhci_host *host)
  73. {
  74. /*
  75. * The SDHCI_WRITE_PROTECT bit is unstable on current hardware so we
  76. * can't depend on its value in any way.
  77. */
  78. return 0;
  79. }
  80. static const struct sdhci_ops pic32_sdhci_ops = {
  81. .get_max_clock = pic32_sdhci_get_max_clock,
  82. .set_clock = sdhci_set_clock,
  83. .set_bus_width = pic32_sdhci_set_bus_width,
  84. .reset = sdhci_reset,
  85. .set_uhs_signaling = sdhci_set_uhs_signaling,
  86. .get_ro = pic32_sdhci_get_ro,
  87. };
  88. static const struct sdhci_pltfm_data sdhci_pic32_pdata = {
  89. .ops = &pic32_sdhci_ops,
  90. .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
  91. .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
  92. };
  93. static void pic32_sdhci_shared_bus(struct platform_device *pdev)
  94. {
  95. struct sdhci_host *host = platform_get_drvdata(pdev);
  96. u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL);
  97. u32 clk_pins = (bus & SDH_SHARED_BUS_NR_CLK_PINS_MASK) >> 0;
  98. u32 irq_pins = (bus & SDH_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4;
  99. /* select first clock */
  100. if (clk_pins & 1)
  101. bus |= (1 << SDH_SHARED_BUS_CLK_PINS);
  102. /* select first interrupt */
  103. if (irq_pins & 1)
  104. bus |= (1 << SDH_SHARED_BUS_IRQ_PINS);
  105. writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL);
  106. }
  107. static int pic32_sdhci_probe_platform(struct platform_device *pdev,
  108. struct pic32_sdhci_priv *pdata)
  109. {
  110. int ret = 0;
  111. u32 caps_slot_type;
  112. struct sdhci_host *host = platform_get_drvdata(pdev);
  113. /* Check card slot connected on shared bus. */
  114. host->caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  115. caps_slot_type = (host->caps & SDH_CAPS_SDH_SLOT_TYPE_MASK) >> 30;
  116. if (caps_slot_type == SDH_SLOT_TYPE_SHARED_BUS)
  117. pic32_sdhci_shared_bus(pdev);
  118. return ret;
  119. }
  120. static int pic32_sdhci_probe(struct platform_device *pdev)
  121. {
  122. struct sdhci_host *host;
  123. struct sdhci_pltfm_host *pltfm_host;
  124. struct pic32_sdhci_priv *sdhci_pdata;
  125. struct pic32_sdhci_platform_data *plat_data;
  126. int ret;
  127. host = sdhci_pltfm_init(pdev, &sdhci_pic32_pdata,
  128. sizeof(struct pic32_sdhci_priv));
  129. if (IS_ERR(host)) {
  130. ret = PTR_ERR(host);
  131. goto err;
  132. }
  133. pltfm_host = sdhci_priv(host);
  134. sdhci_pdata = sdhci_pltfm_priv(pltfm_host);
  135. plat_data = pdev->dev.platform_data;
  136. if (plat_data && plat_data->setup_dma) {
  137. ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD,
  138. ADMA_FIFO_WR_THSHLD);
  139. if (ret)
  140. goto err_host;
  141. }
  142. sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk");
  143. if (IS_ERR(sdhci_pdata->sys_clk)) {
  144. ret = PTR_ERR(sdhci_pdata->sys_clk);
  145. dev_err(&pdev->dev, "Error getting clock\n");
  146. goto err_host;
  147. }
  148. ret = clk_prepare_enable(sdhci_pdata->sys_clk);
  149. if (ret) {
  150. dev_err(&pdev->dev, "Error enabling clock\n");
  151. goto err_host;
  152. }
  153. sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk");
  154. if (IS_ERR(sdhci_pdata->base_clk)) {
  155. ret = PTR_ERR(sdhci_pdata->base_clk);
  156. dev_err(&pdev->dev, "Error getting clock\n");
  157. goto err_sys_clk;
  158. }
  159. ret = clk_prepare_enable(sdhci_pdata->base_clk);
  160. if (ret) {
  161. dev_err(&pdev->dev, "Error enabling clock\n");
  162. goto err_base_clk;
  163. }
  164. ret = mmc_of_parse(host->mmc);
  165. if (ret)
  166. goto err_base_clk;
  167. ret = pic32_sdhci_probe_platform(pdev, sdhci_pdata);
  168. if (ret) {
  169. dev_err(&pdev->dev, "failed to probe platform!\n");
  170. goto err_base_clk;
  171. }
  172. ret = sdhci_add_host(host);
  173. if (ret)
  174. goto err_base_clk;
  175. dev_info(&pdev->dev, "Successfully added sdhci host\n");
  176. return 0;
  177. err_base_clk:
  178. clk_disable_unprepare(sdhci_pdata->base_clk);
  179. err_sys_clk:
  180. clk_disable_unprepare(sdhci_pdata->sys_clk);
  181. err_host:
  182. sdhci_pltfm_free(pdev);
  183. err:
  184. dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret);
  185. return ret;
  186. }
  187. static int pic32_sdhci_remove(struct platform_device *pdev)
  188. {
  189. struct sdhci_host *host = platform_get_drvdata(pdev);
  190. struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
  191. u32 scratch;
  192. scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
  193. sdhci_remove_host(host, scratch == (u32)~0);
  194. clk_disable_unprepare(sdhci_pdata->base_clk);
  195. clk_disable_unprepare(sdhci_pdata->sys_clk);
  196. sdhci_pltfm_free(pdev);
  197. return 0;
  198. }
  199. static const struct of_device_id pic32_sdhci_id_table[] = {
  200. { .compatible = "microchip,pic32mzda-sdhci" },
  201. {}
  202. };
  203. MODULE_DEVICE_TABLE(of, pic32_sdhci_id_table);
  204. static struct platform_driver pic32_sdhci_driver = {
  205. .driver = {
  206. .name = "pic32-sdhci",
  207. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  208. .of_match_table = of_match_ptr(pic32_sdhci_id_table),
  209. },
  210. .probe = pic32_sdhci_probe,
  211. .remove = pic32_sdhci_remove,
  212. };
  213. module_platform_driver(pic32_sdhci_driver);
  214. MODULE_DESCRIPTION("Microchip PIC32 SDHCI driver");
  215. MODULE_AUTHOR("Pistirica Sorin Andrei & Sandeep Sheriker");
  216. MODULE_LICENSE("GPL v2");