sdhci-pci-gli.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 Genesys Logic, Inc.
  4. *
  5. * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
  6. *
  7. * Version: v0.9.0 (2019-08-08)
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/bits.h>
  11. #include <linux/pci.h>
  12. #include <linux/mmc/mmc.h>
  13. #include <linux/delay.h>
  14. #include "sdhci.h"
  15. #include "sdhci-pci.h"
  16. #include "cqhci.h"
  17. /* Genesys Logic extra registers */
  18. #define SDHCI_GLI_9750_WT 0x800
  19. #define SDHCI_GLI_9750_WT_EN BIT(0)
  20. #define GLI_9750_WT_EN_ON 0x1
  21. #define GLI_9750_WT_EN_OFF 0x0
  22. #define SDHCI_GLI_9750_DRIVING 0x860
  23. #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
  24. #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
  25. #define GLI_9750_DRIVING_1_VALUE 0xFFF
  26. #define GLI_9750_DRIVING_2_VALUE 0x3
  27. #define SDHCI_GLI_9750_SEL_1 BIT(29)
  28. #define SDHCI_GLI_9750_SEL_2 BIT(31)
  29. #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
  30. #define SDHCI_GLI_9750_PLL 0x864
  31. #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
  32. #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
  33. #define SDHCI_GLI_9750_PLL_DIR BIT(15)
  34. #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
  35. #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
  36. #define GLI_9750_PLL_TX2_INV_VALUE 0x1
  37. #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
  38. #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
  39. #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
  40. #define SDHCI_GLI_9750_PLLSSC 0x86C
  41. #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
  42. #define SDHCI_GLI_9750_SW_CTRL 0x874
  43. #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
  44. #define GLI_9750_SW_CTRL_4_VALUE 0x3
  45. #define SDHCI_GLI_9750_MISC 0x878
  46. #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
  47. #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
  48. #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
  49. #define GLI_9750_MISC_TX1_INV_VALUE 0x0
  50. #define GLI_9750_MISC_RX_INV_ON 0x1
  51. #define GLI_9750_MISC_RX_INV_OFF 0x0
  52. #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
  53. #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
  54. #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
  55. #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
  56. #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
  57. #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
  58. #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
  59. #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
  60. #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
  61. #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
  62. #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
  63. #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
  64. #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
  65. #define SDHCI_GLI_9763E_CTRL_HS400 0x7
  66. #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
  67. #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
  68. #define PCIE_GLI_9763E_VHS 0x884
  69. #define GLI_9763E_VHS_REV GENMASK(19, 16)
  70. #define GLI_9763E_VHS_REV_R 0x0
  71. #define GLI_9763E_VHS_REV_M 0x1
  72. #define GLI_9763E_VHS_REV_W 0x2
  73. #define PCIE_GLI_9763E_MB 0x888
  74. #define GLI_9763E_MB_CMDQ_OFF BIT(19)
  75. #define PCIE_GLI_9763E_SCR 0x8E0
  76. #define GLI_9763E_SCR_AXI_REQ BIT(9)
  77. #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
  78. #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
  79. SDHCI_TRNS_BLK_CNT_EN | \
  80. SDHCI_TRNS_DMA)
  81. #define PCI_GLI_9755_WT 0x800
  82. #define PCI_GLI_9755_WT_EN BIT(0)
  83. #define GLI_9755_WT_EN_ON 0x1
  84. #define GLI_9755_WT_EN_OFF 0x0
  85. #define PCI_GLI_9755_PLL 0x64
  86. #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
  87. #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
  88. #define PCI_GLI_9755_PLL_DIR BIT(15)
  89. #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
  90. #define PCI_GLI_9755_PLLSSC_EN BIT(31)
  91. #define PCI_GLI_9755_PLLSSC 0x68
  92. #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
  93. #define GLI_MAX_TUNING_LOOP 40
  94. /* Genesys Logic chipset */
  95. static inline void gl9750_wt_on(struct sdhci_host *host)
  96. {
  97. u32 wt_value;
  98. u32 wt_enable;
  99. wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
  100. wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
  101. if (wt_enable == GLI_9750_WT_EN_ON)
  102. return;
  103. wt_value &= ~SDHCI_GLI_9750_WT_EN;
  104. wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
  105. sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
  106. }
  107. static inline void gl9750_wt_off(struct sdhci_host *host)
  108. {
  109. u32 wt_value;
  110. u32 wt_enable;
  111. wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
  112. wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
  113. if (wt_enable == GLI_9750_WT_EN_OFF)
  114. return;
  115. wt_value &= ~SDHCI_GLI_9750_WT_EN;
  116. wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
  117. sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
  118. }
  119. static void gli_set_9750(struct sdhci_host *host)
  120. {
  121. u32 driving_value;
  122. u32 pll_value;
  123. u32 sw_ctrl_value;
  124. u32 misc_value;
  125. u32 parameter_value;
  126. u32 control_value;
  127. u16 ctrl2;
  128. gl9750_wt_on(host);
  129. driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
  130. pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
  131. sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
  132. misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
  133. parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
  134. control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
  135. driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
  136. driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
  137. driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
  138. GLI_9750_DRIVING_1_VALUE);
  139. driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
  140. GLI_9750_DRIVING_2_VALUE);
  141. driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
  142. driving_value |= SDHCI_GLI_9750_SEL_2;
  143. sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
  144. sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
  145. sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
  146. GLI_9750_SW_CTRL_4_VALUE);
  147. sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
  148. /* reset the tuning flow after reinit and before starting tuning */
  149. pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
  150. pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
  151. pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
  152. GLI_9750_PLL_TX2_INV_VALUE);
  153. pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
  154. GLI_9750_PLL_TX2_DLY_VALUE);
  155. misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
  156. misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
  157. misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
  158. misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
  159. GLI_9750_MISC_TX1_INV_VALUE);
  160. misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
  161. GLI_9750_MISC_RX_INV_VALUE);
  162. misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
  163. GLI_9750_MISC_TX1_DLY_VALUE);
  164. parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
  165. parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
  166. GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
  167. control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
  168. control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
  169. control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
  170. GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
  171. control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
  172. GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
  173. sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
  174. sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
  175. /* disable tuned clk */
  176. ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  177. ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
  178. sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
  179. /* enable tuning parameters control */
  180. control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
  181. control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
  182. GLI_9750_TUNING_CONTROL_EN_ON);
  183. sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
  184. /* write tuning parameters */
  185. sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
  186. /* disable tuning parameters control */
  187. control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
  188. control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
  189. GLI_9750_TUNING_CONTROL_EN_OFF);
  190. sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
  191. /* clear tuned clk */
  192. ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  193. ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
  194. sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
  195. gl9750_wt_off(host);
  196. }
  197. static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
  198. {
  199. u32 misc_value;
  200. gl9750_wt_on(host);
  201. misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
  202. misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
  203. if (b) {
  204. misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
  205. GLI_9750_MISC_RX_INV_ON);
  206. } else {
  207. misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
  208. GLI_9750_MISC_RX_INV_OFF);
  209. }
  210. sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
  211. gl9750_wt_off(host);
  212. }
  213. static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
  214. {
  215. int i;
  216. int rx_inv;
  217. for (rx_inv = 0; rx_inv < 2; rx_inv++) {
  218. gli_set_9750_rx_inv(host, !!rx_inv);
  219. sdhci_start_tuning(host);
  220. for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
  221. u16 ctrl;
  222. sdhci_send_tuning(host, opcode);
  223. if (!host->tuning_done) {
  224. sdhci_abort_tuning(host, opcode);
  225. break;
  226. }
  227. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  228. if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
  229. if (ctrl & SDHCI_CTRL_TUNED_CLK)
  230. return 0; /* Success! */
  231. break;
  232. }
  233. }
  234. }
  235. if (!host->tuning_done) {
  236. pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
  237. mmc_hostname(host->mmc));
  238. return -ETIMEDOUT;
  239. }
  240. pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
  241. mmc_hostname(host->mmc));
  242. sdhci_reset_tuning(host);
  243. return -EAGAIN;
  244. }
  245. static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
  246. {
  247. host->mmc->retune_period = 0;
  248. if (host->tuning_mode == SDHCI_TUNING_MODE_1)
  249. host->mmc->retune_period = host->tuning_count;
  250. gli_set_9750(host);
  251. host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
  252. sdhci_end_tuning(host);
  253. return 0;
  254. }
  255. static void gl9750_disable_ssc_pll(struct sdhci_host *host)
  256. {
  257. u32 pll;
  258. gl9750_wt_on(host);
  259. pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
  260. pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
  261. sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
  262. gl9750_wt_off(host);
  263. }
  264. static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
  265. {
  266. u32 pll;
  267. gl9750_wt_on(host);
  268. pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
  269. pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
  270. SDHCI_GLI_9750_PLL_PDIV |
  271. SDHCI_GLI_9750_PLL_DIR);
  272. pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
  273. FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
  274. FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
  275. sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
  276. gl9750_wt_off(host);
  277. /* wait for pll stable */
  278. mdelay(1);
  279. }
  280. static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
  281. {
  282. u32 pll;
  283. u32 ssc;
  284. gl9750_wt_on(host);
  285. pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
  286. ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
  287. pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
  288. SDHCI_GLI_9750_PLLSSC_EN);
  289. ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
  290. pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
  291. FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
  292. ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
  293. sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
  294. sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
  295. gl9750_wt_off(host);
  296. }
  297. static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
  298. {
  299. /* set pll to 205MHz and enable ssc */
  300. gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
  301. gl9750_set_pll(host, 0x1, 0x246, 0x0);
  302. }
  303. static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
  304. {
  305. struct mmc_ios *ios = &host->mmc->ios;
  306. u16 clk;
  307. host->mmc->actual_clock = 0;
  308. gl9750_disable_ssc_pll(host);
  309. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  310. if (clock == 0)
  311. return;
  312. clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  313. if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
  314. host->mmc->actual_clock = 205000000;
  315. gl9750_set_ssc_pll_205mhz(host);
  316. }
  317. sdhci_enable_clk(host, clk);
  318. }
  319. static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
  320. {
  321. int ret;
  322. ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
  323. PCI_IRQ_MSI | PCI_IRQ_MSIX);
  324. if (ret < 0) {
  325. pr_warn("%s: enable PCI MSI failed, error=%d\n",
  326. mmc_hostname(slot->host->mmc), ret);
  327. return;
  328. }
  329. slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
  330. }
  331. static inline void gl9755_wt_on(struct pci_dev *pdev)
  332. {
  333. u32 wt_value;
  334. u32 wt_enable;
  335. pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
  336. wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
  337. if (wt_enable == GLI_9755_WT_EN_ON)
  338. return;
  339. wt_value &= ~PCI_GLI_9755_WT_EN;
  340. wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
  341. pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
  342. }
  343. static inline void gl9755_wt_off(struct pci_dev *pdev)
  344. {
  345. u32 wt_value;
  346. u32 wt_enable;
  347. pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
  348. wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
  349. if (wt_enable == GLI_9755_WT_EN_OFF)
  350. return;
  351. wt_value &= ~PCI_GLI_9755_WT_EN;
  352. wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
  353. pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
  354. }
  355. static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
  356. {
  357. u32 pll;
  358. gl9755_wt_on(pdev);
  359. pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
  360. pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
  361. pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
  362. gl9755_wt_off(pdev);
  363. }
  364. static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
  365. {
  366. u32 pll;
  367. gl9755_wt_on(pdev);
  368. pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
  369. pll &= ~(PCI_GLI_9755_PLL_LDIV |
  370. PCI_GLI_9755_PLL_PDIV |
  371. PCI_GLI_9755_PLL_DIR);
  372. pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
  373. FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
  374. FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
  375. pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
  376. gl9755_wt_off(pdev);
  377. /* wait for pll stable */
  378. mdelay(1);
  379. }
  380. static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
  381. {
  382. u32 pll;
  383. u32 ssc;
  384. gl9755_wt_on(pdev);
  385. pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
  386. pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
  387. pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
  388. PCI_GLI_9755_PLLSSC_EN);
  389. ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
  390. pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
  391. FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
  392. ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
  393. pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
  394. pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
  395. gl9755_wt_off(pdev);
  396. }
  397. static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
  398. {
  399. /* set pll to 205MHz and enable ssc */
  400. gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
  401. gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
  402. }
  403. static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
  404. {
  405. struct sdhci_pci_slot *slot = sdhci_priv(host);
  406. struct mmc_ios *ios = &host->mmc->ios;
  407. struct pci_dev *pdev;
  408. u16 clk;
  409. pdev = slot->chip->pdev;
  410. host->mmc->actual_clock = 0;
  411. gl9755_disable_ssc_pll(pdev);
  412. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  413. if (clock == 0)
  414. return;
  415. clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  416. if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
  417. host->mmc->actual_clock = 205000000;
  418. gl9755_set_ssc_pll_205mhz(pdev);
  419. }
  420. sdhci_enable_clk(host, clk);
  421. }
  422. static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
  423. {
  424. struct sdhci_host *host = slot->host;
  425. gli_pcie_enable_msi(slot);
  426. slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
  427. sdhci_enable_v4_mode(host);
  428. return 0;
  429. }
  430. static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
  431. {
  432. struct sdhci_host *host = slot->host;
  433. gli_pcie_enable_msi(slot);
  434. slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
  435. sdhci_enable_v4_mode(host);
  436. return 0;
  437. }
  438. static void sdhci_gli_voltage_switch(struct sdhci_host *host)
  439. {
  440. /*
  441. * According to Section 3.6.1 signal voltage switch procedure in
  442. * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
  443. * follows:
  444. * (6) Set 1.8V Signal Enable in the Host Control 2 register.
  445. * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
  446. * period.
  447. * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
  448. * step (12).
  449. *
  450. * Wait 5ms after set 1.8V signal enable in Host Control 2 register
  451. * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
  452. *
  453. * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
  454. * slightly longer than 5ms before the control register reports that
  455. * 1.8V is ready, and far longer still before the card will actually
  456. * work reliably.
  457. */
  458. usleep_range(100000, 110000);
  459. }
  460. static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
  461. {
  462. sdhci_reset(host, mask);
  463. gli_set_9750(host);
  464. }
  465. static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
  466. {
  467. u32 value;
  468. value = readl(host->ioaddr + reg);
  469. if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
  470. value |= 0xc8;
  471. return value;
  472. }
  473. #ifdef CONFIG_PM_SLEEP
  474. static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
  475. {
  476. struct sdhci_pci_slot *slot = chip->slots[0];
  477. pci_free_irq_vectors(slot->chip->pdev);
  478. gli_pcie_enable_msi(slot);
  479. return sdhci_pci_resume_host(chip);
  480. }
  481. static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
  482. {
  483. struct sdhci_pci_slot *slot = chip->slots[0];
  484. int ret;
  485. ret = sdhci_pci_gli_resume(chip);
  486. if (ret)
  487. return ret;
  488. return cqhci_resume(slot->host->mmc);
  489. }
  490. static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
  491. {
  492. struct sdhci_pci_slot *slot = chip->slots[0];
  493. int ret;
  494. ret = cqhci_suspend(slot->host->mmc);
  495. if (ret)
  496. return ret;
  497. return sdhci_suspend_host(slot->host);
  498. }
  499. #endif
  500. static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
  501. struct mmc_ios *ios)
  502. {
  503. struct sdhci_host *host = mmc_priv(mmc);
  504. u32 val;
  505. val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
  506. if (ios->enhanced_strobe)
  507. val |= SDHCI_GLI_9763E_HS400_ES_BIT;
  508. else
  509. val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
  510. sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
  511. }
  512. static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
  513. unsigned int timing)
  514. {
  515. u16 ctrl_2;
  516. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  517. ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
  518. if (timing == MMC_TIMING_MMC_HS200)
  519. ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
  520. else if (timing == MMC_TIMING_MMC_HS)
  521. ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
  522. else if (timing == MMC_TIMING_MMC_DDR52)
  523. ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
  524. else if (timing == MMC_TIMING_MMC_HS400)
  525. ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
  526. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  527. }
  528. static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
  529. {
  530. sdhci_dumpregs(mmc_priv(mmc));
  531. }
  532. static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
  533. {
  534. struct cqhci_host *cq_host = mmc->cqe_private;
  535. u32 value;
  536. value = cqhci_readl(cq_host, CQHCI_CFG);
  537. value |= CQHCI_ENABLE;
  538. cqhci_writel(cq_host, value, CQHCI_CFG);
  539. }
  540. static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
  541. {
  542. struct sdhci_host *host = mmc_priv(mmc);
  543. sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
  544. sdhci_cqe_enable(mmc);
  545. }
  546. static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
  547. {
  548. int cmd_error = 0;
  549. int data_error = 0;
  550. if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
  551. return intmask;
  552. cqhci_irq(host->mmc, intmask, cmd_error, data_error);
  553. return 0;
  554. }
  555. static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
  556. {
  557. struct sdhci_host *host = mmc_priv(mmc);
  558. struct cqhci_host *cq_host = mmc->cqe_private;
  559. u32 value;
  560. value = cqhci_readl(cq_host, CQHCI_CFG);
  561. value &= ~CQHCI_ENABLE;
  562. cqhci_writel(cq_host, value, CQHCI_CFG);
  563. sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
  564. }
  565. static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
  566. .enable = sdhci_gl9763e_cqe_enable,
  567. .disable = sdhci_cqe_disable,
  568. .dumpregs = sdhci_gl9763e_dumpregs,
  569. .pre_enable = sdhci_gl9763e_cqe_pre_enable,
  570. .post_disable = sdhci_gl9763e_cqe_post_disable,
  571. };
  572. static int gl9763e_add_host(struct sdhci_pci_slot *slot)
  573. {
  574. struct device *dev = &slot->chip->pdev->dev;
  575. struct sdhci_host *host = slot->host;
  576. struct cqhci_host *cq_host;
  577. bool dma64;
  578. int ret;
  579. ret = sdhci_setup_host(host);
  580. if (ret)
  581. return ret;
  582. cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
  583. if (!cq_host) {
  584. ret = -ENOMEM;
  585. goto cleanup;
  586. }
  587. cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
  588. cq_host->ops = &sdhci_gl9763e_cqhci_ops;
  589. dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
  590. if (dma64)
  591. cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  592. ret = cqhci_init(cq_host, host->mmc, dma64);
  593. if (ret)
  594. goto cleanup;
  595. ret = __sdhci_add_host(host);
  596. if (ret)
  597. goto cleanup;
  598. return 0;
  599. cleanup:
  600. sdhci_cleanup_host(host);
  601. return ret;
  602. }
  603. static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
  604. {
  605. if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
  606. host->mmc->cqe_private)
  607. cqhci_deactivate(host->mmc);
  608. sdhci_reset(host, mask);
  609. }
  610. static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
  611. {
  612. struct pci_dev *pdev = slot->chip->pdev;
  613. u32 value;
  614. pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
  615. value &= ~GLI_9763E_VHS_REV;
  616. value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
  617. pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
  618. pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
  619. value |= GLI_9763E_SCR_AXI_REQ;
  620. pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
  621. pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
  622. value &= ~GLI_9763E_VHS_REV;
  623. value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
  624. pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
  625. }
  626. static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
  627. {
  628. struct pci_dev *pdev = slot->chip->pdev;
  629. struct sdhci_host *host = slot->host;
  630. u32 value;
  631. host->mmc->caps |= MMC_CAP_8_BIT_DATA |
  632. MMC_CAP_1_8V_DDR |
  633. MMC_CAP_NONREMOVABLE;
  634. host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
  635. MMC_CAP2_HS400_1_8V |
  636. MMC_CAP2_HS400_ES |
  637. MMC_CAP2_NO_SDIO |
  638. MMC_CAP2_NO_SD;
  639. pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
  640. if (!(value & GLI_9763E_MB_CMDQ_OFF))
  641. host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
  642. gli_pcie_enable_msi(slot);
  643. host->mmc_host_ops.hs400_enhanced_strobe =
  644. gl9763e_hs400_enhanced_strobe;
  645. gli_set_gl9763e(slot);
  646. sdhci_enable_v4_mode(host);
  647. return 0;
  648. }
  649. static const struct sdhci_ops sdhci_gl9755_ops = {
  650. .set_clock = sdhci_gl9755_set_clock,
  651. .enable_dma = sdhci_pci_enable_dma,
  652. .set_bus_width = sdhci_set_bus_width,
  653. .reset = sdhci_reset,
  654. .set_uhs_signaling = sdhci_set_uhs_signaling,
  655. .voltage_switch = sdhci_gli_voltage_switch,
  656. };
  657. const struct sdhci_pci_fixes sdhci_gl9755 = {
  658. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  659. .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
  660. .probe_slot = gli_probe_slot_gl9755,
  661. .ops = &sdhci_gl9755_ops,
  662. #ifdef CONFIG_PM_SLEEP
  663. .resume = sdhci_pci_gli_resume,
  664. #endif
  665. };
  666. static const struct sdhci_ops sdhci_gl9750_ops = {
  667. .read_l = sdhci_gl9750_readl,
  668. .set_clock = sdhci_gl9750_set_clock,
  669. .enable_dma = sdhci_pci_enable_dma,
  670. .set_bus_width = sdhci_set_bus_width,
  671. .reset = sdhci_gl9750_reset,
  672. .set_uhs_signaling = sdhci_set_uhs_signaling,
  673. .voltage_switch = sdhci_gli_voltage_switch,
  674. .platform_execute_tuning = gl9750_execute_tuning,
  675. };
  676. const struct sdhci_pci_fixes sdhci_gl9750 = {
  677. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  678. .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
  679. .probe_slot = gli_probe_slot_gl9750,
  680. .ops = &sdhci_gl9750_ops,
  681. #ifdef CONFIG_PM_SLEEP
  682. .resume = sdhci_pci_gli_resume,
  683. #endif
  684. };
  685. static const struct sdhci_ops sdhci_gl9763e_ops = {
  686. .set_clock = sdhci_set_clock,
  687. .enable_dma = sdhci_pci_enable_dma,
  688. .set_bus_width = sdhci_set_bus_width,
  689. .reset = sdhci_gl9763e_reset,
  690. .set_uhs_signaling = sdhci_set_gl9763e_signaling,
  691. .voltage_switch = sdhci_gli_voltage_switch,
  692. .irq = sdhci_gl9763e_cqhci_irq,
  693. };
  694. const struct sdhci_pci_fixes sdhci_gl9763e = {
  695. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  696. .probe_slot = gli_probe_slot_gl9763e,
  697. .ops = &sdhci_gl9763e_ops,
  698. #ifdef CONFIG_PM_SLEEP
  699. .resume = sdhci_cqhci_gli_resume,
  700. .suspend = sdhci_cqhci_gli_suspend,
  701. #endif
  702. .add_host = gl9763e_add_host,
  703. };