sdhci-pci-arasan.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sdhci-pci-arasan.c - Driver for Arasan PCI Controller with
  4. * integrated phy.
  5. *
  6. * Copyright (C) 2017 Arasan Chip Systems Inc.
  7. *
  8. * Author: Atul Garg <agarg@arasan.com>
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/delay.h>
  12. #include "sdhci.h"
  13. #include "sdhci-pci.h"
  14. /* Extra registers for Arasan SD/SDIO/MMC Host Controller with PHY */
  15. #define PHY_ADDR_REG 0x300
  16. #define PHY_DAT_REG 0x304
  17. #define PHY_WRITE BIT(8)
  18. #define PHY_BUSY BIT(9)
  19. #define DATA_MASK 0xFF
  20. /* PHY Specific Registers */
  21. #define DLL_STATUS 0x00
  22. #define IPAD_CTRL1 0x01
  23. #define IPAD_CTRL2 0x02
  24. #define IPAD_STS 0x03
  25. #define IOREN_CTRL1 0x06
  26. #define IOREN_CTRL2 0x07
  27. #define IOPU_CTRL1 0x08
  28. #define IOPU_CTRL2 0x09
  29. #define ITAP_DELAY 0x0C
  30. #define OTAP_DELAY 0x0D
  31. #define STRB_SEL 0x0E
  32. #define CLKBUF_SEL 0x0F
  33. #define MODE_CTRL 0x11
  34. #define DLL_TRIM 0x12
  35. #define CMD_CTRL 0x20
  36. #define DATA_CTRL 0x21
  37. #define STRB_CTRL 0x22
  38. #define CLK_CTRL 0x23
  39. #define PHY_CTRL 0x24
  40. #define DLL_ENBL BIT(3)
  41. #define RTRIM_EN BIT(1)
  42. #define PDB_ENBL BIT(1)
  43. #define RETB_ENBL BIT(6)
  44. #define ODEN_CMD BIT(1)
  45. #define ODEN_DAT 0xFF
  46. #define REN_STRB BIT(0)
  47. #define REN_CMND BIT(1)
  48. #define REN_DATA 0xFF
  49. #define PU_CMD BIT(1)
  50. #define PU_DAT 0xFF
  51. #define ITAPDLY_EN BIT(0)
  52. #define OTAPDLY_EN BIT(0)
  53. #define OD_REL_CMD BIT(1)
  54. #define OD_REL_DAT 0xFF
  55. #define DLLTRM_ICP 0x8
  56. #define PDB_CMND BIT(0)
  57. #define PDB_DATA 0xFF
  58. #define PDB_STRB BIT(0)
  59. #define PDB_CLOCK BIT(0)
  60. #define CALDONE_MASK 0x10
  61. #define DLL_RDY_MASK 0x10
  62. #define MAX_CLK_BUF 0x7
  63. /* Mode Controls */
  64. #define ENHSTRB_MODE BIT(0)
  65. #define HS400_MODE BIT(1)
  66. #define LEGACY_MODE BIT(2)
  67. #define DDR50_MODE BIT(3)
  68. /*
  69. * Controller has no specific bits for HS200/HS.
  70. * Used BIT(4), BIT(5) for software programming.
  71. */
  72. #define HS200_MODE BIT(4)
  73. #define HISPD_MODE BIT(5)
  74. #define OTAPDLY(x) (((x) << 1) | OTAPDLY_EN)
  75. #define ITAPDLY(x) (((x) << 1) | ITAPDLY_EN)
  76. #define FREQSEL(x) (((x) << 5) | DLL_ENBL)
  77. #define IOPAD(x, y) ((x) | ((y) << 2))
  78. /* Arasan private data */
  79. struct arasan_host {
  80. u32 chg_clk;
  81. };
  82. static int arasan_phy_addr_poll(struct sdhci_host *host, u32 offset, u32 mask)
  83. {
  84. ktime_t timeout = ktime_add_us(ktime_get(), 100);
  85. bool failed;
  86. u8 val = 0;
  87. while (1) {
  88. failed = ktime_after(ktime_get(), timeout);
  89. val = sdhci_readw(host, PHY_ADDR_REG);
  90. if (!(val & mask))
  91. return 0;
  92. if (failed)
  93. return -EBUSY;
  94. }
  95. }
  96. static int arasan_phy_write(struct sdhci_host *host, u8 data, u8 offset)
  97. {
  98. sdhci_writew(host, data, PHY_DAT_REG);
  99. sdhci_writew(host, (PHY_WRITE | offset), PHY_ADDR_REG);
  100. return arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);
  101. }
  102. static int arasan_phy_read(struct sdhci_host *host, u8 offset, u8 *data)
  103. {
  104. int ret;
  105. sdhci_writew(host, 0, PHY_DAT_REG);
  106. sdhci_writew(host, offset, PHY_ADDR_REG);
  107. ret = arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);
  108. /* Masking valid data bits */
  109. *data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK;
  110. return ret;
  111. }
  112. static int arasan_phy_sts_poll(struct sdhci_host *host, u32 offset, u32 mask)
  113. {
  114. int ret;
  115. ktime_t timeout = ktime_add_us(ktime_get(), 100);
  116. bool failed;
  117. u8 val = 0;
  118. while (1) {
  119. failed = ktime_after(ktime_get(), timeout);
  120. ret = arasan_phy_read(host, offset, &val);
  121. if (ret)
  122. return -EBUSY;
  123. else if (val & mask)
  124. return 0;
  125. if (failed)
  126. return -EBUSY;
  127. }
  128. }
  129. /* Initialize the Arasan PHY */
  130. static int arasan_phy_init(struct sdhci_host *host)
  131. {
  132. int ret;
  133. u8 val;
  134. /* Program IOPADs and wait for calibration to be done */
  135. if (arasan_phy_read(host, IPAD_CTRL1, &val) ||
  136. arasan_phy_write(host, val | RETB_ENBL | PDB_ENBL, IPAD_CTRL1) ||
  137. arasan_phy_read(host, IPAD_CTRL2, &val) ||
  138. arasan_phy_write(host, val | RTRIM_EN, IPAD_CTRL2))
  139. return -EBUSY;
  140. ret = arasan_phy_sts_poll(host, IPAD_STS, CALDONE_MASK);
  141. if (ret)
  142. return -EBUSY;
  143. /* Program CMD/Data lines */
  144. if (arasan_phy_read(host, IOREN_CTRL1, &val) ||
  145. arasan_phy_write(host, val | REN_CMND | REN_STRB, IOREN_CTRL1) ||
  146. arasan_phy_read(host, IOPU_CTRL1, &val) ||
  147. arasan_phy_write(host, val | PU_CMD, IOPU_CTRL1) ||
  148. arasan_phy_read(host, CMD_CTRL, &val) ||
  149. arasan_phy_write(host, val | PDB_CMND, CMD_CTRL) ||
  150. arasan_phy_read(host, IOREN_CTRL2, &val) ||
  151. arasan_phy_write(host, val | REN_DATA, IOREN_CTRL2) ||
  152. arasan_phy_read(host, IOPU_CTRL2, &val) ||
  153. arasan_phy_write(host, val | PU_DAT, IOPU_CTRL2) ||
  154. arasan_phy_read(host, DATA_CTRL, &val) ||
  155. arasan_phy_write(host, val | PDB_DATA, DATA_CTRL) ||
  156. arasan_phy_read(host, STRB_CTRL, &val) ||
  157. arasan_phy_write(host, val | PDB_STRB, STRB_CTRL) ||
  158. arasan_phy_read(host, CLK_CTRL, &val) ||
  159. arasan_phy_write(host, val | PDB_CLOCK, CLK_CTRL) ||
  160. arasan_phy_read(host, CLKBUF_SEL, &val) ||
  161. arasan_phy_write(host, val | MAX_CLK_BUF, CLKBUF_SEL) ||
  162. arasan_phy_write(host, LEGACY_MODE, MODE_CTRL))
  163. return -EBUSY;
  164. return 0;
  165. }
  166. /* Set Arasan PHY for different modes */
  167. static int arasan_phy_set(struct sdhci_host *host, u8 mode, u8 otap,
  168. u8 drv_type, u8 itap, u8 trim, u8 clk)
  169. {
  170. u8 val;
  171. int ret;
  172. if (mode == HISPD_MODE || mode == HS200_MODE)
  173. ret = arasan_phy_write(host, 0x0, MODE_CTRL);
  174. else
  175. ret = arasan_phy_write(host, mode, MODE_CTRL);
  176. if (ret)
  177. return ret;
  178. if (mode == HS400_MODE || mode == HS200_MODE) {
  179. ret = arasan_phy_read(host, IPAD_CTRL1, &val);
  180. if (ret)
  181. return ret;
  182. ret = arasan_phy_write(host, IOPAD(val, drv_type), IPAD_CTRL1);
  183. if (ret)
  184. return ret;
  185. }
  186. if (mode == LEGACY_MODE) {
  187. ret = arasan_phy_write(host, 0x0, OTAP_DELAY);
  188. if (ret)
  189. return ret;
  190. ret = arasan_phy_write(host, 0x0, ITAP_DELAY);
  191. } else {
  192. ret = arasan_phy_write(host, OTAPDLY(otap), OTAP_DELAY);
  193. if (ret)
  194. return ret;
  195. if (mode != HS200_MODE)
  196. ret = arasan_phy_write(host, ITAPDLY(itap), ITAP_DELAY);
  197. else
  198. ret = arasan_phy_write(host, 0x0, ITAP_DELAY);
  199. }
  200. if (ret)
  201. return ret;
  202. if (mode != LEGACY_MODE) {
  203. ret = arasan_phy_write(host, trim, DLL_TRIM);
  204. if (ret)
  205. return ret;
  206. }
  207. ret = arasan_phy_write(host, 0, DLL_STATUS);
  208. if (ret)
  209. return ret;
  210. if (mode != LEGACY_MODE) {
  211. ret = arasan_phy_write(host, FREQSEL(clk), DLL_STATUS);
  212. if (ret)
  213. return ret;
  214. ret = arasan_phy_sts_poll(host, DLL_STATUS, DLL_RDY_MASK);
  215. if (ret)
  216. return -EBUSY;
  217. }
  218. return 0;
  219. }
  220. static int arasan_select_phy_clock(struct sdhci_host *host)
  221. {
  222. struct sdhci_pci_slot *slot = sdhci_priv(host);
  223. struct arasan_host *arasan_host = sdhci_pci_priv(slot);
  224. u8 clk;
  225. if (arasan_host->chg_clk == host->mmc->ios.clock)
  226. return 0;
  227. arasan_host->chg_clk = host->mmc->ios.clock;
  228. if (host->mmc->ios.clock == 200000000)
  229. clk = 0x0;
  230. else if (host->mmc->ios.clock == 100000000)
  231. clk = 0x2;
  232. else if (host->mmc->ios.clock == 50000000)
  233. clk = 0x1;
  234. else
  235. clk = 0x0;
  236. if (host->mmc_host_ops.hs400_enhanced_strobe) {
  237. arasan_phy_set(host, ENHSTRB_MODE, 1, 0x0, 0x0,
  238. DLLTRM_ICP, clk);
  239. } else {
  240. switch (host->mmc->ios.timing) {
  241. case MMC_TIMING_LEGACY:
  242. arasan_phy_set(host, LEGACY_MODE, 0x0, 0x0, 0x0,
  243. 0x0, 0x0);
  244. break;
  245. case MMC_TIMING_MMC_HS:
  246. case MMC_TIMING_SD_HS:
  247. arasan_phy_set(host, HISPD_MODE, 0x3, 0x0, 0x2,
  248. DLLTRM_ICP, clk);
  249. break;
  250. case MMC_TIMING_MMC_HS200:
  251. case MMC_TIMING_UHS_SDR104:
  252. arasan_phy_set(host, HS200_MODE, 0x2,
  253. host->mmc->ios.drv_type, 0x0,
  254. DLLTRM_ICP, clk);
  255. break;
  256. case MMC_TIMING_MMC_DDR52:
  257. case MMC_TIMING_UHS_DDR50:
  258. arasan_phy_set(host, DDR50_MODE, 0x1, 0x0,
  259. 0x0, DLLTRM_ICP, clk);
  260. break;
  261. case MMC_TIMING_MMC_HS400:
  262. arasan_phy_set(host, HS400_MODE, 0x1,
  263. host->mmc->ios.drv_type, 0xa,
  264. DLLTRM_ICP, clk);
  265. break;
  266. default:
  267. break;
  268. }
  269. }
  270. return 0;
  271. }
  272. static int arasan_pci_probe_slot(struct sdhci_pci_slot *slot)
  273. {
  274. int err;
  275. slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA;
  276. err = arasan_phy_init(slot->host);
  277. if (err)
  278. return -ENODEV;
  279. return 0;
  280. }
  281. static void arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  282. {
  283. sdhci_set_clock(host, clock);
  284. /* Change phy settings for the new clock */
  285. arasan_select_phy_clock(host);
  286. }
  287. static const struct sdhci_ops arasan_sdhci_pci_ops = {
  288. .set_clock = arasan_sdhci_set_clock,
  289. .enable_dma = sdhci_pci_enable_dma,
  290. .set_bus_width = sdhci_set_bus_width,
  291. .reset = sdhci_reset,
  292. .set_uhs_signaling = sdhci_set_uhs_signaling,
  293. };
  294. const struct sdhci_pci_fixes sdhci_arasan = {
  295. .probe_slot = arasan_pci_probe_slot,
  296. .ops = &arasan_sdhci_pci_ops,
  297. .priv_size = sizeof(struct arasan_host),
  298. };