sdhci-of-sparx5.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * drivers/mmc/host/sdhci-of-sparx5.c
  4. *
  5. * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
  6. *
  7. * Copyright (c) 2019 Microchip Inc.
  8. *
  9. * Author: Lars Povlsen <lars.povlsen@microchip.com>
  10. */
  11. #include <linux/sizes.h>
  12. #include <linux/delay.h>
  13. #include <linux/module.h>
  14. #include <linux/regmap.h>
  15. #include <linux/of_device.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/dma-mapping.h>
  18. #include "sdhci-pltfm.h"
  19. #define CPU_REGS_GENERAL_CTRL (0x22 * 4)
  20. #define MSHC_DLY_CC_MASK GENMASK(16, 13)
  21. #define MSHC_DLY_CC_SHIFT 13
  22. #define MSHC_DLY_CC_MAX 15
  23. #define CPU_REGS_PROC_CTRL (0x2C * 4)
  24. #define ACP_CACHE_FORCE_ENA BIT(4)
  25. #define ACP_AWCACHE BIT(3)
  26. #define ACP_ARCACHE BIT(2)
  27. #define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
  28. #define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
  29. #define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
  30. #define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
  31. #define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
  32. #define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
  33. struct sdhci_sparx5_data {
  34. struct sdhci_host *host;
  35. struct regmap *cpu_ctrl;
  36. int delay_clock;
  37. };
  38. #define BOUNDARY_OK(addr, len) \
  39. ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
  40. /*
  41. * If DMA addr spans 128MB boundary, we split the DMA transfer into two
  42. * so that each DMA transfer doesn't exceed the boundary.
  43. */
  44. static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
  45. dma_addr_t addr, int len,
  46. unsigned int cmd)
  47. {
  48. int tmplen, offset;
  49. if (likely(!len || BOUNDARY_OK(addr, len))) {
  50. sdhci_adma_write_desc(host, desc, addr, len, cmd);
  51. return;
  52. }
  53. pr_debug("%s: write_desc: splitting dma len %d, offset %pad\n",
  54. mmc_hostname(host->mmc), len, &addr);
  55. offset = addr & (SZ_128M - 1);
  56. tmplen = SZ_128M - offset;
  57. sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
  58. addr += tmplen;
  59. len -= tmplen;
  60. sdhci_adma_write_desc(host, desc, addr, len, cmd);
  61. }
  62. static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
  63. {
  64. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  65. struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
  66. pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
  67. /* Update ACP caching attributes in HW */
  68. regmap_update_bits(sdhci_sparx5->cpu_ctrl,
  69. CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
  70. }
  71. static void sparx5_set_delay(struct sdhci_host *host, u8 value)
  72. {
  73. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  74. struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
  75. pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
  76. /* Update DLY_CC in HW */
  77. regmap_update_bits(sdhci_sparx5->cpu_ctrl,
  78. CPU_REGS_GENERAL_CTRL,
  79. MSHC_DLY_CC_MASK,
  80. (value << MSHC_DLY_CC_SHIFT));
  81. }
  82. static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
  83. {
  84. if (!mmc_card_is_removable(host->mmc)) {
  85. u8 value;
  86. value = sdhci_readb(host, MSHC2_EMMC_CTRL);
  87. if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
  88. value |= MSHC2_EMMC_CTRL_IS_EMMC;
  89. pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
  90. mmc_hostname(host->mmc), value);
  91. sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
  92. }
  93. }
  94. }
  95. static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
  96. {
  97. u8 value;
  98. pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
  99. value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
  100. ~MSHC2_EMMC_CTRL_EMMC_RST_N;
  101. sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
  102. /* For eMMC, minimum is 1us but give it 10us for good measure */
  103. usleep_range(10, 20);
  104. sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
  105. MSHC2_EMMC_CTRL);
  106. /* For eMMC, minimum is 200us but give it 300us for good measure */
  107. usleep_range(300, 400);
  108. }
  109. static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
  110. {
  111. pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
  112. sdhci_reset(host, mask);
  113. /* Be sure CARD_IS_EMMC stays set */
  114. sdhci_sparx5_set_emmc(host);
  115. }
  116. static const struct sdhci_ops sdhci_sparx5_ops = {
  117. .set_clock = sdhci_set_clock,
  118. .set_bus_width = sdhci_set_bus_width,
  119. .set_uhs_signaling = sdhci_set_uhs_signaling,
  120. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  121. .reset = sdhci_sparx5_reset,
  122. .adma_write_desc = sdhci_sparx5_adma_write_desc,
  123. };
  124. static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
  125. .quirks = 0,
  126. .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
  127. SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
  128. .ops = &sdhci_sparx5_ops,
  129. };
  130. static int sdhci_sparx5_probe(struct platform_device *pdev)
  131. {
  132. int ret;
  133. const char *syscon = "microchip,sparx5-cpu-syscon";
  134. struct sdhci_host *host;
  135. struct sdhci_pltfm_host *pltfm_host;
  136. struct sdhci_sparx5_data *sdhci_sparx5;
  137. struct device_node *np = pdev->dev.of_node;
  138. u32 value;
  139. u32 extra;
  140. host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
  141. sizeof(*sdhci_sparx5));
  142. if (IS_ERR(host))
  143. return PTR_ERR(host);
  144. /*
  145. * extra adma table cnt for cross 128M boundary handling.
  146. */
  147. extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
  148. if (extra > SDHCI_MAX_SEGS)
  149. extra = SDHCI_MAX_SEGS;
  150. host->adma_table_cnt += extra;
  151. pltfm_host = sdhci_priv(host);
  152. sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
  153. sdhci_sparx5->host = host;
  154. pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
  155. if (IS_ERR(pltfm_host->clk)) {
  156. ret = PTR_ERR(pltfm_host->clk);
  157. dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
  158. goto free_pltfm;
  159. }
  160. ret = clk_prepare_enable(pltfm_host->clk);
  161. if (ret)
  162. goto free_pltfm;
  163. if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
  164. (value > 0 && value <= MSHC_DLY_CC_MAX))
  165. sdhci_sparx5->delay_clock = value;
  166. sdhci_get_of_property(pdev);
  167. ret = mmc_of_parse(host->mmc);
  168. if (ret)
  169. goto err_clk;
  170. sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
  171. if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
  172. dev_err(&pdev->dev, "No CPU syscon regmap !\n");
  173. ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
  174. goto err_clk;
  175. }
  176. if (sdhci_sparx5->delay_clock >= 0)
  177. sparx5_set_delay(host, sdhci_sparx5->delay_clock);
  178. if (!mmc_card_is_removable(host->mmc)) {
  179. /* Do a HW reset of eMMC card */
  180. sdhci_sparx5_reset_emmc(host);
  181. /* Update EMMC_CTRL */
  182. sdhci_sparx5_set_emmc(host);
  183. /* If eMMC, disable SD and SDIO */
  184. host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
  185. }
  186. ret = sdhci_add_host(host);
  187. if (ret)
  188. goto err_clk;
  189. /* Set AXI bus master to use un-cached access (for DMA) */
  190. if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
  191. IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
  192. sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
  193. pr_debug("%s: SDHC version: 0x%08x\n",
  194. mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
  195. pr_debug("%s: SDHC type: 0x%08x\n",
  196. mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
  197. return ret;
  198. err_clk:
  199. clk_disable_unprepare(pltfm_host->clk);
  200. free_pltfm:
  201. sdhci_pltfm_free(pdev);
  202. return ret;
  203. }
  204. static const struct of_device_id sdhci_sparx5_of_match[] = {
  205. { .compatible = "microchip,dw-sparx5-sdhci" },
  206. { }
  207. };
  208. MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
  209. static struct platform_driver sdhci_sparx5_driver = {
  210. .driver = {
  211. .name = "sdhci-sparx5",
  212. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  213. .of_match_table = sdhci_sparx5_of_match,
  214. .pm = &sdhci_pltfm_pmops,
  215. },
  216. .probe = sdhci_sparx5_probe,
  217. .remove = sdhci_pltfm_unregister,
  218. };
  219. module_platform_driver(sdhci_sparx5_driver);
  220. MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
  221. MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
  222. MODULE_LICENSE("GPL v2");