sdhci-of-esdhc.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale eSDHC controller driver.
  4. *
  5. * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
  6. * Copyright (c) 2009 MontaVista Software, Inc.
  7. * Copyright 2020 NXP
  8. *
  9. * Authors: Xiaobo Xie <X.Xie@freescale.com>
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. */
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/delay.h>
  17. #include <linux/module.h>
  18. #include <linux/sys_soc.h>
  19. #include <linux/clk.h>
  20. #include <linux/ktime.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/iopoll.h>
  23. #include <linux/mmc/host.h>
  24. #include <linux/mmc/mmc.h>
  25. #include "sdhci-pltfm.h"
  26. #include "sdhci-esdhc.h"
  27. #define VENDOR_V_22 0x12
  28. #define VENDOR_V_23 0x13
  29. #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
  30. struct esdhc_clk_fixup {
  31. const unsigned int sd_dflt_max_clk;
  32. const unsigned int max_clk[MMC_TIMING_NUM];
  33. };
  34. static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
  35. .sd_dflt_max_clk = 25000000,
  36. .max_clk[MMC_TIMING_MMC_HS] = 46500000,
  37. .max_clk[MMC_TIMING_SD_HS] = 46500000,
  38. };
  39. static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
  40. .sd_dflt_max_clk = 25000000,
  41. .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
  42. .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
  43. };
  44. static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
  45. .sd_dflt_max_clk = 25000000,
  46. .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
  47. .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
  48. };
  49. static const struct esdhc_clk_fixup p1010_esdhc_clk = {
  50. .sd_dflt_max_clk = 20000000,
  51. .max_clk[MMC_TIMING_LEGACY] = 20000000,
  52. .max_clk[MMC_TIMING_MMC_HS] = 42000000,
  53. .max_clk[MMC_TIMING_SD_HS] = 40000000,
  54. };
  55. static const struct of_device_id sdhci_esdhc_of_match[] = {
  56. { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
  57. { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
  58. { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
  59. { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
  60. { .compatible = "fsl,mpc8379-esdhc" },
  61. { .compatible = "fsl,mpc8536-esdhc" },
  62. { .compatible = "fsl,esdhc" },
  63. { }
  64. };
  65. MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
  66. struct sdhci_esdhc {
  67. u8 vendor_ver;
  68. u8 spec_ver;
  69. bool quirk_incorrect_hostver;
  70. bool quirk_limited_clk_division;
  71. bool quirk_unreliable_pulse_detection;
  72. bool quirk_tuning_erratum_type1;
  73. bool quirk_tuning_erratum_type2;
  74. bool quirk_ignore_data_inhibit;
  75. bool quirk_delay_before_data_reset;
  76. bool quirk_trans_complete_erratum;
  77. bool in_sw_tuning;
  78. unsigned int peripheral_clock;
  79. const struct esdhc_clk_fixup *clk_fixup;
  80. u32 div_ratio;
  81. };
  82. /**
  83. * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
  84. * to make it compatible with SD spec.
  85. *
  86. * @host: pointer to sdhci_host
  87. * @spec_reg: SD spec register address
  88. * @value: 32bit eSDHC register value on spec_reg address
  89. *
  90. * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
  91. * registers are 32 bits. There are differences in register size, register
  92. * address, register function, bit position and function between eSDHC spec
  93. * and SD spec.
  94. *
  95. * Return a fixed up register value
  96. */
  97. static u32 esdhc_readl_fixup(struct sdhci_host *host,
  98. int spec_reg, u32 value)
  99. {
  100. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  101. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  102. u32 ret;
  103. /*
  104. * The bit of ADMA flag in eSDHC is not compatible with standard
  105. * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
  106. * supported by eSDHC.
  107. * And for many FSL eSDHC controller, the reset value of field
  108. * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
  109. * only these vendor version is greater than 2.2/0x12 support ADMA.
  110. */
  111. if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
  112. if (esdhc->vendor_ver > VENDOR_V_22) {
  113. ret = value | SDHCI_CAN_DO_ADMA2;
  114. return ret;
  115. }
  116. }
  117. /*
  118. * The DAT[3:0] line signal levels and the CMD line signal level are
  119. * not compatible with standard SDHC register. The line signal levels
  120. * DAT[7:0] are at bits 31:24 and the command line signal level is at
  121. * bit 23. All other bits are the same as in the standard SDHC
  122. * register.
  123. */
  124. if (spec_reg == SDHCI_PRESENT_STATE) {
  125. ret = value & 0x000fffff;
  126. ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
  127. ret |= (value << 1) & SDHCI_CMD_LVL;
  128. return ret;
  129. }
  130. /*
  131. * DTS properties of mmc host are used to enable each speed mode
  132. * according to soc and board capability. So clean up
  133. * SDR50/SDR104/DDR50 support bits here.
  134. */
  135. if (spec_reg == SDHCI_CAPABILITIES_1) {
  136. ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
  137. SDHCI_SUPPORT_DDR50);
  138. return ret;
  139. }
  140. /*
  141. * Some controllers have unreliable Data Line Active
  142. * bit for commands with busy signal. This affects
  143. * Command Inhibit (data) bit. Just ignore it since
  144. * MMC core driver has already polled card status
  145. * with CMD13 after any command with busy siganl.
  146. */
  147. if ((spec_reg == SDHCI_PRESENT_STATE) &&
  148. (esdhc->quirk_ignore_data_inhibit == true)) {
  149. ret = value & ~SDHCI_DATA_INHIBIT;
  150. return ret;
  151. }
  152. ret = value;
  153. return ret;
  154. }
  155. static u16 esdhc_readw_fixup(struct sdhci_host *host,
  156. int spec_reg, u32 value)
  157. {
  158. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  159. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  160. u16 ret;
  161. int shift = (spec_reg & 0x2) * 8;
  162. if (spec_reg == SDHCI_TRANSFER_MODE)
  163. return pltfm_host->xfer_mode_shadow;
  164. if (spec_reg == SDHCI_HOST_VERSION)
  165. ret = value & 0xffff;
  166. else
  167. ret = (value >> shift) & 0xffff;
  168. /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
  169. * vendor version and spec version information.
  170. */
  171. if ((spec_reg == SDHCI_HOST_VERSION) &&
  172. (esdhc->quirk_incorrect_hostver))
  173. ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
  174. return ret;
  175. }
  176. static u8 esdhc_readb_fixup(struct sdhci_host *host,
  177. int spec_reg, u32 value)
  178. {
  179. u8 ret;
  180. u8 dma_bits;
  181. int shift = (spec_reg & 0x3) * 8;
  182. ret = (value >> shift) & 0xff;
  183. /*
  184. * "DMA select" locates at offset 0x28 in SD specification, but on
  185. * P5020 or P3041, it locates at 0x29.
  186. */
  187. if (spec_reg == SDHCI_HOST_CONTROL) {
  188. /* DMA select is 22,23 bits in Protocol Control Register */
  189. dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
  190. /* fixup the result */
  191. ret &= ~SDHCI_CTRL_DMA_MASK;
  192. ret |= dma_bits;
  193. }
  194. return ret;
  195. }
  196. /**
  197. * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
  198. * written into eSDHC register.
  199. *
  200. * @host: pointer to sdhci_host
  201. * @spec_reg: SD spec register address
  202. * @value: 8/16/32bit SD spec register value that would be written
  203. * @old_value: 32bit eSDHC register value on spec_reg address
  204. *
  205. * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
  206. * registers are 32 bits. There are differences in register size, register
  207. * address, register function, bit position and function between eSDHC spec
  208. * and SD spec.
  209. *
  210. * Return a fixed up register value
  211. */
  212. static u32 esdhc_writel_fixup(struct sdhci_host *host,
  213. int spec_reg, u32 value, u32 old_value)
  214. {
  215. u32 ret;
  216. /*
  217. * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
  218. * when SYSCTL[RSTD] is set for some special operations.
  219. * No any impact on other operation.
  220. */
  221. if (spec_reg == SDHCI_INT_ENABLE)
  222. ret = value | SDHCI_INT_BLK_GAP;
  223. else
  224. ret = value;
  225. return ret;
  226. }
  227. static u32 esdhc_writew_fixup(struct sdhci_host *host,
  228. int spec_reg, u16 value, u32 old_value)
  229. {
  230. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  231. int shift = (spec_reg & 0x2) * 8;
  232. u32 ret;
  233. switch (spec_reg) {
  234. case SDHCI_TRANSFER_MODE:
  235. /*
  236. * Postpone this write, we must do it together with a
  237. * command write that is down below. Return old value.
  238. */
  239. pltfm_host->xfer_mode_shadow = value;
  240. return old_value;
  241. case SDHCI_COMMAND:
  242. ret = (value << 16) | pltfm_host->xfer_mode_shadow;
  243. return ret;
  244. }
  245. ret = old_value & (~(0xffff << shift));
  246. ret |= (value << shift);
  247. if (spec_reg == SDHCI_BLOCK_SIZE) {
  248. /*
  249. * Two last DMA bits are reserved, and first one is used for
  250. * non-standard blksz of 4096 bytes that we don't support
  251. * yet. So clear the DMA boundary bits.
  252. */
  253. ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
  254. }
  255. return ret;
  256. }
  257. static u32 esdhc_writeb_fixup(struct sdhci_host *host,
  258. int spec_reg, u8 value, u32 old_value)
  259. {
  260. u32 ret;
  261. u32 dma_bits;
  262. u8 tmp;
  263. int shift = (spec_reg & 0x3) * 8;
  264. /*
  265. * eSDHC doesn't have a standard power control register, so we do
  266. * nothing here to avoid incorrect operation.
  267. */
  268. if (spec_reg == SDHCI_POWER_CONTROL)
  269. return old_value;
  270. /*
  271. * "DMA select" location is offset 0x28 in SD specification, but on
  272. * P5020 or P3041, it's located at 0x29.
  273. */
  274. if (spec_reg == SDHCI_HOST_CONTROL) {
  275. /*
  276. * If host control register is not standard, exit
  277. * this function
  278. */
  279. if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
  280. return old_value;
  281. /* DMA select is 22,23 bits in Protocol Control Register */
  282. dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
  283. ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
  284. tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
  285. (old_value & SDHCI_CTRL_DMA_MASK);
  286. ret = (ret & (~0xff)) | tmp;
  287. /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
  288. ret &= ~ESDHC_HOST_CONTROL_RES;
  289. return ret;
  290. }
  291. ret = (old_value & (~(0xff << shift))) | (value << shift);
  292. return ret;
  293. }
  294. static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
  295. {
  296. u32 ret;
  297. u32 value;
  298. if (reg == SDHCI_CAPABILITIES_1)
  299. value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
  300. else
  301. value = ioread32be(host->ioaddr + reg);
  302. ret = esdhc_readl_fixup(host, reg, value);
  303. return ret;
  304. }
  305. static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
  306. {
  307. u32 ret;
  308. u32 value;
  309. if (reg == SDHCI_CAPABILITIES_1)
  310. value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
  311. else
  312. value = ioread32(host->ioaddr + reg);
  313. ret = esdhc_readl_fixup(host, reg, value);
  314. return ret;
  315. }
  316. static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
  317. {
  318. u16 ret;
  319. u32 value;
  320. int base = reg & ~0x3;
  321. value = ioread32be(host->ioaddr + base);
  322. ret = esdhc_readw_fixup(host, reg, value);
  323. return ret;
  324. }
  325. static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
  326. {
  327. u16 ret;
  328. u32 value;
  329. int base = reg & ~0x3;
  330. value = ioread32(host->ioaddr + base);
  331. ret = esdhc_readw_fixup(host, reg, value);
  332. return ret;
  333. }
  334. static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
  335. {
  336. u8 ret;
  337. u32 value;
  338. int base = reg & ~0x3;
  339. value = ioread32be(host->ioaddr + base);
  340. ret = esdhc_readb_fixup(host, reg, value);
  341. return ret;
  342. }
  343. static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
  344. {
  345. u8 ret;
  346. u32 value;
  347. int base = reg & ~0x3;
  348. value = ioread32(host->ioaddr + base);
  349. ret = esdhc_readb_fixup(host, reg, value);
  350. return ret;
  351. }
  352. static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
  353. {
  354. u32 value;
  355. value = esdhc_writel_fixup(host, reg, val, 0);
  356. iowrite32be(value, host->ioaddr + reg);
  357. }
  358. static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
  359. {
  360. u32 value;
  361. value = esdhc_writel_fixup(host, reg, val, 0);
  362. iowrite32(value, host->ioaddr + reg);
  363. }
  364. static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
  365. {
  366. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  367. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  368. int base = reg & ~0x3;
  369. u32 value;
  370. u32 ret;
  371. value = ioread32be(host->ioaddr + base);
  372. ret = esdhc_writew_fixup(host, reg, val, value);
  373. if (reg != SDHCI_TRANSFER_MODE)
  374. iowrite32be(ret, host->ioaddr + base);
  375. /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
  376. * 1us later after ESDHC_EXTN is set.
  377. */
  378. if (base == ESDHC_SYSTEM_CONTROL_2) {
  379. if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
  380. esdhc->in_sw_tuning) {
  381. udelay(1);
  382. ret |= ESDHC_SMPCLKSEL;
  383. iowrite32be(ret, host->ioaddr + base);
  384. }
  385. }
  386. }
  387. static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
  388. {
  389. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  390. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  391. int base = reg & ~0x3;
  392. u32 value;
  393. u32 ret;
  394. value = ioread32(host->ioaddr + base);
  395. ret = esdhc_writew_fixup(host, reg, val, value);
  396. if (reg != SDHCI_TRANSFER_MODE)
  397. iowrite32(ret, host->ioaddr + base);
  398. /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
  399. * 1us later after ESDHC_EXTN is set.
  400. */
  401. if (base == ESDHC_SYSTEM_CONTROL_2) {
  402. if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
  403. esdhc->in_sw_tuning) {
  404. udelay(1);
  405. ret |= ESDHC_SMPCLKSEL;
  406. iowrite32(ret, host->ioaddr + base);
  407. }
  408. }
  409. }
  410. static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
  411. {
  412. int base = reg & ~0x3;
  413. u32 value;
  414. u32 ret;
  415. value = ioread32be(host->ioaddr + base);
  416. ret = esdhc_writeb_fixup(host, reg, val, value);
  417. iowrite32be(ret, host->ioaddr + base);
  418. }
  419. static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
  420. {
  421. int base = reg & ~0x3;
  422. u32 value;
  423. u32 ret;
  424. value = ioread32(host->ioaddr + base);
  425. ret = esdhc_writeb_fixup(host, reg, val, value);
  426. iowrite32(ret, host->ioaddr + base);
  427. }
  428. /*
  429. * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
  430. * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
  431. * and Block Gap Event(IRQSTAT[BGE]) are also set.
  432. * For Continue, apply soft reset for data(SYSCTL[RSTD]);
  433. * and re-issue the entire read transaction from beginning.
  434. */
  435. static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
  436. {
  437. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  438. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  439. bool applicable;
  440. dma_addr_t dmastart;
  441. dma_addr_t dmanow;
  442. applicable = (intmask & SDHCI_INT_DATA_END) &&
  443. (intmask & SDHCI_INT_BLK_GAP) &&
  444. (esdhc->vendor_ver == VENDOR_V_23);
  445. if (!applicable)
  446. return;
  447. host->data->error = 0;
  448. dmastart = sg_dma_address(host->data->sg);
  449. dmanow = dmastart + host->data->bytes_xfered;
  450. /*
  451. * Force update to the next DMA block boundary.
  452. */
  453. dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
  454. SDHCI_DEFAULT_BOUNDARY_SIZE;
  455. host->data->bytes_xfered = dmanow - dmastart;
  456. sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
  457. }
  458. static int esdhc_of_enable_dma(struct sdhci_host *host)
  459. {
  460. int ret;
  461. u32 value;
  462. struct device *dev = mmc_dev(host->mmc);
  463. if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
  464. of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) {
  465. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
  466. if (ret)
  467. return ret;
  468. }
  469. value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
  470. if (of_dma_is_coherent(dev->of_node))
  471. value |= ESDHC_DMA_SNOOP;
  472. else
  473. value &= ~ESDHC_DMA_SNOOP;
  474. sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
  475. return 0;
  476. }
  477. static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
  478. {
  479. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  480. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  481. if (esdhc->peripheral_clock)
  482. return esdhc->peripheral_clock;
  483. else
  484. return pltfm_host->clock;
  485. }
  486. static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
  487. {
  488. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  489. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  490. unsigned int clock;
  491. if (esdhc->peripheral_clock)
  492. clock = esdhc->peripheral_clock;
  493. else
  494. clock = pltfm_host->clock;
  495. return clock / 256 / 16;
  496. }
  497. static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
  498. {
  499. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  500. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  501. ktime_t timeout;
  502. u32 val, clk_en;
  503. clk_en = ESDHC_CLOCK_SDCLKEN;
  504. /*
  505. * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version
  506. * is 2.2 or lower.
  507. */
  508. if (esdhc->vendor_ver <= VENDOR_V_22)
  509. clk_en |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
  510. ESDHC_CLOCK_PEREN);
  511. val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  512. if (enable)
  513. val |= clk_en;
  514. else
  515. val &= ~clk_en;
  516. sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
  517. /*
  518. * Wait max 20 ms. If vendor version is 2.2 or lower, do not
  519. * wait clock stable bit which does not exist.
  520. */
  521. timeout = ktime_add_ms(ktime_get(), 20);
  522. while (esdhc->vendor_ver > VENDOR_V_22) {
  523. bool timedout = ktime_after(ktime_get(), timeout);
  524. if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
  525. break;
  526. if (timedout) {
  527. pr_err("%s: Internal clock never stabilised.\n",
  528. mmc_hostname(host->mmc));
  529. break;
  530. }
  531. usleep_range(10, 20);
  532. }
  533. }
  534. static void esdhc_flush_async_fifo(struct sdhci_host *host)
  535. {
  536. ktime_t timeout;
  537. u32 val;
  538. val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
  539. val |= ESDHC_FLUSH_ASYNC_FIFO;
  540. sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
  541. /* Wait max 20 ms */
  542. timeout = ktime_add_ms(ktime_get(), 20);
  543. while (1) {
  544. bool timedout = ktime_after(ktime_get(), timeout);
  545. if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
  546. ESDHC_FLUSH_ASYNC_FIFO))
  547. break;
  548. if (timedout) {
  549. pr_err("%s: flushing asynchronous FIFO timeout.\n",
  550. mmc_hostname(host->mmc));
  551. break;
  552. }
  553. usleep_range(10, 20);
  554. }
  555. }
  556. static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
  557. {
  558. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  559. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  560. unsigned int pre_div = 1, div = 1;
  561. unsigned int clock_fixup = 0;
  562. ktime_t timeout;
  563. u32 temp;
  564. if (clock == 0) {
  565. host->mmc->actual_clock = 0;
  566. esdhc_clock_enable(host, false);
  567. return;
  568. }
  569. /* Start pre_div at 2 for vendor version < 2.3. */
  570. if (esdhc->vendor_ver < VENDOR_V_23)
  571. pre_div = 2;
  572. /* Fix clock value. */
  573. if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
  574. esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
  575. clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk;
  576. else if (esdhc->clk_fixup)
  577. clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
  578. if (clock_fixup == 0 || clock < clock_fixup)
  579. clock_fixup = clock;
  580. /* Calculate pre_div and div. */
  581. while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
  582. pre_div *= 2;
  583. while (host->max_clk / pre_div / div > clock_fixup && div < 16)
  584. div++;
  585. esdhc->div_ratio = pre_div * div;
  586. /* Limit clock division for HS400 200MHz clock for quirk. */
  587. if (esdhc->quirk_limited_clk_division &&
  588. clock == MMC_HS200_MAX_DTR &&
  589. (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
  590. host->flags & SDHCI_HS400_TUNING)) {
  591. if (esdhc->div_ratio <= 4) {
  592. pre_div = 4;
  593. div = 1;
  594. } else if (esdhc->div_ratio <= 8) {
  595. pre_div = 4;
  596. div = 2;
  597. } else if (esdhc->div_ratio <= 12) {
  598. pre_div = 4;
  599. div = 3;
  600. } else {
  601. pr_warn("%s: using unsupported clock division.\n",
  602. mmc_hostname(host->mmc));
  603. }
  604. esdhc->div_ratio = pre_div * div;
  605. }
  606. host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
  607. dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
  608. clock, host->mmc->actual_clock);
  609. /* Set clock division into register. */
  610. pre_div >>= 1;
  611. div--;
  612. esdhc_clock_enable(host, false);
  613. temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  614. temp &= ~ESDHC_CLOCK_MASK;
  615. temp |= ((div << ESDHC_DIVIDER_SHIFT) |
  616. (pre_div << ESDHC_PREDIV_SHIFT));
  617. sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
  618. /*
  619. * Wait max 20 ms. If vendor version is 2.2 or lower, do not
  620. * wait clock stable bit which does not exist.
  621. */
  622. timeout = ktime_add_ms(ktime_get(), 20);
  623. while (esdhc->vendor_ver > VENDOR_V_22) {
  624. bool timedout = ktime_after(ktime_get(), timeout);
  625. if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
  626. break;
  627. if (timedout) {
  628. pr_err("%s: Internal clock never stabilised.\n",
  629. mmc_hostname(host->mmc));
  630. break;
  631. }
  632. usleep_range(10, 20);
  633. }
  634. /* Additional setting for HS400. */
  635. if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
  636. clock == MMC_HS200_MAX_DTR) {
  637. temp = sdhci_readl(host, ESDHC_TBCTL);
  638. sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
  639. temp = sdhci_readl(host, ESDHC_SDCLKCTL);
  640. sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
  641. esdhc_clock_enable(host, true);
  642. temp = sdhci_readl(host, ESDHC_DLLCFG0);
  643. temp |= ESDHC_DLL_ENABLE;
  644. if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
  645. temp |= ESDHC_DLL_FREQ_SEL;
  646. sdhci_writel(host, temp, ESDHC_DLLCFG0);
  647. temp |= ESDHC_DLL_RESET;
  648. sdhci_writel(host, temp, ESDHC_DLLCFG0);
  649. udelay(1);
  650. temp &= ~ESDHC_DLL_RESET;
  651. sdhci_writel(host, temp, ESDHC_DLLCFG0);
  652. /* Wait max 20 ms */
  653. if (read_poll_timeout(sdhci_readl, temp,
  654. temp & ESDHC_DLL_STS_SLV_LOCK,
  655. 10, 20000, false,
  656. host, ESDHC_DLLSTAT0))
  657. pr_err("%s: timeout for delay chain lock.\n",
  658. mmc_hostname(host->mmc));
  659. temp = sdhci_readl(host, ESDHC_TBCTL);
  660. sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
  661. esdhc_clock_enable(host, false);
  662. esdhc_flush_async_fifo(host);
  663. }
  664. esdhc_clock_enable(host, true);
  665. }
  666. static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
  667. {
  668. u32 ctrl;
  669. ctrl = sdhci_readl(host, ESDHC_PROCTL);
  670. ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
  671. switch (width) {
  672. case MMC_BUS_WIDTH_8:
  673. ctrl |= ESDHC_CTRL_8BITBUS;
  674. break;
  675. case MMC_BUS_WIDTH_4:
  676. ctrl |= ESDHC_CTRL_4BITBUS;
  677. break;
  678. default:
  679. break;
  680. }
  681. sdhci_writel(host, ctrl, ESDHC_PROCTL);
  682. }
  683. static void esdhc_reset(struct sdhci_host *host, u8 mask)
  684. {
  685. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  686. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  687. u32 val, bus_width = 0;
  688. /*
  689. * Add delay to make sure all the DMA transfers are finished
  690. * for quirk.
  691. */
  692. if (esdhc->quirk_delay_before_data_reset &&
  693. (mask & SDHCI_RESET_DATA) &&
  694. (host->flags & SDHCI_REQ_USE_DMA))
  695. mdelay(5);
  696. /*
  697. * Save bus-width for eSDHC whose vendor version is 2.2
  698. * or lower for data reset.
  699. */
  700. if ((mask & SDHCI_RESET_DATA) &&
  701. (esdhc->vendor_ver <= VENDOR_V_22)) {
  702. val = sdhci_readl(host, ESDHC_PROCTL);
  703. bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
  704. }
  705. sdhci_reset(host, mask);
  706. /*
  707. * Restore bus-width setting and interrupt registers for eSDHC
  708. * whose vendor version is 2.2 or lower for data reset.
  709. */
  710. if ((mask & SDHCI_RESET_DATA) &&
  711. (esdhc->vendor_ver <= VENDOR_V_22)) {
  712. val = sdhci_readl(host, ESDHC_PROCTL);
  713. val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
  714. val |= bus_width;
  715. sdhci_writel(host, val, ESDHC_PROCTL);
  716. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  717. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  718. }
  719. /*
  720. * Some bits have to be cleaned manually for eSDHC whose spec
  721. * version is higher than 3.0 for all reset.
  722. */
  723. if ((mask & SDHCI_RESET_ALL) &&
  724. (esdhc->spec_ver >= SDHCI_SPEC_300)) {
  725. val = sdhci_readl(host, ESDHC_TBCTL);
  726. val &= ~ESDHC_TB_EN;
  727. sdhci_writel(host, val, ESDHC_TBCTL);
  728. /*
  729. * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to
  730. * 0 for quirk.
  731. */
  732. if (esdhc->quirk_unreliable_pulse_detection) {
  733. val = sdhci_readl(host, ESDHC_DLLCFG1);
  734. val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
  735. sdhci_writel(host, val, ESDHC_DLLCFG1);
  736. }
  737. }
  738. }
  739. /* The SCFG, Supplemental Configuration Unit, provides SoC specific
  740. * configuration and status registers for the device. There is a
  741. * SDHC IO VSEL control register on SCFG for some platforms. It's
  742. * used to support SDHC IO voltage switching.
  743. */
  744. static const struct of_device_id scfg_device_ids[] = {
  745. { .compatible = "fsl,t1040-scfg", },
  746. { .compatible = "fsl,ls1012a-scfg", },
  747. { .compatible = "fsl,ls1046a-scfg", },
  748. {}
  749. };
  750. /* SDHC IO VSEL control register definition */
  751. #define SCFG_SDHCIOVSELCR 0x408
  752. #define SDHCIOVSELCR_TGLEN 0x80000000
  753. #define SDHCIOVSELCR_VSELVAL 0x60000000
  754. #define SDHCIOVSELCR_SDHC_VS 0x00000001
  755. static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
  756. struct mmc_ios *ios)
  757. {
  758. struct sdhci_host *host = mmc_priv(mmc);
  759. struct device_node *scfg_node;
  760. void __iomem *scfg_base = NULL;
  761. u32 sdhciovselcr;
  762. u32 val;
  763. /*
  764. * Signal Voltage Switching is only applicable for Host Controllers
  765. * v3.00 and above.
  766. */
  767. if (host->version < SDHCI_SPEC_300)
  768. return 0;
  769. val = sdhci_readl(host, ESDHC_PROCTL);
  770. switch (ios->signal_voltage) {
  771. case MMC_SIGNAL_VOLTAGE_330:
  772. val &= ~ESDHC_VOLT_SEL;
  773. sdhci_writel(host, val, ESDHC_PROCTL);
  774. return 0;
  775. case MMC_SIGNAL_VOLTAGE_180:
  776. scfg_node = of_find_matching_node(NULL, scfg_device_ids);
  777. if (scfg_node)
  778. scfg_base = of_iomap(scfg_node, 0);
  779. if (scfg_base) {
  780. sdhciovselcr = SDHCIOVSELCR_TGLEN |
  781. SDHCIOVSELCR_VSELVAL;
  782. iowrite32be(sdhciovselcr,
  783. scfg_base + SCFG_SDHCIOVSELCR);
  784. val |= ESDHC_VOLT_SEL;
  785. sdhci_writel(host, val, ESDHC_PROCTL);
  786. mdelay(5);
  787. sdhciovselcr = SDHCIOVSELCR_TGLEN |
  788. SDHCIOVSELCR_SDHC_VS;
  789. iowrite32be(sdhciovselcr,
  790. scfg_base + SCFG_SDHCIOVSELCR);
  791. iounmap(scfg_base);
  792. } else {
  793. val |= ESDHC_VOLT_SEL;
  794. sdhci_writel(host, val, ESDHC_PROCTL);
  795. }
  796. return 0;
  797. default:
  798. return 0;
  799. }
  800. }
  801. static struct soc_device_attribute soc_tuning_erratum_type1[] = {
  802. { .family = "QorIQ T1023", },
  803. { .family = "QorIQ T1040", },
  804. { .family = "QorIQ T2080", },
  805. { .family = "QorIQ LS1021A", },
  806. { },
  807. };
  808. static struct soc_device_attribute soc_tuning_erratum_type2[] = {
  809. { .family = "QorIQ LS1012A", },
  810. { .family = "QorIQ LS1043A", },
  811. { .family = "QorIQ LS1046A", },
  812. { .family = "QorIQ LS1080A", },
  813. { .family = "QorIQ LS2080A", },
  814. { .family = "QorIQ LA1575A", },
  815. { },
  816. };
  817. static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
  818. {
  819. u32 val;
  820. esdhc_clock_enable(host, false);
  821. esdhc_flush_async_fifo(host);
  822. val = sdhci_readl(host, ESDHC_TBCTL);
  823. if (enable)
  824. val |= ESDHC_TB_EN;
  825. else
  826. val &= ~ESDHC_TB_EN;
  827. sdhci_writel(host, val, ESDHC_TBCTL);
  828. esdhc_clock_enable(host, true);
  829. }
  830. static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start,
  831. u8 *window_end)
  832. {
  833. u32 val;
  834. /* Write TBCTL[11:8]=4'h8 */
  835. val = sdhci_readl(host, ESDHC_TBCTL);
  836. val &= ~(0xf << 8);
  837. val |= 8 << 8;
  838. sdhci_writel(host, val, ESDHC_TBCTL);
  839. mdelay(1);
  840. /* Read TBCTL[31:0] register and rewrite again */
  841. val = sdhci_readl(host, ESDHC_TBCTL);
  842. sdhci_writel(host, val, ESDHC_TBCTL);
  843. mdelay(1);
  844. /* Read the TBSTAT[31:0] register twice */
  845. val = sdhci_readl(host, ESDHC_TBSTAT);
  846. val = sdhci_readl(host, ESDHC_TBSTAT);
  847. *window_end = val & 0xff;
  848. *window_start = (val >> 8) & 0xff;
  849. }
  850. static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start,
  851. u8 *window_end)
  852. {
  853. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  854. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  855. u8 start_ptr, end_ptr;
  856. if (esdhc->quirk_tuning_erratum_type1) {
  857. *window_start = 5 * esdhc->div_ratio;
  858. *window_end = 3 * esdhc->div_ratio;
  859. return;
  860. }
  861. esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr);
  862. /* Reset data lines by setting ESDHCCTL[RSTD] */
  863. sdhci_reset(host, SDHCI_RESET_DATA);
  864. /* Write 32'hFFFF_FFFF to IRQSTAT register */
  865. sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
  866. /* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2
  867. * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2,
  868. * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio
  869. * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio.
  870. */
  871. if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) {
  872. *window_start = 8 * esdhc->div_ratio;
  873. *window_end = 4 * esdhc->div_ratio;
  874. } else {
  875. *window_start = 5 * esdhc->div_ratio;
  876. *window_end = 3 * esdhc->div_ratio;
  877. }
  878. }
  879. static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode,
  880. u8 window_start, u8 window_end)
  881. {
  882. struct sdhci_host *host = mmc_priv(mmc);
  883. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  884. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  885. u32 val;
  886. int ret;
  887. /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */
  888. val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
  889. ESDHC_WNDW_STRT_PTR_MASK;
  890. val |= window_end & ESDHC_WNDW_END_PTR_MASK;
  891. sdhci_writel(host, val, ESDHC_TBPTR);
  892. /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */
  893. val = sdhci_readl(host, ESDHC_TBCTL);
  894. val &= ~ESDHC_TB_MODE_MASK;
  895. val |= ESDHC_TB_MODE_SW;
  896. sdhci_writel(host, val, ESDHC_TBCTL);
  897. esdhc->in_sw_tuning = true;
  898. ret = sdhci_execute_tuning(mmc, opcode);
  899. esdhc->in_sw_tuning = false;
  900. return ret;
  901. }
  902. static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
  903. {
  904. struct sdhci_host *host = mmc_priv(mmc);
  905. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  906. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  907. u8 window_start, window_end;
  908. int ret, retries = 1;
  909. bool hs400_tuning;
  910. unsigned int clk;
  911. u32 val;
  912. /* For tuning mode, the sd clock divisor value
  913. * must be larger than 3 according to reference manual.
  914. */
  915. clk = esdhc->peripheral_clock / 3;
  916. if (host->clock > clk)
  917. esdhc_of_set_clock(host, clk);
  918. esdhc_tuning_block_enable(host, true);
  919. /*
  920. * The eSDHC controller takes the data timeout value into account
  921. * during tuning. If the SD card is too slow sending the response, the
  922. * timer will expire and a "Buffer Read Ready" interrupt without data
  923. * is triggered. This leads to tuning errors.
  924. *
  925. * Just set the timeout to the maximum value because the core will
  926. * already take care of it in sdhci_send_tuning().
  927. */
  928. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  929. hs400_tuning = host->flags & SDHCI_HS400_TUNING;
  930. do {
  931. if (esdhc->quirk_limited_clk_division &&
  932. hs400_tuning)
  933. esdhc_of_set_clock(host, host->clock);
  934. /* Do HW tuning */
  935. val = sdhci_readl(host, ESDHC_TBCTL);
  936. val &= ~ESDHC_TB_MODE_MASK;
  937. val |= ESDHC_TB_MODE_3;
  938. sdhci_writel(host, val, ESDHC_TBCTL);
  939. ret = sdhci_execute_tuning(mmc, opcode);
  940. if (ret)
  941. break;
  942. /* For type2 affected platforms of the tuning erratum,
  943. * tuning may succeed although eSDHC might not have
  944. * tuned properly. Need to check tuning window.
  945. */
  946. if (esdhc->quirk_tuning_erratum_type2 &&
  947. !host->tuning_err) {
  948. esdhc_tuning_window_ptr(host, &window_start,
  949. &window_end);
  950. if (abs(window_start - window_end) >
  951. (4 * esdhc->div_ratio + 2))
  952. host->tuning_err = -EAGAIN;
  953. }
  954. /* If HW tuning fails and triggers erratum,
  955. * try workaround.
  956. */
  957. ret = host->tuning_err;
  958. if (ret == -EAGAIN &&
  959. (esdhc->quirk_tuning_erratum_type1 ||
  960. esdhc->quirk_tuning_erratum_type2)) {
  961. /* Recover HS400 tuning flag */
  962. if (hs400_tuning)
  963. host->flags |= SDHCI_HS400_TUNING;
  964. pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
  965. mmc_hostname(mmc));
  966. /* Do SW tuning */
  967. esdhc_prepare_sw_tuning(host, &window_start,
  968. &window_end);
  969. ret = esdhc_execute_sw_tuning(mmc, opcode,
  970. window_start,
  971. window_end);
  972. if (ret)
  973. break;
  974. /* Retry both HW/SW tuning with reduced clock. */
  975. ret = host->tuning_err;
  976. if (ret == -EAGAIN && retries) {
  977. /* Recover HS400 tuning flag */
  978. if (hs400_tuning)
  979. host->flags |= SDHCI_HS400_TUNING;
  980. clk = host->max_clk / (esdhc->div_ratio + 1);
  981. esdhc_of_set_clock(host, clk);
  982. pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
  983. mmc_hostname(mmc));
  984. } else {
  985. break;
  986. }
  987. } else {
  988. break;
  989. }
  990. } while (retries--);
  991. if (ret) {
  992. esdhc_tuning_block_enable(host, false);
  993. } else if (hs400_tuning) {
  994. val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
  995. val |= ESDHC_FLW_CTL_BG;
  996. sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
  997. }
  998. return ret;
  999. }
  1000. static void esdhc_set_uhs_signaling(struct sdhci_host *host,
  1001. unsigned int timing)
  1002. {
  1003. u32 val;
  1004. /*
  1005. * There are specific registers setting for HS400 mode.
  1006. * Clean all of them if controller is in HS400 mode to
  1007. * exit HS400 mode before re-setting any speed mode.
  1008. */
  1009. val = sdhci_readl(host, ESDHC_TBCTL);
  1010. if (val & ESDHC_HS400_MODE) {
  1011. val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
  1012. val &= ~ESDHC_FLW_CTL_BG;
  1013. sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
  1014. val = sdhci_readl(host, ESDHC_SDCLKCTL);
  1015. val &= ~ESDHC_CMD_CLK_CTL;
  1016. sdhci_writel(host, val, ESDHC_SDCLKCTL);
  1017. esdhc_clock_enable(host, false);
  1018. val = sdhci_readl(host, ESDHC_TBCTL);
  1019. val &= ~ESDHC_HS400_MODE;
  1020. sdhci_writel(host, val, ESDHC_TBCTL);
  1021. esdhc_clock_enable(host, true);
  1022. val = sdhci_readl(host, ESDHC_DLLCFG0);
  1023. val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL);
  1024. sdhci_writel(host, val, ESDHC_DLLCFG0);
  1025. val = sdhci_readl(host, ESDHC_TBCTL);
  1026. val &= ~ESDHC_HS400_WNDW_ADJUST;
  1027. sdhci_writel(host, val, ESDHC_TBCTL);
  1028. esdhc_tuning_block_enable(host, false);
  1029. }
  1030. if (timing == MMC_TIMING_MMC_HS400)
  1031. esdhc_tuning_block_enable(host, true);
  1032. else
  1033. sdhci_set_uhs_signaling(host, timing);
  1034. }
  1035. static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
  1036. {
  1037. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1038. struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  1039. u32 command;
  1040. if (esdhc->quirk_trans_complete_erratum) {
  1041. command = SDHCI_GET_CMD(sdhci_readw(host,
  1042. SDHCI_COMMAND));
  1043. if (command == MMC_WRITE_MULTIPLE_BLOCK &&
  1044. sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
  1045. intmask & SDHCI_INT_DATA_END) {
  1046. intmask &= ~SDHCI_INT_DATA_END;
  1047. sdhci_writel(host, SDHCI_INT_DATA_END,
  1048. SDHCI_INT_STATUS);
  1049. }
  1050. }
  1051. return intmask;
  1052. }
  1053. #ifdef CONFIG_PM_SLEEP
  1054. static u32 esdhc_proctl;
  1055. static int esdhc_of_suspend(struct device *dev)
  1056. {
  1057. struct sdhci_host *host = dev_get_drvdata(dev);
  1058. esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
  1059. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  1060. mmc_retune_needed(host->mmc);
  1061. return sdhci_suspend_host(host);
  1062. }
  1063. static int esdhc_of_resume(struct device *dev)
  1064. {
  1065. struct sdhci_host *host = dev_get_drvdata(dev);
  1066. int ret = sdhci_resume_host(host);
  1067. if (ret == 0) {
  1068. /* Isn't this already done by sdhci_resume_host() ? --rmk */
  1069. esdhc_of_enable_dma(host);
  1070. sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
  1071. }
  1072. return ret;
  1073. }
  1074. #endif
  1075. static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
  1076. esdhc_of_suspend,
  1077. esdhc_of_resume);
  1078. static const struct sdhci_ops sdhci_esdhc_be_ops = {
  1079. .read_l = esdhc_be_readl,
  1080. .read_w = esdhc_be_readw,
  1081. .read_b = esdhc_be_readb,
  1082. .write_l = esdhc_be_writel,
  1083. .write_w = esdhc_be_writew,
  1084. .write_b = esdhc_be_writeb,
  1085. .set_clock = esdhc_of_set_clock,
  1086. .enable_dma = esdhc_of_enable_dma,
  1087. .get_max_clock = esdhc_of_get_max_clock,
  1088. .get_min_clock = esdhc_of_get_min_clock,
  1089. .adma_workaround = esdhc_of_adma_workaround,
  1090. .set_bus_width = esdhc_pltfm_set_bus_width,
  1091. .reset = esdhc_reset,
  1092. .set_uhs_signaling = esdhc_set_uhs_signaling,
  1093. .irq = esdhc_irq,
  1094. };
  1095. static const struct sdhci_ops sdhci_esdhc_le_ops = {
  1096. .read_l = esdhc_le_readl,
  1097. .read_w = esdhc_le_readw,
  1098. .read_b = esdhc_le_readb,
  1099. .write_l = esdhc_le_writel,
  1100. .write_w = esdhc_le_writew,
  1101. .write_b = esdhc_le_writeb,
  1102. .set_clock = esdhc_of_set_clock,
  1103. .enable_dma = esdhc_of_enable_dma,
  1104. .get_max_clock = esdhc_of_get_max_clock,
  1105. .get_min_clock = esdhc_of_get_min_clock,
  1106. .adma_workaround = esdhc_of_adma_workaround,
  1107. .set_bus_width = esdhc_pltfm_set_bus_width,
  1108. .reset = esdhc_reset,
  1109. .set_uhs_signaling = esdhc_set_uhs_signaling,
  1110. .irq = esdhc_irq,
  1111. };
  1112. static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
  1113. .quirks = ESDHC_DEFAULT_QUIRKS |
  1114. #ifdef CONFIG_PPC
  1115. SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  1116. #endif
  1117. SDHCI_QUIRK_NO_CARD_NO_RESET |
  1118. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  1119. .ops = &sdhci_esdhc_be_ops,
  1120. };
  1121. static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
  1122. .quirks = ESDHC_DEFAULT_QUIRKS |
  1123. SDHCI_QUIRK_NO_CARD_NO_RESET |
  1124. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  1125. .ops = &sdhci_esdhc_le_ops,
  1126. };
  1127. static struct soc_device_attribute soc_incorrect_hostver[] = {
  1128. { .family = "QorIQ T4240", .revision = "1.0", },
  1129. { .family = "QorIQ T4240", .revision = "2.0", },
  1130. { },
  1131. };
  1132. static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
  1133. { .family = "QorIQ LX2160A", .revision = "1.0", },
  1134. { .family = "QorIQ LX2160A", .revision = "2.0", },
  1135. { .family = "QorIQ LS1028A", .revision = "1.0", },
  1136. { },
  1137. };
  1138. static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
  1139. { .family = "QorIQ LX2160A", .revision = "1.0", },
  1140. { .family = "QorIQ LX2160A", .revision = "2.0", },
  1141. { .family = "QorIQ LS1028A", .revision = "1.0", },
  1142. { },
  1143. };
  1144. static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
  1145. {
  1146. const struct of_device_id *match;
  1147. struct sdhci_pltfm_host *pltfm_host;
  1148. struct sdhci_esdhc *esdhc;
  1149. struct device_node *np;
  1150. struct clk *clk;
  1151. u32 val;
  1152. u16 host_ver;
  1153. pltfm_host = sdhci_priv(host);
  1154. esdhc = sdhci_pltfm_priv(pltfm_host);
  1155. host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
  1156. esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
  1157. SDHCI_VENDOR_VER_SHIFT;
  1158. esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
  1159. if (soc_device_match(soc_incorrect_hostver))
  1160. esdhc->quirk_incorrect_hostver = true;
  1161. else
  1162. esdhc->quirk_incorrect_hostver = false;
  1163. if (soc_device_match(soc_fixup_sdhc_clkdivs))
  1164. esdhc->quirk_limited_clk_division = true;
  1165. else
  1166. esdhc->quirk_limited_clk_division = false;
  1167. if (soc_device_match(soc_unreliable_pulse_detection))
  1168. esdhc->quirk_unreliable_pulse_detection = true;
  1169. else
  1170. esdhc->quirk_unreliable_pulse_detection = false;
  1171. match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
  1172. if (match)
  1173. esdhc->clk_fixup = match->data;
  1174. np = pdev->dev.of_node;
  1175. if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
  1176. esdhc->quirk_delay_before_data_reset = true;
  1177. esdhc->quirk_trans_complete_erratum = true;
  1178. }
  1179. clk = of_clk_get(np, 0);
  1180. if (!IS_ERR(clk)) {
  1181. /*
  1182. * esdhc->peripheral_clock would be assigned with a value
  1183. * which is eSDHC base clock when use periperal clock.
  1184. * For some platforms, the clock value got by common clk
  1185. * API is peripheral clock while the eSDHC base clock is
  1186. * 1/2 peripheral clock.
  1187. */
  1188. if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
  1189. of_device_is_compatible(np, "fsl,ls1028a-esdhc") ||
  1190. of_device_is_compatible(np, "fsl,ls1088a-esdhc"))
  1191. esdhc->peripheral_clock = clk_get_rate(clk) / 2;
  1192. else
  1193. esdhc->peripheral_clock = clk_get_rate(clk);
  1194. clk_put(clk);
  1195. }
  1196. esdhc_clock_enable(host, false);
  1197. val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
  1198. /*
  1199. * This bit is not able to be reset by SDHCI_RESET_ALL. Need to
  1200. * initialize it as 1 or 0 once, to override the different value
  1201. * which may be configured in bootloader.
  1202. */
  1203. if (esdhc->peripheral_clock)
  1204. val |= ESDHC_PERIPHERAL_CLK_SEL;
  1205. else
  1206. val &= ~ESDHC_PERIPHERAL_CLK_SEL;
  1207. sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
  1208. esdhc_clock_enable(host, true);
  1209. }
  1210. static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
  1211. {
  1212. esdhc_tuning_block_enable(mmc_priv(mmc), false);
  1213. return 0;
  1214. }
  1215. static int sdhci_esdhc_probe(struct platform_device *pdev)
  1216. {
  1217. struct sdhci_host *host;
  1218. struct device_node *np;
  1219. struct sdhci_pltfm_host *pltfm_host;
  1220. struct sdhci_esdhc *esdhc;
  1221. int ret;
  1222. np = pdev->dev.of_node;
  1223. if (of_property_read_bool(np, "little-endian"))
  1224. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
  1225. sizeof(struct sdhci_esdhc));
  1226. else
  1227. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
  1228. sizeof(struct sdhci_esdhc));
  1229. if (IS_ERR(host))
  1230. return PTR_ERR(host);
  1231. host->mmc_host_ops.start_signal_voltage_switch =
  1232. esdhc_signal_voltage_switch;
  1233. host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
  1234. host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
  1235. host->tuning_delay = 1;
  1236. esdhc_init(pdev, host);
  1237. sdhci_get_of_property(pdev);
  1238. pltfm_host = sdhci_priv(host);
  1239. esdhc = sdhci_pltfm_priv(pltfm_host);
  1240. if (soc_device_match(soc_tuning_erratum_type1))
  1241. esdhc->quirk_tuning_erratum_type1 = true;
  1242. else
  1243. esdhc->quirk_tuning_erratum_type1 = false;
  1244. if (soc_device_match(soc_tuning_erratum_type2))
  1245. esdhc->quirk_tuning_erratum_type2 = true;
  1246. else
  1247. esdhc->quirk_tuning_erratum_type2 = false;
  1248. if (esdhc->vendor_ver == VENDOR_V_22)
  1249. host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
  1250. if (esdhc->vendor_ver > VENDOR_V_22)
  1251. host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
  1252. if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
  1253. host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
  1254. host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
  1255. }
  1256. if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
  1257. of_device_is_compatible(np, "fsl,p5020-esdhc") ||
  1258. of_device_is_compatible(np, "fsl,p4080-esdhc") ||
  1259. of_device_is_compatible(np, "fsl,p1020-esdhc") ||
  1260. of_device_is_compatible(np, "fsl,t1040-esdhc"))
  1261. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  1262. if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
  1263. host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
  1264. esdhc->quirk_ignore_data_inhibit = false;
  1265. if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
  1266. /*
  1267. * Freescale messed up with P2020 as it has a non-standard
  1268. * host control register
  1269. */
  1270. host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
  1271. esdhc->quirk_ignore_data_inhibit = true;
  1272. }
  1273. /* call to generic mmc_of_parse to support additional capabilities */
  1274. ret = mmc_of_parse(host->mmc);
  1275. if (ret)
  1276. goto err;
  1277. mmc_of_parse_voltage(np, &host->ocr_mask);
  1278. ret = sdhci_add_host(host);
  1279. if (ret)
  1280. goto err;
  1281. return 0;
  1282. err:
  1283. sdhci_pltfm_free(pdev);
  1284. return ret;
  1285. }
  1286. static struct platform_driver sdhci_esdhc_driver = {
  1287. .driver = {
  1288. .name = "sdhci-esdhc",
  1289. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1290. .of_match_table = sdhci_esdhc_of_match,
  1291. .pm = &esdhc_of_dev_pm_ops,
  1292. },
  1293. .probe = sdhci_esdhc_probe,
  1294. .remove = sdhci_pltfm_unregister,
  1295. };
  1296. module_platform_driver(sdhci_esdhc_driver);
  1297. MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
  1298. MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
  1299. "Anton Vorontsov <avorontsov@ru.mvista.com>");
  1300. MODULE_LICENSE("GPL v2");