sdhci-of-dwcmshc.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
  4. *
  5. * Copyright (C) 2018 Synaptics Incorporated
  6. *
  7. * Author: Jisheng Zhang <jszhang@kernel.org>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/sizes.h>
  15. #include <linux/delay.h>
  16. #include "sdhci-pltfm.h"
  17. #include "sdhci-of-dwcmshc.h"
  18. #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
  19. /* DWCMSHC specific Mode Select value */
  20. #define DWCMSHC_CTRL_HS400 0x7
  21. #define BOUNDARY_OK(addr, len) \
  22. ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
  23. struct dwcmshc_priv {
  24. struct clk *bus_clk;
  25. void __iomem *soc_base;
  26. bool is_emmc_card;
  27. bool pull_up_en;
  28. bool io_fixed_1v8;
  29. bool wprtn_ignore;
  30. long reset_cnt;
  31. };
  32. #define HS400_DELAY_LINE 24
  33. static uint32_t delay_line = 50;
  34. static void sdhci_phy_1_8v_init_no_pull(struct sdhci_host *host)
  35. {
  36. uint32_t val;
  37. sdhci_writel(host, 1, DWC_MSHC_PTR_PHY_R);
  38. sdhci_writeb(host, 1 << 4, PHY_SDCLKDL_CNFG_R);
  39. sdhci_writeb(host, 0x40, PHY_SDCLKDL_DC_R);
  40. val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
  41. val &= ~(1 << 4);
  42. sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
  43. val = sdhci_readw(host, PHY_CMDPAD_CNFG_R);
  44. sdhci_writew(host, val | 1, PHY_CMDPAD_CNFG_R);
  45. val = sdhci_readw(host, PHY_DATAPAD_CNFG_R);
  46. sdhci_writew(host, val | 1, PHY_DATAPAD_CNFG_R);
  47. val = sdhci_readw(host, PHY_RSTNPAD_CNFG_R);
  48. sdhci_writew(host, val | 1, PHY_RSTNPAD_CNFG_R);
  49. val = sdhci_readw(host, PHY_STBPAD_CNFG_R);
  50. sdhci_writew(host, val | 1, PHY_STBPAD_CNFG_R);
  51. val = sdhci_readb(host, PHY_DLL_CTRL_R);
  52. sdhci_writeb(host, val | 1, PHY_DLL_CTRL_R);
  53. }
  54. static void sdhci_phy_3_3v_init_no_pull(struct sdhci_host *host)
  55. {
  56. uint32_t val;
  57. sdhci_writel(host, 1, DWC_MSHC_PTR_PHY_R);
  58. sdhci_writeb(host, 1 << 4, PHY_SDCLKDL_CNFG_R);
  59. sdhci_writeb(host, 0x40, PHY_SDCLKDL_DC_R);
  60. val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
  61. val &= ~(1 << 4);
  62. sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
  63. val = sdhci_readw(host, PHY_CMDPAD_CNFG_R);
  64. sdhci_writew(host, val | 2, PHY_CMDPAD_CNFG_R);
  65. val = sdhci_readw(host, PHY_DATAPAD_CNFG_R);
  66. sdhci_writew(host, val | 2, PHY_DATAPAD_CNFG_R);
  67. val = sdhci_readw(host, PHY_RSTNPAD_CNFG_R);
  68. sdhci_writew(host, val | 2, PHY_RSTNPAD_CNFG_R);
  69. val = sdhci_readw(host, PHY_STBPAD_CNFG_R);
  70. sdhci_writew(host, val | 2, PHY_STBPAD_CNFG_R);
  71. val = sdhci_readb(host, PHY_DLL_CTRL_R);
  72. sdhci_writeb(host, val | 1, PHY_DLL_CTRL_R);
  73. }
  74. static void snps_phy_1_8v_init(struct sdhci_host *host)
  75. {
  76. struct sdhci_pltfm_host *pltfm_host;
  77. struct dwcmshc_priv *priv;
  78. u32 val;
  79. pltfm_host = sdhci_priv(host);
  80. priv = sdhci_pltfm_priv(pltfm_host);
  81. if (priv->pull_up_en == 0) {
  82. sdhci_phy_1_8v_init_no_pull(host);
  83. return;
  84. }
  85. //set driving force
  86. sdhci_writel(host, (1 << PHY_RSTN) | (0xc << PAD_SP) | (0xc << PAD_SN), PHY_CNFG_R);
  87. //disable delay lane
  88. sdhci_writeb(host, 1 << UPDATE_DC, PHY_SDCLKDL_CNFG_R);
  89. //set delay lane
  90. sdhci_writeb(host, delay_line, PHY_SDCLKDL_DC_R);
  91. sdhci_writeb(host, 0xa, PHY_DLL_CNFG2_R);
  92. //enable delay lane
  93. val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
  94. val &= ~(1 << UPDATE_DC);
  95. sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
  96. val = (1 << RXSEL) | (1 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N);
  97. sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
  98. sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
  99. sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
  100. val = (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N);
  101. sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
  102. val = (1 << RXSEL) | (2 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N);
  103. sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
  104. /* enable data strobe mode */
  105. sdhci_writeb(host, 3 << SLV_INPSEL, PHY_DLLDL_CNFG_R);
  106. sdhci_writeb(host, (1 << DLL_EN), PHY_DLL_CTRL_R);
  107. }
  108. static void snps_phy_3_3v_init(struct sdhci_host *host)
  109. {
  110. struct sdhci_pltfm_host *pltfm_host;
  111. struct dwcmshc_priv *priv;
  112. u32 val;
  113. pltfm_host = sdhci_priv(host);
  114. priv = sdhci_pltfm_priv(pltfm_host);
  115. if (priv->pull_up_en == 0) {
  116. sdhci_phy_3_3v_init_no_pull(host);
  117. return;
  118. }
  119. //set driving force
  120. sdhci_writel(host, (1 << PHY_RSTN) | (0xc << PAD_SP) | (0xc << PAD_SN), PHY_CNFG_R);
  121. //disable delay lane
  122. sdhci_writeb(host, 1 << UPDATE_DC, PHY_SDCLKDL_CNFG_R);
  123. //set delay lane
  124. sdhci_writeb(host, delay_line, PHY_SDCLKDL_DC_R);
  125. sdhci_writeb(host, 0xa, PHY_DLL_CNFG2_R);
  126. //enable delay lane
  127. val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
  128. val &= ~(1 << UPDATE_DC);
  129. sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
  130. val = (2 << RXSEL) | (1 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N);
  131. sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
  132. sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
  133. sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
  134. val = (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N);
  135. sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
  136. val = (2 << RXSEL) | (2 << WEAKPULL_EN) | (3 << TXSLEW_CTRL_P) | (3 << TXSLEW_CTRL_N);
  137. sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
  138. }
  139. static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
  140. {
  141. #define DW_SDHCI_TUNING_LOOP_COUNT 128
  142. int i;
  143. /*
  144. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  145. * of loops reaches tuning loop count.
  146. */
  147. for (i = 0; i < DW_SDHCI_TUNING_LOOP_COUNT; i++) {
  148. u16 ctrl;
  149. sdhci_send_tuning(host, opcode);
  150. if (!host->tuning_done) {
  151. pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
  152. mmc_hostname(host->mmc));
  153. sdhci_abort_tuning(host, opcode);
  154. return -ETIMEDOUT;
  155. }
  156. /* Spec does not require a delay between tuning cycles */
  157. if (host->tuning_delay > 0)
  158. mdelay(host->tuning_delay);
  159. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  160. if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
  161. if (ctrl & SDHCI_CTRL_TUNED_CLK)
  162. return 0; /* Success! */
  163. break;
  164. }
  165. }
  166. pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
  167. mmc_hostname(host->mmc));
  168. printk("%s: Tuning failed, falling back to fixed sampling clock\n",
  169. mmc_hostname(host->mmc));
  170. sdhci_reset_tuning(host);
  171. return -EAGAIN;
  172. }
  173. static int snps_execute_tuning(struct sdhci_host *host, u32 opcode)
  174. {
  175. u32 val = 0;
  176. if (host->flags & SDHCI_HS400_TUNING) {
  177. return 0;
  178. }
  179. sdhci_writeb(host, 3 << INPSEL_CNFG, PHY_ATDL_CNFG_R);
  180. val = sdhci_readl(host, AT_CTRL_R);
  181. val &= ~((1 << CI_SEL) | (1 << RPT_TUNE_ERR)\
  182. | (1 << SW_TUNE_EN) |(0xf << WIN_EDGE_SEL));
  183. val |= (1 << AT_EN) | (1 << SWIN_TH_EN) | (1 << TUNE_CLK_STOP_EN)\
  184. | (1 << PRE_CHANGE_DLY) | (3 << POST_CHANGE_DLY) | (9 << SWIN_TH_VAL);
  185. sdhci_writel(host, val, AT_CTRL_R);
  186. val = sdhci_readl(host, AT_CTRL_R);
  187. if(!(val & (1 << AT_EN))) {
  188. pr_err("*****Auto Tuning is NOT Enable!!!\n");
  189. return -1;
  190. }
  191. val &= ~(1 << AT_EN);
  192. sdhci_writel(host, val, AT_CTRL_R);
  193. sdhci_start_tuning(host);
  194. host->tuning_err = __sdhci_execute_tuning(host, opcode);
  195. if (host->tuning_err) {
  196. val &= ~(1 << AT_EN);
  197. sdhci_writel(host, val, AT_CTRL_R);
  198. return -1;
  199. }
  200. sdhci_end_tuning(host);
  201. return 0;
  202. }
  203. static void snps_sdhci_set_phy(struct sdhci_host *host)
  204. {
  205. struct sdhci_pltfm_host *pltfm_host;
  206. struct dwcmshc_priv *priv;
  207. u8 emmc_ctl;
  208. pltfm_host = sdhci_priv(host);
  209. priv = sdhci_pltfm_priv(pltfm_host);
  210. /*Before power on,set PHY configs*/
  211. emmc_ctl = sdhci_readw(host, EMMC_CTRL_R);
  212. if (priv->is_emmc_card) {
  213. snps_phy_1_8v_init(host);
  214. emmc_ctl |= (1 << CARD_IS_EMMC);
  215. } else {
  216. snps_phy_3_3v_init(host);
  217. emmc_ctl &=~(1 << CARD_IS_EMMC);
  218. }
  219. sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R);
  220. sdhci_writeb(host, 0x25, PHY_DLL_CNFG1_R);
  221. }
  222. static void snps_sdhci_reset(struct sdhci_host *host, u8 mask)
  223. {
  224. struct sdhci_pltfm_host *pltfm_host;
  225. struct dwcmshc_priv *priv;
  226. u16 ctrl_2;
  227. pltfm_host = sdhci_priv(host);
  228. priv = sdhci_pltfm_priv(pltfm_host);
  229. /*soc reset, fix host reset error*/
  230. //soc_reg = readl( priv->soc_base);
  231. //soc_reg &= ~1;
  232. //writel(soc_reg, priv->soc_base);
  233. //soc_reg |= 1;
  234. //writel(soc_reg, priv->soc_base);
  235. /*host reset*/
  236. sdhci_reset(host, mask);
  237. /* Before phy reset,set io voltage to fixed to 1v8.
  238. * For mask is SDHCI_RESET_ALL,regs will reset to default val.
  239. */
  240. if(priv->io_fixed_1v8){
  241. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  242. if(! (ctrl_2 & SDHCI_CTRL_VDD_180)){
  243. ctrl_2 |= SDHCI_CTRL_VDD_180;
  244. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  245. }
  246. }
  247. ++(priv->reset_cnt);
  248. pr_debug("%s: sdhci reset cnt %ld\n",host->hw_name,priv->reset_cnt);
  249. }
  250. /*
  251. * If DMA addr spans 128MB boundary, we split the DMA transfer into two
  252. * so that each DMA transfer doesn't exceed the boundary.
  253. */
  254. static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
  255. dma_addr_t addr, int len, unsigned int cmd)
  256. {
  257. int tmplen, offset;
  258. if (likely(!len || BOUNDARY_OK(addr, len))) {
  259. sdhci_adma_write_desc(host, desc, addr, len, cmd);
  260. return;
  261. }
  262. offset = addr & (SZ_128M - 1);
  263. tmplen = SZ_128M - offset;
  264. sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
  265. addr += tmplen;
  266. len -= tmplen;
  267. sdhci_adma_write_desc(host, desc, addr, len, cmd);
  268. }
  269. static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
  270. struct mmc_request *mrq)
  271. {
  272. struct sdhci_host *host = mmc_priv(mmc);
  273. /*
  274. * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
  275. * block count register which doesn't support stuff bits of
  276. * CMD23 argument on dwcmsch host controller.
  277. */
  278. if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
  279. host->flags &= ~SDHCI_AUTO_CMD23;
  280. else
  281. host->flags |= SDHCI_AUTO_CMD23;
  282. }
  283. static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  284. {
  285. dwcmshc_check_auto_cmd23(mmc, mrq);
  286. sdhci_request(mmc, mrq);
  287. }
  288. static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
  289. unsigned int timing)
  290. {
  291. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  292. struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
  293. u16 ctrl_2;
  294. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  295. /* Select Bus Speed Mode for host */
  296. ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
  297. if ((timing == MMC_TIMING_MMC_HS200) ||
  298. (timing == MMC_TIMING_UHS_SDR104))
  299. ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
  300. else if (timing == MMC_TIMING_UHS_SDR12)
  301. ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
  302. else if ((timing == MMC_TIMING_UHS_SDR25) ||
  303. (timing == MMC_TIMING_MMC_HS))
  304. ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
  305. else if (timing == MMC_TIMING_UHS_SDR50)
  306. ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
  307. else if ((timing == MMC_TIMING_UHS_DDR50) ||
  308. (timing == MMC_TIMING_MMC_DDR52))
  309. ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
  310. else if (timing == MMC_TIMING_MMC_HS400)
  311. ctrl_2 |= DWCMSHC_CTRL_HS400;
  312. if (priv->io_fixed_1v8)
  313. ctrl_2 |= SDHCI_CTRL_VDD_180;
  314. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  315. if (timing == MMC_TIMING_MMC_HS400) {
  316. // //disable delay lane
  317. // sdhci_writeb(host, 1 << UPDATE_DC, PHY_SDCLKDL_CNFG_R);
  318. // //set delay lane
  319. // sdhci_writeb(host, delay_line, PHY_SDCLKDL_DC_R);
  320. // //enable delay lane
  321. // reg = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
  322. // reg &= ~(1 << UPDATE_DC);
  323. // sdhci_writeb(host, reg, PHY_SDCLKDL_CNFG_R);
  324. //disable auto tuning
  325. u32 reg = sdhci_readl(host, AT_CTRL_R);
  326. reg &= ~1;
  327. sdhci_writel(host, reg, AT_CTRL_R);
  328. delay_line = HS400_DELAY_LINE;
  329. snps_sdhci_set_phy(host); /* update tx delay*/
  330. } else {
  331. sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
  332. }
  333. }
  334. static unsigned int dwcmshc_pltfm_get_ro(struct sdhci_host *host)
  335. {
  336. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  337. struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
  338. int is_readonly;
  339. if (priv->wprtn_ignore)
  340. return 0;
  341. is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
  342. & SDHCI_WRITE_PROTECT);
  343. return is_readonly;
  344. }
  345. /* Complete selection of HS400 ,software reset DAT & cmd line
  346. * resolve for first time data access error(time out) when
  347. * first swith to hs400 mode.
  348. *
  349. * From : SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
  350. * Some (ENE) controllers go apeshit on some ios operation,
  351. * signalling timeout and CRC errors even on CMD0. Resetting
  352. * it on each ios seems to solve the problem.
  353. *
  354. */
  355. static void dwcmshc_hs400_complete(struct mmc_host *mmc)
  356. {
  357. struct sdhci_host *host = mmc_priv(mmc);
  358. u8 mask = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
  359. if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
  360. if (!mmc->ops->get_cd(mmc))
  361. return;
  362. }
  363. snps_sdhci_reset(host,mask);
  364. //host->ops->reset(host, mask);
  365. }
  366. static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
  367. unsigned short vdd)
  368. {
  369. struct mmc_host *mmc = host->mmc;
  370. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
  371. if (mode != MMC_POWER_OFF)
  372. sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
  373. else
  374. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  375. }
  376. /* Add snps_sdhci_set_phy before POWER ON for this controller.
  377. * Similar to public sdhci.c sdhci_set_power_noreg().
  378. */
  379. static void dwcmshc_set_power_noreg(struct sdhci_host *host, unsigned char mode,
  380. unsigned short vdd)
  381. {
  382. u8 pwr = 0;
  383. if (mode != MMC_POWER_OFF) {
  384. switch (1 << vdd) {
  385. case MMC_VDD_165_195:
  386. /*
  387. * Without a regulator, SDHCI does not support 2.0v
  388. * so we only get here if the driver deliberately
  389. * added the 2.0v range to ocr_avail. Map it to 1.8v
  390. * for the purpose of turning on the power.
  391. */
  392. case MMC_VDD_20_21:
  393. pwr = SDHCI_POWER_180;
  394. break;
  395. case MMC_VDD_29_30:
  396. case MMC_VDD_30_31:
  397. pwr = SDHCI_POWER_300;
  398. break;
  399. case MMC_VDD_32_33:
  400. case MMC_VDD_33_34:
  401. /*
  402. * 3.4 ~ 3.6V are valid only for those platforms where it's
  403. * known that the voltage range is supported by hardware.
  404. */
  405. case MMC_VDD_34_35:
  406. case MMC_VDD_35_36:
  407. pwr = SDHCI_POWER_330;
  408. break;
  409. default:
  410. WARN(1, "%s: Invalid vdd %#x\n",
  411. mmc_hostname(host->mmc), vdd);
  412. break;
  413. }
  414. }
  415. if (host->pwr == pwr)
  416. return;
  417. host->pwr = pwr;
  418. snps_sdhci_set_phy(host);
  419. if (pwr == 0) {
  420. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  421. /*
  422. if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
  423. sdhci_runtime_pm_bus_off(host);
  424. */
  425. } else {
  426. /*
  427. * Spec says that we should clear the power reg before setting
  428. * a new value. Some controllers don't seem to like this though.
  429. */
  430. if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
  431. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  432. /*
  433. * At least the Marvell CaFe chip gets confused if we set the
  434. * voltage and set turn on power at the same time, so set the
  435. * voltage first.
  436. */
  437. if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
  438. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  439. pwr |= SDHCI_POWER_ON;
  440. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  441. /*
  442. if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
  443. sdhci_runtime_pm_bus_on(host);
  444. */
  445. /*
  446. * Some controllers need an extra 10ms delay of 10ms before
  447. * they can apply clock after applying power
  448. */
  449. if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
  450. mdelay(10);
  451. }
  452. }
  453. static void dwcmshc_set_power(struct sdhci_host *host, unsigned char mode,
  454. unsigned short vdd)
  455. {
  456. if (IS_ERR(host->mmc->supply.vmmc))
  457. dwcmshc_set_power_noreg(host, mode, vdd);
  458. else
  459. sdhci_set_power_reg(host, mode, vdd);
  460. }
  461. static const struct sdhci_ops sdhci_dwcmshc_ops = {
  462. .set_clock = sdhci_set_clock,
  463. .set_power = dwcmshc_set_power,
  464. .set_bus_width = sdhci_set_bus_width,
  465. .set_uhs_signaling = dwcmshc_set_uhs_signaling,
  466. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  467. .get_ro = dwcmshc_pltfm_get_ro,
  468. .reset = snps_sdhci_reset,
  469. .adma_write_desc = dwcmshc_adma_write_desc,
  470. .voltage_switch = snps_phy_1_8v_init,
  471. .platform_execute_tuning = &snps_execute_tuning,
  472. };
  473. static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
  474. .ops = &sdhci_dwcmshc_ops,
  475. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_SINGLE_POWER_WRITE,
  476. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  477. };
  478. static int dwcmshc_probe(struct platform_device *pdev)
  479. {
  480. struct sdhci_pltfm_host *pltfm_host;
  481. struct sdhci_host *host;
  482. struct dwcmshc_priv *priv;
  483. int err;
  484. u32 extra;
  485. host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata,
  486. sizeof(struct dwcmshc_priv));
  487. if (IS_ERR(host))
  488. return PTR_ERR(host);
  489. /*
  490. * extra adma table cnt for cross 128M boundary handling.
  491. */
  492. extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
  493. if (extra > SDHCI_MAX_SEGS)
  494. extra = SDHCI_MAX_SEGS;
  495. host->adma_table_cnt += extra;
  496. host->v4_mode = true;
  497. pltfm_host = sdhci_priv(host);
  498. priv = sdhci_pltfm_priv(pltfm_host);
  499. /*used fix sdhci reset error*/
  500. priv->soc_base = devm_platform_ioremap_resource(pdev, 1);
  501. if (device_property_present(&pdev->dev, "is_emmc")) {
  502. priv->is_emmc_card = 1;
  503. } else {
  504. priv->is_emmc_card = 0;
  505. }
  506. if (device_property_present(&pdev->dev, "pull_up")) {
  507. priv->pull_up_en = 1;
  508. } else {
  509. priv->pull_up_en = 0;
  510. }
  511. if (device_property_present(&pdev->dev, "io_fixed_1v8"))
  512. priv->io_fixed_1v8 = true;
  513. else
  514. priv->io_fixed_1v8 = false;
  515. /* start_signal_voltage_switch will try 3V3 first, when io fixed 1V8,
  516. * use SDHCI_SIGNALING_180 ranther than SDHCI_SIGNALING_330 to avoid set to 3V3
  517. * in sdhci_start_signal_voltage_switch.
  518. */
  519. if(priv->io_fixed_1v8){
  520. host->flags &=~SDHCI_SIGNALING_330;
  521. host->flags |= SDHCI_SIGNALING_180;
  522. }
  523. if (device_property_present(&pdev->dev, "wprtn_ignore"))
  524. priv->wprtn_ignore = true;
  525. else
  526. priv->wprtn_ignore = false;
  527. pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
  528. if (IS_ERR(pltfm_host->clk)) {
  529. err = PTR_ERR(pltfm_host->clk);
  530. dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
  531. goto free_pltfm;
  532. }
  533. err = clk_prepare_enable(pltfm_host->clk);
  534. if (err)
  535. goto free_pltfm;
  536. priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
  537. if (!IS_ERR(priv->bus_clk))
  538. clk_prepare_enable(priv->bus_clk);
  539. err = mmc_of_parse(host->mmc);
  540. if (err)
  541. goto err_clk;
  542. sdhci_get_of_property(pdev);
  543. host->mmc_host_ops.request = dwcmshc_request;
  544. host->mmc_host_ops.hs400_complete = dwcmshc_hs400_complete;
  545. err = sdhci_add_host(host);
  546. if (err)
  547. goto err_clk;
  548. return 0;
  549. err_clk:
  550. clk_disable_unprepare(pltfm_host->clk);
  551. clk_disable_unprepare(priv->bus_clk);
  552. free_pltfm:
  553. sdhci_pltfm_free(pdev);
  554. return err;
  555. }
  556. static int dwcmshc_remove(struct platform_device *pdev)
  557. {
  558. struct sdhci_host *host = platform_get_drvdata(pdev);
  559. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  560. struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
  561. sdhci_remove_host(host, 0);
  562. clk_disable_unprepare(pltfm_host->clk);
  563. clk_disable_unprepare(priv->bus_clk);
  564. sdhci_pltfm_free(pdev);
  565. return 0;
  566. }
  567. #ifdef CONFIG_PM_SLEEP
  568. static int dwcmshc_suspend(struct device *dev)
  569. {
  570. struct sdhci_host *host = dev_get_drvdata(dev);
  571. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  572. struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
  573. int ret;
  574. ret = sdhci_suspend_host(host);
  575. if (ret)
  576. return ret;
  577. clk_disable_unprepare(pltfm_host->clk);
  578. if (!IS_ERR(priv->bus_clk))
  579. clk_disable_unprepare(priv->bus_clk);
  580. return ret;
  581. }
  582. static int dwcmshc_resume(struct device *dev)
  583. {
  584. struct sdhci_host *host = dev_get_drvdata(dev);
  585. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  586. struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
  587. int ret;
  588. ret = clk_prepare_enable(pltfm_host->clk);
  589. if (ret)
  590. return ret;
  591. if (!IS_ERR(priv->bus_clk)) {
  592. ret = clk_prepare_enable(priv->bus_clk);
  593. if (ret)
  594. return ret;
  595. }
  596. return sdhci_resume_host(host);
  597. }
  598. #endif
  599. static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
  600. static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
  601. { .compatible = "snps,dwcmshc-sdhci" },
  602. {}
  603. };
  604. MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
  605. static struct platform_driver sdhci_dwcmshc_driver = {
  606. .driver = {
  607. .name = "sdhci-dwcmshc",
  608. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  609. .of_match_table = sdhci_dwcmshc_dt_ids,
  610. .pm = &dwcmshc_pmops,
  611. },
  612. .probe = dwcmshc_probe,
  613. .remove = dwcmshc_remove,
  614. };
  615. module_platform_driver(sdhci_dwcmshc_driver);
  616. MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
  617. MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
  618. MODULE_LICENSE("GPL v2");