sdhci-of-arasan.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Arasan Secure Digital Host Controller Interface.
  4. * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
  5. * Copyright (c) 2012 Wind River Systems, Inc.
  6. * Copyright (C) 2013 Pengutronix e.K.
  7. * Copyright (C) 2013 Xilinx Inc.
  8. *
  9. * Based on sdhci-of-esdhc.c
  10. *
  11. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  12. * Copyright (c) 2009 MontaVista Software, Inc.
  13. *
  14. * Authors: Xiaobo Xie <X.Xie@freescale.com>
  15. * Anton Vorontsov <avorontsov@ru.mvista.com>
  16. */
  17. #include <linux/clk-provider.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/phy/phy.h>
  22. #include <linux/regmap.h>
  23. #include <linux/of.h>
  24. #include <linux/firmware/xlnx-zynqmp.h>
  25. #include "cqhci.h"
  26. #include "sdhci-pltfm.h"
  27. #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
  28. #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
  29. #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
  30. #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
  31. #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
  32. #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
  33. #define VENDOR_ENHANCED_STROBE BIT(0)
  34. #define PHY_CLK_TOO_SLOW_HZ 400000
  35. #define SDHCI_ITAPDLY_CHGWIN 0x200
  36. #define SDHCI_ITAPDLY_ENABLE 0x100
  37. #define SDHCI_OTAPDLY_ENABLE 0x40
  38. /* Default settings for ZynqMP Clock Phases */
  39. #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
  40. #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
  41. #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
  42. #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
  43. /*
  44. * On some SoCs the syscon area has a feature where the upper 16-bits of
  45. * each 32-bit register act as a write mask for the lower 16-bits. This allows
  46. * atomic updates of the register without locking. This macro is used on SoCs
  47. * that have that feature.
  48. */
  49. #define HIWORD_UPDATE(val, mask, shift) \
  50. ((val) << (shift) | (mask) << ((shift) + 16))
  51. /**
  52. * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
  53. *
  54. * @reg: Offset within the syscon of the register containing this field
  55. * @width: Number of bits for this field
  56. * @shift: Bit offset within @reg of this field (or -1 if not avail)
  57. */
  58. struct sdhci_arasan_soc_ctl_field {
  59. u32 reg;
  60. u16 width;
  61. s16 shift;
  62. };
  63. /**
  64. * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
  65. *
  66. * @baseclkfreq: Where to find corecfg_baseclkfreq
  67. * @clockmultiplier: Where to find corecfg_clockmultiplier
  68. * @support64b: Where to find SUPPORT64B bit
  69. * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
  70. *
  71. * It's up to the licensee of the Arsan IP block to make these available
  72. * somewhere if needed. Presumably these will be scattered somewhere that's
  73. * accessible via the syscon API.
  74. */
  75. struct sdhci_arasan_soc_ctl_map {
  76. struct sdhci_arasan_soc_ctl_field baseclkfreq;
  77. struct sdhci_arasan_soc_ctl_field clockmultiplier;
  78. struct sdhci_arasan_soc_ctl_field support64b;
  79. bool hiword_update;
  80. };
  81. /**
  82. * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
  83. *
  84. * @sdcardclk_ops: The output clock related operations
  85. * @sampleclk_ops: The sample clock related operations
  86. */
  87. struct sdhci_arasan_clk_ops {
  88. const struct clk_ops *sdcardclk_ops;
  89. const struct clk_ops *sampleclk_ops;
  90. };
  91. /**
  92. * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
  93. *
  94. * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
  95. * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
  96. * @sampleclk_hw: Struct for the clock we might provide to a PHY.
  97. * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
  98. * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
  99. * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
  100. * @set_clk_delays: Function pointer for setting Clock Delays
  101. * @clk_of_data: Platform specific runtime clock data storage pointer
  102. */
  103. struct sdhci_arasan_clk_data {
  104. struct clk_hw sdcardclk_hw;
  105. struct clk *sdcardclk;
  106. struct clk_hw sampleclk_hw;
  107. struct clk *sampleclk;
  108. int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  109. int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  110. void (*set_clk_delays)(struct sdhci_host *host);
  111. void *clk_of_data;
  112. };
  113. /**
  114. * struct sdhci_arasan_data - Arasan Controller Data
  115. *
  116. * @host: Pointer to the main SDHCI host structure.
  117. * @clk_ahb: Pointer to the AHB clock
  118. * @phy: Pointer to the generic phy
  119. * @is_phy_on: True if the PHY is on; false if not.
  120. * @has_cqe: True if controller has command queuing engine.
  121. * @clk_data: Struct for the Arasan Controller Clock Data.
  122. * @clk_ops: Struct for the Arasan Controller Clock Operations.
  123. * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
  124. * @soc_ctl_map: Map to get offsets into soc_ctl registers.
  125. * @quirks: Arasan deviations from spec.
  126. */
  127. struct sdhci_arasan_data {
  128. struct sdhci_host *host;
  129. struct clk *clk_ahb;
  130. struct phy *phy;
  131. bool is_phy_on;
  132. bool has_cqe;
  133. struct sdhci_arasan_clk_data clk_data;
  134. const struct sdhci_arasan_clk_ops *clk_ops;
  135. struct regmap *soc_ctl_base;
  136. const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
  137. unsigned int quirks;
  138. /* Controller does not have CD wired and will not function normally without */
  139. #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
  140. /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
  141. * internal clock even when the clock isn't stable */
  142. #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
  143. /*
  144. * Some of the Arasan variations might not have timing requirements
  145. * met at 25MHz for Default Speed mode, those controllers work at
  146. * 19MHz instead
  147. */
  148. #define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
  149. };
  150. struct sdhci_arasan_of_data {
  151. const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
  152. const struct sdhci_pltfm_data *pdata;
  153. const struct sdhci_arasan_clk_ops *clk_ops;
  154. };
  155. static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
  156. .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
  157. .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
  158. .hiword_update = true,
  159. };
  160. static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
  161. .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
  162. .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
  163. .hiword_update = false,
  164. };
  165. static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
  166. .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
  167. .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
  168. .hiword_update = false,
  169. };
  170. static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
  171. .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
  172. .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
  173. .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
  174. .hiword_update = false,
  175. };
  176. /**
  177. * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
  178. *
  179. * @host: The sdhci_host
  180. * @fld: The field to write to
  181. * @val: The value to write
  182. *
  183. * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
  184. * Note that if a field is specified as not available (shift < 0) then
  185. * this function will silently return an error code. It will be noisy
  186. * and print errors for any other (unexpected) errors.
  187. *
  188. * Return: 0 on success and error value on error
  189. */
  190. static int sdhci_arasan_syscon_write(struct sdhci_host *host,
  191. const struct sdhci_arasan_soc_ctl_field *fld,
  192. u32 val)
  193. {
  194. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  195. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  196. struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
  197. u32 reg = fld->reg;
  198. u16 width = fld->width;
  199. s16 shift = fld->shift;
  200. int ret;
  201. /*
  202. * Silently return errors for shift < 0 so caller doesn't have
  203. * to check for fields which are optional. For fields that
  204. * are required then caller needs to do something special
  205. * anyway.
  206. */
  207. if (shift < 0)
  208. return -EINVAL;
  209. if (sdhci_arasan->soc_ctl_map->hiword_update)
  210. ret = regmap_write(soc_ctl_base, reg,
  211. HIWORD_UPDATE(val, GENMASK(width, 0),
  212. shift));
  213. else
  214. ret = regmap_update_bits(soc_ctl_base, reg,
  215. GENMASK(shift + width, shift),
  216. val << shift);
  217. /* Yell about (unexpected) regmap errors */
  218. if (ret)
  219. pr_warn("%s: Regmap write fail: %d\n",
  220. mmc_hostname(host->mmc), ret);
  221. return ret;
  222. }
  223. static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
  224. {
  225. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  226. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  227. struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
  228. bool ctrl_phy = false;
  229. if (!IS_ERR(sdhci_arasan->phy)) {
  230. if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
  231. /*
  232. * If PHY off, set clock to max speed and power PHY on.
  233. *
  234. * Although PHY docs apparently suggest power cycling
  235. * when changing the clock the PHY doesn't like to be
  236. * powered on while at low speeds like those used in ID
  237. * mode. Even worse is powering the PHY on while the
  238. * clock is off.
  239. *
  240. * To workaround the PHY limitations, the best we can
  241. * do is to power it on at a faster speed and then slam
  242. * through low speeds without power cycling.
  243. */
  244. sdhci_set_clock(host, host->max_clk);
  245. if (phy_power_on(sdhci_arasan->phy)) {
  246. pr_err("%s: Cannot power on phy.\n",
  247. mmc_hostname(host->mmc));
  248. return;
  249. }
  250. sdhci_arasan->is_phy_on = true;
  251. /*
  252. * We'll now fall through to the below case with
  253. * ctrl_phy = false (so we won't turn off/on). The
  254. * sdhci_set_clock() will set the real clock.
  255. */
  256. } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
  257. /*
  258. * At higher clock speeds the PHY is fine being power
  259. * cycled and docs say you _should_ power cycle when
  260. * changing clock speeds.
  261. */
  262. ctrl_phy = true;
  263. }
  264. }
  265. if (ctrl_phy && sdhci_arasan->is_phy_on) {
  266. phy_power_off(sdhci_arasan->phy);
  267. sdhci_arasan->is_phy_on = false;
  268. }
  269. if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
  270. /*
  271. * Some of the Arasan variations might not have timing
  272. * requirements met at 25MHz for Default Speed mode,
  273. * those controllers work at 19MHz instead.
  274. */
  275. if (clock == DEFAULT_SPEED_MAX_DTR)
  276. clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
  277. }
  278. /* Set the Input and Output Clock Phase Delays */
  279. if (clk_data->set_clk_delays)
  280. clk_data->set_clk_delays(host);
  281. sdhci_set_clock(host, clock);
  282. if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
  283. /*
  284. * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
  285. * after enabling the clock even though the clock is not
  286. * stable. Trying to use a clock without waiting here results
  287. * in EILSEQ while detecting some older/slower cards. The
  288. * chosen delay is the maximum delay from sdhci_set_clock.
  289. */
  290. msleep(20);
  291. if (ctrl_phy) {
  292. if (phy_power_on(sdhci_arasan->phy)) {
  293. pr_err("%s: Cannot power on phy.\n",
  294. mmc_hostname(host->mmc));
  295. return;
  296. }
  297. sdhci_arasan->is_phy_on = true;
  298. }
  299. }
  300. static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
  301. struct mmc_ios *ios)
  302. {
  303. u32 vendor;
  304. struct sdhci_host *host = mmc_priv(mmc);
  305. vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
  306. if (ios->enhanced_strobe)
  307. vendor |= VENDOR_ENHANCED_STROBE;
  308. else
  309. vendor &= ~VENDOR_ENHANCED_STROBE;
  310. sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
  311. }
  312. static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
  313. {
  314. u8 ctrl;
  315. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  316. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  317. sdhci_reset(host, mask);
  318. if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
  319. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  320. ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
  321. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  322. }
  323. }
  324. static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
  325. struct mmc_ios *ios)
  326. {
  327. switch (ios->signal_voltage) {
  328. case MMC_SIGNAL_VOLTAGE_180:
  329. /*
  330. * Plese don't switch to 1V8 as arasan,5.1 doesn't
  331. * actually refer to this setting to indicate the
  332. * signal voltage and the state machine will be broken
  333. * actually if we force to enable 1V8. That's something
  334. * like broken quirk but we could work around here.
  335. */
  336. return 0;
  337. case MMC_SIGNAL_VOLTAGE_330:
  338. case MMC_SIGNAL_VOLTAGE_120:
  339. /* We don't support 3V3 and 1V2 */
  340. break;
  341. }
  342. return -EINVAL;
  343. }
  344. static const struct sdhci_ops sdhci_arasan_ops = {
  345. .set_clock = sdhci_arasan_set_clock,
  346. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  347. .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
  348. .set_bus_width = sdhci_set_bus_width,
  349. .reset = sdhci_arasan_reset,
  350. .set_uhs_signaling = sdhci_set_uhs_signaling,
  351. .set_power = sdhci_set_power_and_bus_voltage,
  352. };
  353. static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
  354. {
  355. int cmd_error = 0;
  356. int data_error = 0;
  357. if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
  358. return intmask;
  359. cqhci_irq(host->mmc, intmask, cmd_error, data_error);
  360. return 0;
  361. }
  362. static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
  363. {
  364. sdhci_dumpregs(mmc_priv(mmc));
  365. }
  366. static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
  367. {
  368. struct sdhci_host *host = mmc_priv(mmc);
  369. u32 reg;
  370. reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
  371. while (reg & SDHCI_DATA_AVAILABLE) {
  372. sdhci_readl(host, SDHCI_BUFFER);
  373. reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
  374. }
  375. sdhci_cqe_enable(mmc);
  376. }
  377. static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
  378. .enable = sdhci_arasan_cqe_enable,
  379. .disable = sdhci_cqe_disable,
  380. .dumpregs = sdhci_arasan_dumpregs,
  381. };
  382. static const struct sdhci_ops sdhci_arasan_cqe_ops = {
  383. .set_clock = sdhci_arasan_set_clock,
  384. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  385. .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
  386. .set_bus_width = sdhci_set_bus_width,
  387. .reset = sdhci_arasan_reset,
  388. .set_uhs_signaling = sdhci_set_uhs_signaling,
  389. .set_power = sdhci_set_power_and_bus_voltage,
  390. .irq = sdhci_arasan_cqhci_irq,
  391. };
  392. static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
  393. .ops = &sdhci_arasan_cqe_ops,
  394. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  395. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  396. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
  397. };
  398. #ifdef CONFIG_PM_SLEEP
  399. /**
  400. * sdhci_arasan_suspend - Suspend method for the driver
  401. * @dev: Address of the device structure
  402. *
  403. * Put the device in a low power state.
  404. *
  405. * Return: 0 on success and error value on error
  406. */
  407. static int sdhci_arasan_suspend(struct device *dev)
  408. {
  409. struct sdhci_host *host = dev_get_drvdata(dev);
  410. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  411. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  412. int ret;
  413. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  414. mmc_retune_needed(host->mmc);
  415. if (sdhci_arasan->has_cqe) {
  416. ret = cqhci_suspend(host->mmc);
  417. if (ret)
  418. return ret;
  419. }
  420. ret = sdhci_suspend_host(host);
  421. if (ret)
  422. return ret;
  423. if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
  424. ret = phy_power_off(sdhci_arasan->phy);
  425. if (ret) {
  426. dev_err(dev, "Cannot power off phy.\n");
  427. if (sdhci_resume_host(host))
  428. dev_err(dev, "Cannot resume host.\n");
  429. return ret;
  430. }
  431. sdhci_arasan->is_phy_on = false;
  432. }
  433. clk_disable(pltfm_host->clk);
  434. clk_disable(sdhci_arasan->clk_ahb);
  435. return 0;
  436. }
  437. /**
  438. * sdhci_arasan_resume - Resume method for the driver
  439. * @dev: Address of the device structure
  440. *
  441. * Resume operation after suspend
  442. *
  443. * Return: 0 on success and error value on error
  444. */
  445. static int sdhci_arasan_resume(struct device *dev)
  446. {
  447. struct sdhci_host *host = dev_get_drvdata(dev);
  448. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  449. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  450. int ret;
  451. ret = clk_enable(sdhci_arasan->clk_ahb);
  452. if (ret) {
  453. dev_err(dev, "Cannot enable AHB clock.\n");
  454. return ret;
  455. }
  456. ret = clk_enable(pltfm_host->clk);
  457. if (ret) {
  458. dev_err(dev, "Cannot enable SD clock.\n");
  459. return ret;
  460. }
  461. if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
  462. ret = phy_power_on(sdhci_arasan->phy);
  463. if (ret) {
  464. dev_err(dev, "Cannot power on phy.\n");
  465. return ret;
  466. }
  467. sdhci_arasan->is_phy_on = true;
  468. }
  469. ret = sdhci_resume_host(host);
  470. if (ret) {
  471. dev_err(dev, "Cannot resume host.\n");
  472. return ret;
  473. }
  474. if (sdhci_arasan->has_cqe)
  475. return cqhci_resume(host->mmc);
  476. return 0;
  477. }
  478. #endif /* ! CONFIG_PM_SLEEP */
  479. static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
  480. sdhci_arasan_resume);
  481. /**
  482. * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
  483. *
  484. * @hw: Pointer to the hardware clock structure.
  485. * @parent_rate: The parent rate (should be rate of clk_xin).
  486. *
  487. * Return the current actual rate of the SD card clock. This can be used
  488. * to communicate with out PHY.
  489. *
  490. * Return: The card clock rate.
  491. */
  492. static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
  493. unsigned long parent_rate)
  494. {
  495. struct sdhci_arasan_clk_data *clk_data =
  496. container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
  497. struct sdhci_arasan_data *sdhci_arasan =
  498. container_of(clk_data, struct sdhci_arasan_data, clk_data);
  499. struct sdhci_host *host = sdhci_arasan->host;
  500. return host->mmc->actual_clock;
  501. }
  502. static const struct clk_ops arasan_sdcardclk_ops = {
  503. .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
  504. };
  505. /**
  506. * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
  507. *
  508. * @hw: Pointer to the hardware clock structure.
  509. * @parent_rate: The parent rate (should be rate of clk_xin).
  510. *
  511. * Return the current actual rate of the sampling clock. This can be used
  512. * to communicate with out PHY.
  513. *
  514. * Return: The sample clock rate.
  515. */
  516. static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
  517. unsigned long parent_rate)
  518. {
  519. struct sdhci_arasan_clk_data *clk_data =
  520. container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
  521. struct sdhci_arasan_data *sdhci_arasan =
  522. container_of(clk_data, struct sdhci_arasan_data, clk_data);
  523. struct sdhci_host *host = sdhci_arasan->host;
  524. return host->mmc->actual_clock;
  525. }
  526. static const struct clk_ops arasan_sampleclk_ops = {
  527. .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
  528. };
  529. /**
  530. * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
  531. *
  532. * @hw: Pointer to the hardware clock structure.
  533. * @degrees: The clock phase shift between 0 - 359.
  534. *
  535. * Set the SD Output Clock Tap Delays for Output path
  536. *
  537. * Return: 0 on success and error value on error
  538. */
  539. static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
  540. {
  541. struct sdhci_arasan_clk_data *clk_data =
  542. container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
  543. struct sdhci_arasan_data *sdhci_arasan =
  544. container_of(clk_data, struct sdhci_arasan_data, clk_data);
  545. struct sdhci_host *host = sdhci_arasan->host;
  546. const char *clk_name = clk_hw_get_name(hw);
  547. u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
  548. u8 tap_delay, tap_max = 0;
  549. int ret;
  550. /* This is applicable for SDHCI_SPEC_300 and above */
  551. if (host->version < SDHCI_SPEC_300)
  552. return 0;
  553. switch (host->timing) {
  554. case MMC_TIMING_MMC_HS:
  555. case MMC_TIMING_SD_HS:
  556. case MMC_TIMING_UHS_SDR25:
  557. case MMC_TIMING_UHS_DDR50:
  558. case MMC_TIMING_MMC_DDR52:
  559. /* For 50MHz clock, 30 Taps are available */
  560. tap_max = 30;
  561. break;
  562. case MMC_TIMING_UHS_SDR50:
  563. /* For 100MHz clock, 15 Taps are available */
  564. tap_max = 15;
  565. break;
  566. case MMC_TIMING_UHS_SDR104:
  567. case MMC_TIMING_MMC_HS200:
  568. /* For 200MHz clock, 8 Taps are available */
  569. tap_max = 8;
  570. default:
  571. break;
  572. }
  573. tap_delay = (degrees * tap_max) / 360;
  574. /* Set the Clock Phase */
  575. ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
  576. if (ret)
  577. pr_err("Error setting Output Tap Delay\n");
  578. /* Release DLL Reset */
  579. zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
  580. return ret;
  581. }
  582. static const struct clk_ops zynqmp_sdcardclk_ops = {
  583. .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
  584. .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
  585. };
  586. /**
  587. * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
  588. *
  589. * @hw: Pointer to the hardware clock structure.
  590. * @degrees: The clock phase shift between 0 - 359.
  591. *
  592. * Set the SD Input Clock Tap Delays for Input path
  593. *
  594. * Return: 0 on success and error value on error
  595. */
  596. static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
  597. {
  598. struct sdhci_arasan_clk_data *clk_data =
  599. container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
  600. struct sdhci_arasan_data *sdhci_arasan =
  601. container_of(clk_data, struct sdhci_arasan_data, clk_data);
  602. struct sdhci_host *host = sdhci_arasan->host;
  603. const char *clk_name = clk_hw_get_name(hw);
  604. u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
  605. u8 tap_delay, tap_max = 0;
  606. int ret;
  607. /* This is applicable for SDHCI_SPEC_300 and above */
  608. if (host->version < SDHCI_SPEC_300)
  609. return 0;
  610. /* Assert DLL Reset */
  611. zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
  612. switch (host->timing) {
  613. case MMC_TIMING_MMC_HS:
  614. case MMC_TIMING_SD_HS:
  615. case MMC_TIMING_UHS_SDR25:
  616. case MMC_TIMING_UHS_DDR50:
  617. case MMC_TIMING_MMC_DDR52:
  618. /* For 50MHz clock, 120 Taps are available */
  619. tap_max = 120;
  620. break;
  621. case MMC_TIMING_UHS_SDR50:
  622. /* For 100MHz clock, 60 Taps are available */
  623. tap_max = 60;
  624. break;
  625. case MMC_TIMING_UHS_SDR104:
  626. case MMC_TIMING_MMC_HS200:
  627. /* For 200MHz clock, 30 Taps are available */
  628. tap_max = 30;
  629. default:
  630. break;
  631. }
  632. tap_delay = (degrees * tap_max) / 360;
  633. /* Set the Clock Phase */
  634. ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
  635. if (ret)
  636. pr_err("Error setting Input Tap Delay\n");
  637. return ret;
  638. }
  639. static const struct clk_ops zynqmp_sampleclk_ops = {
  640. .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
  641. .set_phase = sdhci_zynqmp_sampleclk_set_phase,
  642. };
  643. /**
  644. * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
  645. *
  646. * @hw: Pointer to the hardware clock structure.
  647. * @degrees: The clock phase shift between 0 - 359.
  648. *
  649. * Set the SD Output Clock Tap Delays for Output path
  650. *
  651. * Return: 0 on success and error value on error
  652. */
  653. static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
  654. {
  655. struct sdhci_arasan_clk_data *clk_data =
  656. container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
  657. struct sdhci_arasan_data *sdhci_arasan =
  658. container_of(clk_data, struct sdhci_arasan_data, clk_data);
  659. struct sdhci_host *host = sdhci_arasan->host;
  660. u8 tap_delay, tap_max = 0;
  661. /* This is applicable for SDHCI_SPEC_300 and above */
  662. if (host->version < SDHCI_SPEC_300)
  663. return 0;
  664. switch (host->timing) {
  665. case MMC_TIMING_MMC_HS:
  666. case MMC_TIMING_SD_HS:
  667. case MMC_TIMING_UHS_SDR25:
  668. case MMC_TIMING_UHS_DDR50:
  669. case MMC_TIMING_MMC_DDR52:
  670. /* For 50MHz clock, 30 Taps are available */
  671. tap_max = 30;
  672. break;
  673. case MMC_TIMING_UHS_SDR50:
  674. /* For 100MHz clock, 15 Taps are available */
  675. tap_max = 15;
  676. break;
  677. case MMC_TIMING_UHS_SDR104:
  678. case MMC_TIMING_MMC_HS200:
  679. /* For 200MHz clock, 8 Taps are available */
  680. tap_max = 8;
  681. default:
  682. break;
  683. }
  684. tap_delay = (degrees * tap_max) / 360;
  685. /* Set the Clock Phase */
  686. if (tap_delay) {
  687. u32 regval;
  688. regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
  689. regval |= SDHCI_OTAPDLY_ENABLE;
  690. sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
  691. regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
  692. regval |= tap_delay;
  693. sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
  694. }
  695. return 0;
  696. }
  697. static const struct clk_ops versal_sdcardclk_ops = {
  698. .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
  699. .set_phase = sdhci_versal_sdcardclk_set_phase,
  700. };
  701. /**
  702. * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
  703. *
  704. * @hw: Pointer to the hardware clock structure.
  705. * @degrees: The clock phase shift between 0 - 359.
  706. *
  707. * Set the SD Input Clock Tap Delays for Input path
  708. *
  709. * Return: 0 on success and error value on error
  710. */
  711. static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
  712. {
  713. struct sdhci_arasan_clk_data *clk_data =
  714. container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
  715. struct sdhci_arasan_data *sdhci_arasan =
  716. container_of(clk_data, struct sdhci_arasan_data, clk_data);
  717. struct sdhci_host *host = sdhci_arasan->host;
  718. u8 tap_delay, tap_max = 0;
  719. /* This is applicable for SDHCI_SPEC_300 and above */
  720. if (host->version < SDHCI_SPEC_300)
  721. return 0;
  722. switch (host->timing) {
  723. case MMC_TIMING_MMC_HS:
  724. case MMC_TIMING_SD_HS:
  725. case MMC_TIMING_UHS_SDR25:
  726. case MMC_TIMING_UHS_DDR50:
  727. case MMC_TIMING_MMC_DDR52:
  728. /* For 50MHz clock, 120 Taps are available */
  729. tap_max = 120;
  730. break;
  731. case MMC_TIMING_UHS_SDR50:
  732. /* For 100MHz clock, 60 Taps are available */
  733. tap_max = 60;
  734. break;
  735. case MMC_TIMING_UHS_SDR104:
  736. case MMC_TIMING_MMC_HS200:
  737. /* For 200MHz clock, 30 Taps are available */
  738. tap_max = 30;
  739. default:
  740. break;
  741. }
  742. tap_delay = (degrees * tap_max) / 360;
  743. /* Set the Clock Phase */
  744. if (tap_delay) {
  745. u32 regval;
  746. regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
  747. regval |= SDHCI_ITAPDLY_CHGWIN;
  748. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  749. regval |= SDHCI_ITAPDLY_ENABLE;
  750. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  751. regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
  752. regval |= tap_delay;
  753. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  754. regval &= ~SDHCI_ITAPDLY_CHGWIN;
  755. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  756. }
  757. return 0;
  758. }
  759. static const struct clk_ops versal_sampleclk_ops = {
  760. .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
  761. .set_phase = sdhci_versal_sampleclk_set_phase,
  762. };
  763. static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
  764. {
  765. u16 clk;
  766. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  767. clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
  768. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  769. /* Issue DLL Reset */
  770. zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
  771. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  772. sdhci_enable_clk(host, clk);
  773. }
  774. static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
  775. {
  776. struct sdhci_host *host = mmc_priv(mmc);
  777. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  778. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  779. struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
  780. const char *clk_name = clk_hw_get_name(hw);
  781. u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
  782. NODE_SD_1;
  783. int err;
  784. arasan_zynqmp_dll_reset(host, device_id);
  785. err = sdhci_execute_tuning(mmc, opcode);
  786. if (err)
  787. return err;
  788. arasan_zynqmp_dll_reset(host, device_id);
  789. return 0;
  790. }
  791. /**
  792. * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
  793. *
  794. * @host: The sdhci_host
  795. * @value: The value to write
  796. *
  797. * The corecfg_clockmultiplier is supposed to contain clock multiplier
  798. * value of programmable clock generator.
  799. *
  800. * NOTES:
  801. * - Many existing devices don't seem to do this and work fine. To keep
  802. * compatibility for old hardware where the device tree doesn't provide a
  803. * register map, this function is a noop if a soc_ctl_map hasn't been provided
  804. * for this platform.
  805. * - The value of corecfg_clockmultiplier should sync with that of corresponding
  806. * value reading from sdhci_capability_register. So this function is called
  807. * once at probe time and never called again.
  808. */
  809. static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
  810. u32 value)
  811. {
  812. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  813. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  814. const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
  815. sdhci_arasan->soc_ctl_map;
  816. /* Having a map is optional */
  817. if (!soc_ctl_map)
  818. return;
  819. /* If we have a map, we expect to have a syscon */
  820. if (!sdhci_arasan->soc_ctl_base) {
  821. pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
  822. mmc_hostname(host->mmc));
  823. return;
  824. }
  825. sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
  826. }
  827. /**
  828. * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
  829. *
  830. * @host: The sdhci_host
  831. *
  832. * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
  833. * function can be used to make that happen.
  834. *
  835. * NOTES:
  836. * - Many existing devices don't seem to do this and work fine. To keep
  837. * compatibility for old hardware where the device tree doesn't provide a
  838. * register map, this function is a noop if a soc_ctl_map hasn't been provided
  839. * for this platform.
  840. * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
  841. * to achieve lower clock rates. That means that this function is called once
  842. * at probe time and never called again.
  843. */
  844. static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
  845. {
  846. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  847. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  848. const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
  849. sdhci_arasan->soc_ctl_map;
  850. u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
  851. /* Having a map is optional */
  852. if (!soc_ctl_map)
  853. return;
  854. /* If we have a map, we expect to have a syscon */
  855. if (!sdhci_arasan->soc_ctl_base) {
  856. pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
  857. mmc_hostname(host->mmc));
  858. return;
  859. }
  860. sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
  861. }
  862. static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
  863. {
  864. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  865. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  866. struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
  867. clk_set_phase(clk_data->sampleclk,
  868. clk_data->clk_phase_in[host->timing]);
  869. clk_set_phase(clk_data->sdcardclk,
  870. clk_data->clk_phase_out[host->timing]);
  871. }
  872. static void arasan_dt_read_clk_phase(struct device *dev,
  873. struct sdhci_arasan_clk_data *clk_data,
  874. unsigned int timing, const char *prop)
  875. {
  876. struct device_node *np = dev->of_node;
  877. int clk_phase[2] = {0};
  878. /*
  879. * Read Tap Delay values from DT, if the DT does not contain the
  880. * Tap Values then use the pre-defined values.
  881. */
  882. if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
  883. 2, 0)) {
  884. dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
  885. prop, clk_data->clk_phase_in[timing],
  886. clk_data->clk_phase_out[timing]);
  887. return;
  888. }
  889. /* The values read are Input and Output Clock Delays in order */
  890. clk_data->clk_phase_in[timing] = clk_phase[0];
  891. clk_data->clk_phase_out[timing] = clk_phase[1];
  892. }
  893. /**
  894. * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
  895. *
  896. * @dev: Pointer to our struct device.
  897. * @clk_data: Pointer to the Clock Data structure
  898. *
  899. * Called at initialization to parse the values of Clock Delays.
  900. */
  901. static void arasan_dt_parse_clk_phases(struct device *dev,
  902. struct sdhci_arasan_clk_data *clk_data)
  903. {
  904. u32 mio_bank = 0;
  905. int i;
  906. /*
  907. * This has been kept as a pointer and is assigned a function here.
  908. * So that different controller variants can assign their own handling
  909. * function.
  910. */
  911. clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
  912. if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
  913. u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
  914. ZYNQMP_ICLK_PHASE;
  915. u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
  916. ZYNQMP_OCLK_PHASE;
  917. of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
  918. if (mio_bank == 2) {
  919. zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
  920. zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
  921. }
  922. for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
  923. clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
  924. clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
  925. }
  926. }
  927. if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
  928. u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
  929. VERSAL_ICLK_PHASE;
  930. u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
  931. VERSAL_OCLK_PHASE;
  932. for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
  933. clk_data->clk_phase_in[i] = versal_iclk_phase[i];
  934. clk_data->clk_phase_out[i] = versal_oclk_phase[i];
  935. }
  936. }
  937. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
  938. "clk-phase-legacy");
  939. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
  940. "clk-phase-mmc-hs");
  941. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
  942. "clk-phase-sd-hs");
  943. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
  944. "clk-phase-uhs-sdr12");
  945. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
  946. "clk-phase-uhs-sdr25");
  947. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
  948. "clk-phase-uhs-sdr50");
  949. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
  950. "clk-phase-uhs-sdr104");
  951. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
  952. "clk-phase-uhs-ddr50");
  953. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
  954. "clk-phase-mmc-ddr52");
  955. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
  956. "clk-phase-mmc-hs200");
  957. arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
  958. "clk-phase-mmc-hs400");
  959. }
  960. static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
  961. .ops = &sdhci_arasan_ops,
  962. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  963. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  964. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
  965. SDHCI_QUIRK2_STOP_WITH_TC,
  966. };
  967. static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
  968. .sdcardclk_ops = &arasan_sdcardclk_ops,
  969. .sampleclk_ops = &arasan_sampleclk_ops,
  970. };
  971. static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
  972. .pdata = &sdhci_arasan_pdata,
  973. .clk_ops = &arasan_clk_ops,
  974. };
  975. static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
  976. .ops = &sdhci_arasan_cqe_ops,
  977. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
  978. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  979. SDHCI_QUIRK_NO_LED |
  980. SDHCI_QUIRK_32BIT_DMA_ADDR |
  981. SDHCI_QUIRK_32BIT_DMA_SIZE |
  982. SDHCI_QUIRK_32BIT_ADMA_SIZE,
  983. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  984. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
  985. SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
  986. SDHCI_QUIRK2_STOP_WITH_TC |
  987. SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  988. };
  989. static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
  990. .ops = &sdhci_arasan_ops,
  991. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
  992. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  993. SDHCI_QUIRK_NO_LED |
  994. SDHCI_QUIRK_32BIT_DMA_ADDR |
  995. SDHCI_QUIRK_32BIT_DMA_SIZE |
  996. SDHCI_QUIRK_32BIT_ADMA_SIZE,
  997. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  998. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
  999. SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
  1000. SDHCI_QUIRK2_STOP_WITH_TC |
  1001. SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  1002. };
  1003. static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
  1004. .ops = &sdhci_arasan_ops,
  1005. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
  1006. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
  1007. SDHCI_QUIRK_NO_LED |
  1008. SDHCI_QUIRK_32BIT_DMA_ADDR |
  1009. SDHCI_QUIRK_32BIT_DMA_SIZE |
  1010. SDHCI_QUIRK_32BIT_ADMA_SIZE,
  1011. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  1012. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
  1013. SDHCI_QUIRK2_HOST_OFF_CARD_ON |
  1014. SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
  1015. };
  1016. static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
  1017. .soc_ctl_map = &rk3399_soc_ctl_map,
  1018. .pdata = &sdhci_arasan_cqe_pdata,
  1019. .clk_ops = &arasan_clk_ops,
  1020. };
  1021. static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
  1022. .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
  1023. .pdata = &sdhci_arasan_cqe_pdata,
  1024. .clk_ops = &arasan_clk_ops,
  1025. };
  1026. static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
  1027. .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
  1028. .pdata = &sdhci_arasan_cqe_pdata,
  1029. .clk_ops = &arasan_clk_ops,
  1030. };
  1031. static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
  1032. .ops = &sdhci_arasan_ops,
  1033. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  1034. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
  1035. SDHCI_QUIRK2_STOP_WITH_TC,
  1036. };
  1037. static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
  1038. .sdcardclk_ops = &zynqmp_sdcardclk_ops,
  1039. .sampleclk_ops = &zynqmp_sampleclk_ops,
  1040. };
  1041. static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
  1042. .pdata = &sdhci_arasan_zynqmp_pdata,
  1043. .clk_ops = &zynqmp_clk_ops,
  1044. };
  1045. static const struct sdhci_arasan_clk_ops versal_clk_ops = {
  1046. .sdcardclk_ops = &versal_sdcardclk_ops,
  1047. .sampleclk_ops = &versal_sampleclk_ops,
  1048. };
  1049. static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
  1050. .pdata = &sdhci_arasan_zynqmp_pdata,
  1051. .clk_ops = &versal_clk_ops,
  1052. };
  1053. static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
  1054. .soc_ctl_map = &intel_keembay_soc_ctl_map,
  1055. .pdata = &sdhci_keembay_emmc_pdata,
  1056. .clk_ops = &arasan_clk_ops,
  1057. };
  1058. static struct sdhci_arasan_of_data intel_keembay_sd_data = {
  1059. .soc_ctl_map = &intel_keembay_soc_ctl_map,
  1060. .pdata = &sdhci_keembay_sd_pdata,
  1061. .clk_ops = &arasan_clk_ops,
  1062. };
  1063. static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
  1064. .soc_ctl_map = &intel_keembay_soc_ctl_map,
  1065. .pdata = &sdhci_keembay_sdio_pdata,
  1066. .clk_ops = &arasan_clk_ops,
  1067. };
  1068. static const struct of_device_id sdhci_arasan_of_match[] = {
  1069. /* SoC-specific compatible strings w/ soc_ctl_map */
  1070. {
  1071. .compatible = "rockchip,rk3399-sdhci-5.1",
  1072. .data = &sdhci_arasan_rk3399_data,
  1073. },
  1074. {
  1075. .compatible = "intel,lgm-sdhci-5.1-emmc",
  1076. .data = &intel_lgm_emmc_data,
  1077. },
  1078. {
  1079. .compatible = "intel,lgm-sdhci-5.1-sdxc",
  1080. .data = &intel_lgm_sdxc_data,
  1081. },
  1082. {
  1083. .compatible = "intel,keembay-sdhci-5.1-emmc",
  1084. .data = &intel_keembay_emmc_data,
  1085. },
  1086. {
  1087. .compatible = "intel,keembay-sdhci-5.1-sd",
  1088. .data = &intel_keembay_sd_data,
  1089. },
  1090. {
  1091. .compatible = "intel,keembay-sdhci-5.1-sdio",
  1092. .data = &intel_keembay_sdio_data,
  1093. },
  1094. /* Generic compatible below here */
  1095. {
  1096. .compatible = "arasan,sdhci-8.9a",
  1097. .data = &sdhci_arasan_generic_data,
  1098. },
  1099. {
  1100. .compatible = "arasan,sdhci-5.1",
  1101. .data = &sdhci_arasan_generic_data,
  1102. },
  1103. {
  1104. .compatible = "arasan,sdhci-4.9a",
  1105. .data = &sdhci_arasan_generic_data,
  1106. },
  1107. {
  1108. .compatible = "xlnx,zynqmp-8.9a",
  1109. .data = &sdhci_arasan_zynqmp_data,
  1110. },
  1111. {
  1112. .compatible = "xlnx,versal-8.9a",
  1113. .data = &sdhci_arasan_versal_data,
  1114. },
  1115. { /* sentinel */ }
  1116. };
  1117. MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
  1118. /**
  1119. * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
  1120. *
  1121. * @sdhci_arasan: Our private data structure.
  1122. * @clk_xin: Pointer to the functional clock
  1123. * @dev: Pointer to our struct device.
  1124. *
  1125. * Some PHY devices need to know what the actual card clock is. In order for
  1126. * them to find out, we'll provide a clock through the common clock framework
  1127. * for them to query.
  1128. *
  1129. * Return: 0 on success and error value on error
  1130. */
  1131. static int
  1132. sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
  1133. struct clk *clk_xin,
  1134. struct device *dev)
  1135. {
  1136. struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
  1137. struct device_node *np = dev->of_node;
  1138. struct clk_init_data sdcardclk_init;
  1139. const char *parent_clk_name;
  1140. int ret;
  1141. ret = of_property_read_string_index(np, "clock-output-names", 0,
  1142. &sdcardclk_init.name);
  1143. if (ret) {
  1144. dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
  1145. return ret;
  1146. }
  1147. parent_clk_name = __clk_get_name(clk_xin);
  1148. sdcardclk_init.parent_names = &parent_clk_name;
  1149. sdcardclk_init.num_parents = 1;
  1150. sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
  1151. sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
  1152. clk_data->sdcardclk_hw.init = &sdcardclk_init;
  1153. clk_data->sdcardclk =
  1154. devm_clk_register(dev, &clk_data->sdcardclk_hw);
  1155. if (IS_ERR(clk_data->sdcardclk))
  1156. return PTR_ERR(clk_data->sdcardclk);
  1157. clk_data->sdcardclk_hw.init = NULL;
  1158. ret = of_clk_add_provider(np, of_clk_src_simple_get,
  1159. clk_data->sdcardclk);
  1160. if (ret)
  1161. dev_err(dev, "Failed to add sdcard clock provider\n");
  1162. return ret;
  1163. }
  1164. /**
  1165. * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
  1166. *
  1167. * @sdhci_arasan: Our private data structure.
  1168. * @clk_xin: Pointer to the functional clock
  1169. * @dev: Pointer to our struct device.
  1170. *
  1171. * Some PHY devices need to know what the actual card clock is. In order for
  1172. * them to find out, we'll provide a clock through the common clock framework
  1173. * for them to query.
  1174. *
  1175. * Return: 0 on success and error value on error
  1176. */
  1177. static int
  1178. sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
  1179. struct clk *clk_xin,
  1180. struct device *dev)
  1181. {
  1182. struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
  1183. struct device_node *np = dev->of_node;
  1184. struct clk_init_data sampleclk_init;
  1185. const char *parent_clk_name;
  1186. int ret;
  1187. ret = of_property_read_string_index(np, "clock-output-names", 1,
  1188. &sampleclk_init.name);
  1189. if (ret) {
  1190. dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
  1191. return ret;
  1192. }
  1193. parent_clk_name = __clk_get_name(clk_xin);
  1194. sampleclk_init.parent_names = &parent_clk_name;
  1195. sampleclk_init.num_parents = 1;
  1196. sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
  1197. sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
  1198. clk_data->sampleclk_hw.init = &sampleclk_init;
  1199. clk_data->sampleclk =
  1200. devm_clk_register(dev, &clk_data->sampleclk_hw);
  1201. if (IS_ERR(clk_data->sampleclk))
  1202. return PTR_ERR(clk_data->sampleclk);
  1203. clk_data->sampleclk_hw.init = NULL;
  1204. ret = of_clk_add_provider(np, of_clk_src_simple_get,
  1205. clk_data->sampleclk);
  1206. if (ret)
  1207. dev_err(dev, "Failed to add sample clock provider\n");
  1208. return ret;
  1209. }
  1210. /**
  1211. * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
  1212. *
  1213. * @dev: Pointer to our struct device.
  1214. *
  1215. * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
  1216. * returned success.
  1217. */
  1218. static void sdhci_arasan_unregister_sdclk(struct device *dev)
  1219. {
  1220. struct device_node *np = dev->of_node;
  1221. if (!of_find_property(np, "#clock-cells", NULL))
  1222. return;
  1223. of_clk_del_provider(dev->of_node);
  1224. }
  1225. /**
  1226. * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
  1227. *
  1228. * This should be set based on the System Address Bus.
  1229. * 0: the Core supports only 32-bit System Address Bus.
  1230. * 1: the Core supports 64-bit System Address Bus.
  1231. *
  1232. * NOTES:
  1233. * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
  1234. * Keem Bay does not support 64-bit access.
  1235. *
  1236. * @host: The sdhci_host
  1237. * @value: The value to write
  1238. */
  1239. static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
  1240. {
  1241. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1242. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  1243. const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
  1244. sdhci_arasan->soc_ctl_map;
  1245. /* Having a map is optional */
  1246. if (!soc_ctl_map)
  1247. return;
  1248. /* If we have a map, we expect to have a syscon */
  1249. if (!sdhci_arasan->soc_ctl_base) {
  1250. pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
  1251. mmc_hostname(host->mmc));
  1252. return;
  1253. }
  1254. sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
  1255. }
  1256. /**
  1257. * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
  1258. *
  1259. * @sdhci_arasan: Our private data structure.
  1260. * @clk_xin: Pointer to the functional clock
  1261. * @dev: Pointer to our struct device.
  1262. *
  1263. * Some PHY devices need to know what the actual card clock is. In order for
  1264. * them to find out, we'll provide a clock through the common clock framework
  1265. * for them to query.
  1266. *
  1267. * Note: without seriously re-architecting SDHCI's clock code and testing on
  1268. * all platforms, there's no way to create a totally beautiful clock here
  1269. * with all clock ops implemented. Instead, we'll just create a clock that can
  1270. * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
  1271. * framework that we're doing things behind its back. This should be sufficient
  1272. * to create nice clean device tree bindings and later (if needed) we can try
  1273. * re-architecting SDHCI if we see some benefit to it.
  1274. *
  1275. * Return: 0 on success and error value on error
  1276. */
  1277. static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
  1278. struct clk *clk_xin,
  1279. struct device *dev)
  1280. {
  1281. struct device_node *np = dev->of_node;
  1282. u32 num_clks = 0;
  1283. int ret;
  1284. /* Providing a clock to the PHY is optional; no error if missing */
  1285. if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
  1286. return 0;
  1287. ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
  1288. if (ret)
  1289. return ret;
  1290. if (num_clks) {
  1291. ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
  1292. dev);
  1293. if (ret) {
  1294. sdhci_arasan_unregister_sdclk(dev);
  1295. return ret;
  1296. }
  1297. }
  1298. return 0;
  1299. }
  1300. static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
  1301. {
  1302. struct sdhci_host *host = sdhci_arasan->host;
  1303. struct cqhci_host *cq_host;
  1304. bool dma64;
  1305. int ret;
  1306. if (!sdhci_arasan->has_cqe)
  1307. return sdhci_add_host(host);
  1308. ret = sdhci_setup_host(host);
  1309. if (ret)
  1310. return ret;
  1311. cq_host = devm_kzalloc(host->mmc->parent,
  1312. sizeof(*cq_host), GFP_KERNEL);
  1313. if (!cq_host) {
  1314. ret = -ENOMEM;
  1315. goto cleanup;
  1316. }
  1317. cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
  1318. cq_host->ops = &sdhci_arasan_cqhci_ops;
  1319. dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
  1320. if (dma64)
  1321. cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  1322. ret = cqhci_init(cq_host, host->mmc, dma64);
  1323. if (ret)
  1324. goto cleanup;
  1325. ret = __sdhci_add_host(host);
  1326. if (ret)
  1327. goto cleanup;
  1328. return 0;
  1329. cleanup:
  1330. sdhci_cleanup_host(host);
  1331. return ret;
  1332. }
  1333. static int sdhci_arasan_probe(struct platform_device *pdev)
  1334. {
  1335. int ret;
  1336. const struct of_device_id *match;
  1337. struct device_node *node;
  1338. struct clk *clk_xin;
  1339. struct sdhci_host *host;
  1340. struct sdhci_pltfm_host *pltfm_host;
  1341. struct sdhci_arasan_data *sdhci_arasan;
  1342. struct device_node *np = pdev->dev.of_node;
  1343. const struct sdhci_arasan_of_data *data;
  1344. match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
  1345. data = match->data;
  1346. host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
  1347. if (IS_ERR(host))
  1348. return PTR_ERR(host);
  1349. pltfm_host = sdhci_priv(host);
  1350. sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  1351. sdhci_arasan->host = host;
  1352. sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
  1353. sdhci_arasan->clk_ops = data->clk_ops;
  1354. node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
  1355. if (node) {
  1356. sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
  1357. of_node_put(node);
  1358. if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
  1359. ret = dev_err_probe(&pdev->dev,
  1360. PTR_ERR(sdhci_arasan->soc_ctl_base),
  1361. "Can't get syscon\n");
  1362. goto err_pltfm_free;
  1363. }
  1364. }
  1365. sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
  1366. if (IS_ERR(sdhci_arasan->clk_ahb)) {
  1367. dev_err(&pdev->dev, "clk_ahb clock not found.\n");
  1368. ret = PTR_ERR(sdhci_arasan->clk_ahb);
  1369. goto err_pltfm_free;
  1370. }
  1371. clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
  1372. if (IS_ERR(clk_xin)) {
  1373. dev_err(&pdev->dev, "clk_xin clock not found.\n");
  1374. ret = PTR_ERR(clk_xin);
  1375. goto err_pltfm_free;
  1376. }
  1377. ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
  1378. if (ret) {
  1379. dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
  1380. goto err_pltfm_free;
  1381. }
  1382. ret = clk_prepare_enable(clk_xin);
  1383. if (ret) {
  1384. dev_err(&pdev->dev, "Unable to enable SD clock.\n");
  1385. goto clk_dis_ahb;
  1386. }
  1387. sdhci_get_of_property(pdev);
  1388. if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
  1389. sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
  1390. if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
  1391. sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
  1392. pltfm_host->clk = clk_xin;
  1393. if (of_device_is_compatible(pdev->dev.of_node,
  1394. "rockchip,rk3399-sdhci-5.1"))
  1395. sdhci_arasan_update_clockmultiplier(host, 0x0);
  1396. if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
  1397. of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
  1398. of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
  1399. sdhci_arasan_update_clockmultiplier(host, 0x0);
  1400. sdhci_arasan_update_support64b(host, 0x0);
  1401. host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  1402. }
  1403. sdhci_arasan_update_baseclkfreq(host);
  1404. ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
  1405. if (ret)
  1406. goto clk_disable_all;
  1407. if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
  1408. host->mmc_host_ops.execute_tuning =
  1409. arasan_zynqmp_execute_tuning;
  1410. sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
  1411. }
  1412. arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
  1413. ret = mmc_of_parse(host->mmc);
  1414. if (ret) {
  1415. if (ret != -EPROBE_DEFER)
  1416. dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
  1417. goto unreg_clk;
  1418. }
  1419. sdhci_arasan->phy = ERR_PTR(-ENODEV);
  1420. if (of_device_is_compatible(pdev->dev.of_node,
  1421. "arasan,sdhci-5.1")) {
  1422. sdhci_arasan->phy = devm_phy_get(&pdev->dev,
  1423. "phy_arasan");
  1424. if (IS_ERR(sdhci_arasan->phy)) {
  1425. ret = PTR_ERR(sdhci_arasan->phy);
  1426. dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
  1427. goto unreg_clk;
  1428. }
  1429. ret = phy_init(sdhci_arasan->phy);
  1430. if (ret < 0) {
  1431. dev_err(&pdev->dev, "phy_init err.\n");
  1432. goto unreg_clk;
  1433. }
  1434. host->mmc_host_ops.hs400_enhanced_strobe =
  1435. sdhci_arasan_hs400_enhanced_strobe;
  1436. host->mmc_host_ops.start_signal_voltage_switch =
  1437. sdhci_arasan_voltage_switch;
  1438. sdhci_arasan->has_cqe = true;
  1439. host->mmc->caps2 |= MMC_CAP2_CQE;
  1440. if (!of_property_read_bool(np, "disable-cqe-dcmd"))
  1441. host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
  1442. }
  1443. ret = sdhci_arasan_add_host(sdhci_arasan);
  1444. if (ret)
  1445. goto err_add_host;
  1446. return 0;
  1447. err_add_host:
  1448. if (!IS_ERR(sdhci_arasan->phy))
  1449. phy_exit(sdhci_arasan->phy);
  1450. unreg_clk:
  1451. sdhci_arasan_unregister_sdclk(&pdev->dev);
  1452. clk_disable_all:
  1453. clk_disable_unprepare(clk_xin);
  1454. clk_dis_ahb:
  1455. clk_disable_unprepare(sdhci_arasan->clk_ahb);
  1456. err_pltfm_free:
  1457. sdhci_pltfm_free(pdev);
  1458. return ret;
  1459. }
  1460. static int sdhci_arasan_remove(struct platform_device *pdev)
  1461. {
  1462. int ret;
  1463. struct sdhci_host *host = platform_get_drvdata(pdev);
  1464. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1465. struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
  1466. struct clk *clk_ahb = sdhci_arasan->clk_ahb;
  1467. if (!IS_ERR(sdhci_arasan->phy)) {
  1468. if (sdhci_arasan->is_phy_on)
  1469. phy_power_off(sdhci_arasan->phy);
  1470. phy_exit(sdhci_arasan->phy);
  1471. }
  1472. sdhci_arasan_unregister_sdclk(&pdev->dev);
  1473. ret = sdhci_pltfm_unregister(pdev);
  1474. clk_disable_unprepare(clk_ahb);
  1475. return ret;
  1476. }
  1477. static struct platform_driver sdhci_arasan_driver = {
  1478. .driver = {
  1479. .name = "sdhci-arasan",
  1480. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1481. .of_match_table = sdhci_arasan_of_match,
  1482. .pm = &sdhci_arasan_dev_pm_ops,
  1483. },
  1484. .probe = sdhci_arasan_probe,
  1485. .remove = sdhci_arasan_remove,
  1486. };
  1487. module_platform_driver(sdhci_arasan_driver);
  1488. MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
  1489. MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
  1490. MODULE_LICENSE("GPL");