sdhci-iproc.c 12 KB

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  1. /*
  2. * Copyright (C) 2014 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. /*
  14. * iProc SDHCI platform driver
  15. */
  16. #include <linux/acpi.h>
  17. #include <linux/delay.h>
  18. #include <linux/module.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include "sdhci-pltfm.h"
  23. struct sdhci_iproc_data {
  24. const struct sdhci_pltfm_data *pdata;
  25. u32 caps;
  26. u32 caps1;
  27. u32 mmc_caps;
  28. };
  29. struct sdhci_iproc_host {
  30. const struct sdhci_iproc_data *data;
  31. u32 shadow_cmd;
  32. u32 shadow_blk;
  33. bool is_cmd_shadowed;
  34. bool is_blk_shadowed;
  35. };
  36. #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
  37. static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
  38. {
  39. u32 val = readl(host->ioaddr + reg);
  40. pr_debug("%s: readl [0x%02x] 0x%08x\n",
  41. mmc_hostname(host->mmc), reg, val);
  42. return val;
  43. }
  44. static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
  45. {
  46. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  47. struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
  48. u32 val;
  49. u16 word;
  50. if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
  51. /* Get the saved transfer mode */
  52. val = iproc_host->shadow_cmd;
  53. } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
  54. iproc_host->is_blk_shadowed) {
  55. /* Get the saved block info */
  56. val = iproc_host->shadow_blk;
  57. } else {
  58. val = sdhci_iproc_readl(host, (reg & ~3));
  59. }
  60. word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
  61. return word;
  62. }
  63. static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
  64. {
  65. u32 val = sdhci_iproc_readl(host, (reg & ~3));
  66. u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
  67. return byte;
  68. }
  69. static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
  70. {
  71. pr_debug("%s: writel [0x%02x] 0x%08x\n",
  72. mmc_hostname(host->mmc), reg, val);
  73. writel(val, host->ioaddr + reg);
  74. if (host->clock <= 400000) {
  75. /* Round up to micro-second four SD clock delay */
  76. if (host->clock)
  77. udelay((4 * 1000000 + host->clock - 1) / host->clock);
  78. else
  79. udelay(10);
  80. }
  81. }
  82. /*
  83. * The Arasan has a bugette whereby it may lose the content of successive
  84. * writes to the same register that are within two SD-card clock cycles of
  85. * each other (a clock domain crossing problem). The data
  86. * register does not have this problem, which is just as well - otherwise we'd
  87. * have to nobble the DMA engine too.
  88. *
  89. * This wouldn't be a problem with the code except that we can only write the
  90. * controller with 32-bit writes. So two different 16-bit registers are
  91. * written back to back creates the problem.
  92. *
  93. * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
  94. * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
  95. * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
  96. * the work around can be further optimized. We can keep shadow values of
  97. * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
  98. * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
  99. * by the TRANSFER+COMMAND in another 32-bit write.
  100. */
  101. static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
  102. {
  103. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  104. struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
  105. u32 word_shift = REG_OFFSET_IN_BITS(reg);
  106. u32 mask = 0xffff << word_shift;
  107. u32 oldval, newval;
  108. if (reg == SDHCI_COMMAND) {
  109. /* Write the block now as we are issuing a command */
  110. if (iproc_host->is_blk_shadowed) {
  111. sdhci_iproc_writel(host, iproc_host->shadow_blk,
  112. SDHCI_BLOCK_SIZE);
  113. iproc_host->is_blk_shadowed = false;
  114. }
  115. oldval = iproc_host->shadow_cmd;
  116. iproc_host->is_cmd_shadowed = false;
  117. } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
  118. iproc_host->is_blk_shadowed) {
  119. /* Block size and count are stored in shadow reg */
  120. oldval = iproc_host->shadow_blk;
  121. } else {
  122. /* Read reg, all other registers are not shadowed */
  123. oldval = sdhci_iproc_readl(host, (reg & ~3));
  124. }
  125. newval = (oldval & ~mask) | (val << word_shift);
  126. if (reg == SDHCI_TRANSFER_MODE) {
  127. /* Save the transfer mode until the command is issued */
  128. iproc_host->shadow_cmd = newval;
  129. iproc_host->is_cmd_shadowed = true;
  130. } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
  131. /* Save the block info until the command is issued */
  132. iproc_host->shadow_blk = newval;
  133. iproc_host->is_blk_shadowed = true;
  134. } else {
  135. /* Command or other regular 32-bit write */
  136. sdhci_iproc_writel(host, newval, reg & ~3);
  137. }
  138. }
  139. static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
  140. {
  141. u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
  142. u32 byte_shift = REG_OFFSET_IN_BITS(reg);
  143. u32 mask = 0xff << byte_shift;
  144. u32 newval = (oldval & ~mask) | (val << byte_shift);
  145. sdhci_iproc_writel(host, newval, reg & ~3);
  146. }
  147. static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
  148. {
  149. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  150. if (pltfm_host->clk)
  151. return sdhci_pltfm_clk_get_max_clock(host);
  152. else
  153. return pltfm_host->clock;
  154. }
  155. /*
  156. * There is a known bug on BCM2711's SDHCI core integration where the
  157. * controller will hang when the difference between the core clock and the bus
  158. * clock is too great. Specifically this can be reproduced under the following
  159. * conditions:
  160. *
  161. * - No SD card plugged in, polling thread is running, probing cards at
  162. * 100 kHz.
  163. * - BCM2711's core clock configured at 500MHz or more
  164. *
  165. * So we set 200kHz as the minimum clock frequency available for that SoC.
  166. */
  167. static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
  168. {
  169. return 200000;
  170. }
  171. static const struct sdhci_ops sdhci_iproc_ops = {
  172. .set_clock = sdhci_set_clock,
  173. .get_max_clock = sdhci_iproc_get_max_clock,
  174. .set_bus_width = sdhci_set_bus_width,
  175. .reset = sdhci_reset,
  176. .set_uhs_signaling = sdhci_set_uhs_signaling,
  177. };
  178. static const struct sdhci_ops sdhci_iproc_32only_ops = {
  179. .read_l = sdhci_iproc_readl,
  180. .read_w = sdhci_iproc_readw,
  181. .read_b = sdhci_iproc_readb,
  182. .write_l = sdhci_iproc_writel,
  183. .write_w = sdhci_iproc_writew,
  184. .write_b = sdhci_iproc_writeb,
  185. .set_clock = sdhci_set_clock,
  186. .get_max_clock = sdhci_iproc_get_max_clock,
  187. .set_bus_width = sdhci_set_bus_width,
  188. .reset = sdhci_reset,
  189. .set_uhs_signaling = sdhci_set_uhs_signaling,
  190. };
  191. static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
  192. .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  193. SDHCI_QUIRK_NO_HISPD_BIT,
  194. .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
  195. .ops = &sdhci_iproc_32only_ops,
  196. };
  197. static const struct sdhci_iproc_data iproc_cygnus_data = {
  198. .pdata = &sdhci_iproc_cygnus_pltfm_data,
  199. .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
  200. & SDHCI_MAX_BLOCK_MASK) |
  201. SDHCI_CAN_VDD_330 |
  202. SDHCI_CAN_VDD_180 |
  203. SDHCI_CAN_DO_SUSPEND |
  204. SDHCI_CAN_DO_HISPD |
  205. SDHCI_CAN_DO_ADMA2 |
  206. SDHCI_CAN_DO_SDMA,
  207. .caps1 = SDHCI_DRIVER_TYPE_C |
  208. SDHCI_DRIVER_TYPE_D |
  209. SDHCI_SUPPORT_DDR50,
  210. .mmc_caps = MMC_CAP_1_8V_DDR,
  211. };
  212. static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
  213. .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  214. SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
  215. SDHCI_QUIRK_NO_HISPD_BIT,
  216. .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
  217. .ops = &sdhci_iproc_ops,
  218. };
  219. static const struct sdhci_iproc_data iproc_data = {
  220. .pdata = &sdhci_iproc_pltfm_data,
  221. .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
  222. & SDHCI_MAX_BLOCK_MASK) |
  223. SDHCI_CAN_VDD_330 |
  224. SDHCI_CAN_VDD_180 |
  225. SDHCI_CAN_DO_SUSPEND |
  226. SDHCI_CAN_DO_HISPD |
  227. SDHCI_CAN_DO_ADMA2 |
  228. SDHCI_CAN_DO_SDMA,
  229. .caps1 = SDHCI_DRIVER_TYPE_C |
  230. SDHCI_DRIVER_TYPE_D |
  231. SDHCI_SUPPORT_DDR50,
  232. };
  233. static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
  234. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  235. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  236. SDHCI_QUIRK_MISSING_CAPS |
  237. SDHCI_QUIRK_NO_HISPD_BIT,
  238. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  239. .ops = &sdhci_iproc_32only_ops,
  240. };
  241. static const struct sdhci_iproc_data bcm2835_data = {
  242. .pdata = &sdhci_bcm2835_pltfm_data,
  243. .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
  244. & SDHCI_MAX_BLOCK_MASK) |
  245. SDHCI_CAN_VDD_330 |
  246. SDHCI_CAN_DO_HISPD,
  247. .caps1 = SDHCI_DRIVER_TYPE_A |
  248. SDHCI_DRIVER_TYPE_C,
  249. .mmc_caps = 0x00000000,
  250. };
  251. static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
  252. .read_l = sdhci_iproc_readl,
  253. .read_w = sdhci_iproc_readw,
  254. .read_b = sdhci_iproc_readb,
  255. .write_l = sdhci_iproc_writel,
  256. .write_w = sdhci_iproc_writew,
  257. .write_b = sdhci_iproc_writeb,
  258. .set_clock = sdhci_set_clock,
  259. .set_power = sdhci_set_power_and_bus_voltage,
  260. .get_max_clock = sdhci_iproc_get_max_clock,
  261. .get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
  262. .set_bus_width = sdhci_set_bus_width,
  263. .reset = sdhci_reset,
  264. .set_uhs_signaling = sdhci_set_uhs_signaling,
  265. };
  266. static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
  267. .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
  268. .ops = &sdhci_iproc_bcm2711_ops,
  269. };
  270. static const struct sdhci_iproc_data bcm2711_data = {
  271. .pdata = &sdhci_bcm2711_pltfm_data,
  272. .mmc_caps = MMC_CAP_3_3V_DDR,
  273. };
  274. static const struct of_device_id sdhci_iproc_of_match[] = {
  275. { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
  276. { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
  277. { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
  278. { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
  279. { }
  280. };
  281. MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
  282. #ifdef CONFIG_ACPI
  283. /*
  284. * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
  285. * which are provided by the ACPI table.
  286. */
  287. static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
  288. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  289. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  290. SDHCI_QUIRK_NO_HISPD_BIT,
  291. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
  292. .ops = &sdhci_iproc_32only_ops,
  293. };
  294. static const struct sdhci_iproc_data bcm_arasan_data = {
  295. .pdata = &sdhci_bcm_arasan_data,
  296. };
  297. static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
  298. { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
  299. { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
  300. { .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
  301. { .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
  302. { /* sentinel */ }
  303. };
  304. MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
  305. #endif
  306. static int sdhci_iproc_probe(struct platform_device *pdev)
  307. {
  308. struct device *dev = &pdev->dev;
  309. const struct sdhci_iproc_data *iproc_data = NULL;
  310. struct sdhci_host *host;
  311. struct sdhci_iproc_host *iproc_host;
  312. struct sdhci_pltfm_host *pltfm_host;
  313. int ret;
  314. iproc_data = device_get_match_data(dev);
  315. if (!iproc_data)
  316. return -ENODEV;
  317. host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
  318. if (IS_ERR(host))
  319. return PTR_ERR(host);
  320. pltfm_host = sdhci_priv(host);
  321. iproc_host = sdhci_pltfm_priv(pltfm_host);
  322. iproc_host->data = iproc_data;
  323. ret = mmc_of_parse(host->mmc);
  324. if (ret)
  325. goto err;
  326. sdhci_get_property(pdev);
  327. host->mmc->caps |= iproc_host->data->mmc_caps;
  328. if (dev->of_node) {
  329. pltfm_host->clk = devm_clk_get(dev, NULL);
  330. if (IS_ERR(pltfm_host->clk)) {
  331. ret = PTR_ERR(pltfm_host->clk);
  332. goto err;
  333. }
  334. ret = clk_prepare_enable(pltfm_host->clk);
  335. if (ret) {
  336. dev_err(dev, "failed to enable host clk\n");
  337. goto err;
  338. }
  339. }
  340. if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
  341. host->caps = iproc_host->data->caps;
  342. host->caps1 = iproc_host->data->caps1;
  343. }
  344. ret = sdhci_add_host(host);
  345. if (ret)
  346. goto err_clk;
  347. return 0;
  348. err_clk:
  349. if (dev->of_node)
  350. clk_disable_unprepare(pltfm_host->clk);
  351. err:
  352. sdhci_pltfm_free(pdev);
  353. return ret;
  354. }
  355. static struct platform_driver sdhci_iproc_driver = {
  356. .driver = {
  357. .name = "sdhci-iproc",
  358. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  359. .of_match_table = sdhci_iproc_of_match,
  360. .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
  361. .pm = &sdhci_pltfm_pmops,
  362. },
  363. .probe = sdhci_iproc_probe,
  364. .remove = sdhci_pltfm_unregister,
  365. };
  366. module_platform_driver(sdhci_iproc_driver);
  367. MODULE_AUTHOR("Broadcom");
  368. MODULE_DESCRIPTION("IPROC SDHCI driver");
  369. MODULE_LICENSE("GPL v2");