sdhci-esdhc.h 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Freescale eSDHC controller driver generics for OF and pltfm.
  4. *
  5. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  6. * Copyright (c) 2009 MontaVista Software, Inc.
  7. * Copyright (c) 2010 Pengutronix e.K.
  8. * Copyright 2020 NXP
  9. * Author: Wolfram Sang <kernel@pengutronix.de>
  10. */
  11. #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
  12. #define _DRIVERS_MMC_SDHCI_ESDHC_H
  13. /*
  14. * Ops and quirks for the Freescale eSDHC controller.
  15. */
  16. #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
  17. SDHCI_QUIRK_32BIT_DMA_ADDR | \
  18. SDHCI_QUIRK_NO_BUSY_IRQ | \
  19. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
  20. SDHCI_QUIRK_PIO_NEEDS_DELAY | \
  21. SDHCI_QUIRK_NO_HISPD_BIT)
  22. /* pltfm-specific */
  23. #define ESDHC_HOST_CONTROL_LE 0x20
  24. /*
  25. * eSDHC register definition
  26. */
  27. /* Present State Register */
  28. #define ESDHC_PRSSTAT 0x24
  29. #define ESDHC_CLOCK_GATE_OFF 0x00000080
  30. #define ESDHC_CLOCK_STABLE 0x00000008
  31. /* Protocol Control Register */
  32. #define ESDHC_PROCTL 0x28
  33. #define ESDHC_VOLT_SEL 0x00000400
  34. #define ESDHC_CTRL_4BITBUS (0x1 << 1)
  35. #define ESDHC_CTRL_8BITBUS (0x2 << 1)
  36. #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
  37. #define ESDHC_HOST_CONTROL_RES 0x01
  38. /* System Control Register */
  39. #define ESDHC_SYSTEM_CONTROL 0x2c
  40. #define ESDHC_CLOCK_MASK 0x0000fff0
  41. #define ESDHC_PREDIV_SHIFT 8
  42. #define ESDHC_DIVIDER_SHIFT 4
  43. #define ESDHC_CLOCK_SDCLKEN 0x00000008
  44. #define ESDHC_CLOCK_PEREN 0x00000004
  45. #define ESDHC_CLOCK_HCKEN 0x00000002
  46. #define ESDHC_CLOCK_IPGEN 0x00000001
  47. /* System Control 2 Register */
  48. #define ESDHC_SYSTEM_CONTROL_2 0x3c
  49. #define ESDHC_SMPCLKSEL 0x00800000
  50. #define ESDHC_EXTN 0x00400000
  51. /* Host Controller Capabilities Register 2 */
  52. #define ESDHC_CAPABILITIES_1 0x114
  53. /* Tuning Block Control Register */
  54. #define ESDHC_TBCTL 0x120
  55. #define ESDHC_HS400_WNDW_ADJUST 0x00000040
  56. #define ESDHC_HS400_MODE 0x00000010
  57. #define ESDHC_TB_EN 0x00000004
  58. #define ESDHC_TB_MODE_MASK 0x00000003
  59. #define ESDHC_TB_MODE_SW 0x00000003
  60. #define ESDHC_TB_MODE_3 0x00000002
  61. #define ESDHC_TBSTAT 0x124
  62. #define ESDHC_TBPTR 0x128
  63. #define ESDHC_WNDW_STRT_PTR_SHIFT 8
  64. #define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)
  65. #define ESDHC_WNDW_END_PTR_MASK 0x7f
  66. /* SD Clock Control Register */
  67. #define ESDHC_SDCLKCTL 0x144
  68. #define ESDHC_LPBK_CLK_SEL 0x80000000
  69. #define ESDHC_CMD_CLK_CTL 0x00008000
  70. /* SD Timing Control Register */
  71. #define ESDHC_SDTIMNGCTL 0x148
  72. #define ESDHC_FLW_CTL_BG 0x00008000
  73. /* DLL Config 0 Register */
  74. #define ESDHC_DLLCFG0 0x160
  75. #define ESDHC_DLL_ENABLE 0x80000000
  76. #define ESDHC_DLL_RESET 0x40000000
  77. #define ESDHC_DLL_FREQ_SEL 0x08000000
  78. /* DLL Config 1 Register */
  79. #define ESDHC_DLLCFG1 0x164
  80. #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
  81. /* DLL Status 0 Register */
  82. #define ESDHC_DLLSTAT0 0x170
  83. #define ESDHC_DLL_STS_SLV_LOCK 0x08000000
  84. /* Control Register for DMA transfer */
  85. #define ESDHC_DMA_SYSCTL 0x40c
  86. #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
  87. #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
  88. #define ESDHC_DMA_SNOOP 0x00000040
  89. #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */