sdhci-esdhc-mcf.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale eSDHC ColdFire family controller driver, platform bus.
  4. *
  5. * Copyright (c) 2020 Timesys Corporation
  6. * Author: Angelo Dureghello <angelo.dureghello@timesys.it>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/delay.h>
  10. #include <linux/platform_data/mmc-esdhc-mcf.h>
  11. #include <linux/mmc/mmc.h>
  12. #include "sdhci-pltfm.h"
  13. #include "sdhci-esdhc.h"
  14. #define ESDHC_PROCTL_D3CD 0x08
  15. #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
  16. #define ESDHC_DEFAULT_HOST_CONTROL 0x28
  17. /*
  18. * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
  19. */
  20. #define ESDHC_INT_VENDOR_SPEC_DMA_ERR BIT(28)
  21. struct pltfm_mcf_data {
  22. struct clk *clk_ipg;
  23. struct clk *clk_ahb;
  24. struct clk *clk_per;
  25. int aside;
  26. int current_bus_width;
  27. };
  28. static inline void esdhc_mcf_buffer_swap32(u32 *buf, int len)
  29. {
  30. int i;
  31. u32 temp;
  32. len = (len + 3) >> 2;
  33. for (i = 0; i < len; i++) {
  34. temp = swab32(*buf);
  35. *buf++ = temp;
  36. }
  37. }
  38. static inline void esdhc_clrset_be(struct sdhci_host *host,
  39. u32 mask, u32 val, int reg)
  40. {
  41. void __iomem *base = host->ioaddr + (reg & ~3);
  42. u8 shift = (reg & 3) << 3;
  43. mask <<= shift;
  44. val <<= shift;
  45. if (reg == SDHCI_HOST_CONTROL)
  46. val |= ESDHC_PROCTL_D3CD;
  47. writel((readl(base) & ~mask) | val, base);
  48. }
  49. /*
  50. * Note: mcf is big-endian, single bytes need to be accessed at big endian
  51. * offsets.
  52. */
  53. static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
  54. {
  55. void __iomem *base = host->ioaddr + (reg & ~3);
  56. u8 shift = (reg & 3) << 3;
  57. u32 mask = ~(0xff << shift);
  58. if (reg == SDHCI_HOST_CONTROL) {
  59. u32 host_ctrl = ESDHC_DEFAULT_HOST_CONTROL;
  60. u8 dma_bits = (val & SDHCI_CTRL_DMA_MASK) >> 3;
  61. u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1);
  62. tmp &= ~0x03;
  63. tmp |= dma_bits;
  64. /*
  65. * Recomposition needed, restore always endianness and
  66. * keep D3CD and AI, just setting bus width.
  67. */
  68. host_ctrl |= val;
  69. host_ctrl |= (dma_bits << 8);
  70. writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  71. return;
  72. }
  73. writel((readl(base) & mask) | (val << shift), base);
  74. }
  75. static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
  76. {
  77. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  78. struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
  79. void __iomem *base = host->ioaddr + (reg & ~3);
  80. u8 shift = (reg & 3) << 3;
  81. u32 mask = ~(0xffff << shift);
  82. switch (reg) {
  83. case SDHCI_TRANSFER_MODE:
  84. mcf_data->aside = val;
  85. return;
  86. case SDHCI_COMMAND:
  87. if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
  88. val |= SDHCI_CMD_ABORTCMD;
  89. /*
  90. * As for the fsl driver,
  91. * we have to set the mode in a single write here.
  92. */
  93. writel(val << 16 | mcf_data->aside,
  94. host->ioaddr + SDHCI_TRANSFER_MODE);
  95. return;
  96. }
  97. writel((readl(base) & mask) | (val << shift), base);
  98. }
  99. static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg)
  100. {
  101. writel(val, host->ioaddr + reg);
  102. }
  103. static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg)
  104. {
  105. if (reg == SDHCI_HOST_CONTROL) {
  106. u8 __iomem *base = host->ioaddr + (reg & ~3);
  107. u16 val = readw(base + 2);
  108. u8 dma_bits = (val >> 5) & SDHCI_CTRL_DMA_MASK;
  109. u8 host_ctrl = val & 0xff;
  110. host_ctrl &= ~SDHCI_CTRL_DMA_MASK;
  111. host_ctrl |= dma_bits;
  112. return host_ctrl;
  113. }
  114. return readb(host->ioaddr + (reg ^ 0x3));
  115. }
  116. static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg)
  117. {
  118. /*
  119. * For SDHCI_HOST_VERSION, sdhci specs defines 0xFE,
  120. * a wrong offset for us, we are at 0xFC.
  121. */
  122. if (reg == SDHCI_HOST_VERSION)
  123. reg -= 2;
  124. return readw(host->ioaddr + (reg ^ 0x2));
  125. }
  126. static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg)
  127. {
  128. u32 val;
  129. val = readl(host->ioaddr + reg);
  130. /*
  131. * RM (25.3.9) sd pin clock must never exceed 25Mhz.
  132. * So forcing legacy mode at 25Mhz.
  133. */
  134. if (unlikely(reg == SDHCI_CAPABILITIES))
  135. val &= ~SDHCI_CAN_DO_HISPD;
  136. if (unlikely(reg == SDHCI_INT_STATUS)) {
  137. if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
  138. val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
  139. val |= SDHCI_INT_ADMA_ERROR;
  140. }
  141. }
  142. return val;
  143. }
  144. static unsigned int esdhc_mcf_get_max_timeout_count(struct sdhci_host *host)
  145. {
  146. return 1 << 27;
  147. }
  148. static void esdhc_mcf_set_timeout(struct sdhci_host *host,
  149. struct mmc_command *cmd)
  150. {
  151. /* Use maximum timeout counter */
  152. esdhc_clrset_be(host, ESDHC_SYS_CTRL_DTOCV_MASK, 0xE,
  153. SDHCI_TIMEOUT_CONTROL);
  154. }
  155. static void esdhc_mcf_reset(struct sdhci_host *host, u8 mask)
  156. {
  157. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  158. struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
  159. sdhci_reset(host, mask);
  160. esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
  161. mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
  162. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  163. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  164. }
  165. static unsigned int esdhc_mcf_pltfm_get_max_clock(struct sdhci_host *host)
  166. {
  167. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  168. return pltfm_host->clock;
  169. }
  170. static unsigned int esdhc_mcf_pltfm_get_min_clock(struct sdhci_host *host)
  171. {
  172. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  173. return pltfm_host->clock / 256 / 16;
  174. }
  175. static void esdhc_mcf_pltfm_set_clock(struct sdhci_host *host,
  176. unsigned int clock)
  177. {
  178. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  179. unsigned long *pll_dr = (unsigned long *)MCF_PLL_DR;
  180. u32 fvco, fsys, fesdhc, temp;
  181. const int sdclkfs[] = {2, 4, 8, 16, 32, 64, 128, 256};
  182. int delta, old_delta = clock;
  183. int i, q, ri, rq;
  184. if (clock == 0) {
  185. host->mmc->actual_clock = 0;
  186. return;
  187. }
  188. /*
  189. * ColdFire eSDHC clock.s
  190. *
  191. * pll -+-> / outdiv1 --> fsys
  192. * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS
  193. *
  194. * mcf5441x datasheet says:
  195. * (8.1.2) eSDHC should be 40 MHz max
  196. * (25.3.9) eSDHC input is, as example, 96 Mhz ...
  197. * (25.3.9) sd pin clock must never exceed 25Mhz
  198. *
  199. * fvco = fsys * outdvi1 + 1
  200. * fshdc = fvco / outdiv3 + 1
  201. */
  202. temp = readl(pll_dr);
  203. fsys = pltfm_host->clock;
  204. fvco = fsys * ((temp & 0x1f) + 1);
  205. fesdhc = fvco / (((temp >> 10) & 0x1f) + 1);
  206. for (i = 0; i < 8; ++i) {
  207. int result = fesdhc / sdclkfs[i];
  208. for (q = 1; q < 17; ++q) {
  209. int finale = result / q;
  210. delta = abs(clock - finale);
  211. if (delta < old_delta) {
  212. old_delta = delta;
  213. ri = i;
  214. rq = q;
  215. }
  216. }
  217. }
  218. /*
  219. * Apply divisors and re-enable all the clocks
  220. */
  221. temp = ((sdclkfs[ri] >> 1) << 8) | ((rq - 1) << 4) |
  222. (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN);
  223. esdhc_clrset_be(host, 0x0000fff7, temp, SDHCI_CLOCK_CONTROL);
  224. host->mmc->actual_clock = clock;
  225. mdelay(1);
  226. }
  227. static void esdhc_mcf_pltfm_set_bus_width(struct sdhci_host *host, int width)
  228. {
  229. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  230. struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
  231. switch (width) {
  232. case MMC_BUS_WIDTH_4:
  233. mcf_data->current_bus_width = ESDHC_CTRL_4BITBUS;
  234. break;
  235. default:
  236. mcf_data->current_bus_width = 0;
  237. break;
  238. }
  239. esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
  240. mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
  241. }
  242. static void esdhc_mcf_request_done(struct sdhci_host *host,
  243. struct mmc_request *mrq)
  244. {
  245. struct scatterlist *sg;
  246. u32 *buffer;
  247. int i;
  248. if (!mrq->data || !mrq->data->bytes_xfered)
  249. goto exit_done;
  250. if (mmc_get_dma_dir(mrq->data) != DMA_FROM_DEVICE)
  251. goto exit_done;
  252. /*
  253. * On mcf5441x there is no hw sdma option/flag to select the dma
  254. * transfer endiannes. A swap after the transfer is needed.
  255. */
  256. for_each_sg(mrq->data->sg, sg, mrq->data->sg_len, i) {
  257. buffer = (u32 *)sg_virt(sg);
  258. esdhc_mcf_buffer_swap32(buffer, sg->length);
  259. }
  260. exit_done:
  261. mmc_request_done(host->mmc, mrq);
  262. }
  263. static void esdhc_mcf_copy_to_bounce_buffer(struct sdhci_host *host,
  264. struct mmc_data *data,
  265. unsigned int length)
  266. {
  267. sg_copy_to_buffer(data->sg, data->sg_len,
  268. host->bounce_buffer, length);
  269. esdhc_mcf_buffer_swap32((u32 *)host->bounce_buffer,
  270. data->blksz * data->blocks);
  271. }
  272. static struct sdhci_ops sdhci_esdhc_ops = {
  273. .reset = esdhc_mcf_reset,
  274. .set_clock = esdhc_mcf_pltfm_set_clock,
  275. .get_max_clock = esdhc_mcf_pltfm_get_max_clock,
  276. .get_min_clock = esdhc_mcf_pltfm_get_min_clock,
  277. .set_bus_width = esdhc_mcf_pltfm_set_bus_width,
  278. .get_max_timeout_count = esdhc_mcf_get_max_timeout_count,
  279. .set_timeout = esdhc_mcf_set_timeout,
  280. .write_b = esdhc_mcf_writeb_be,
  281. .write_w = esdhc_mcf_writew_be,
  282. .write_l = esdhc_mcf_writel_be,
  283. .read_b = esdhc_mcf_readb_be,
  284. .read_w = esdhc_mcf_readw_be,
  285. .read_l = esdhc_mcf_readl_be,
  286. .copy_to_bounce_buffer = esdhc_mcf_copy_to_bounce_buffer,
  287. .request_done = esdhc_mcf_request_done,
  288. };
  289. static const struct sdhci_pltfm_data sdhci_esdhc_mcf_pdata = {
  290. .ops = &sdhci_esdhc_ops,
  291. .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_FORCE_DMA,
  292. /*
  293. * Mandatory quirk,
  294. * controller does not support cmd23,
  295. * without, on > 8G cards cmd23 is used, and
  296. * driver times out.
  297. */
  298. SDHCI_QUIRK2_HOST_NO_CMD23,
  299. };
  300. static int esdhc_mcf_plat_init(struct sdhci_host *host,
  301. struct pltfm_mcf_data *mcf_data)
  302. {
  303. struct mcf_esdhc_platform_data *plat_data;
  304. if (!host->mmc->parent->platform_data) {
  305. dev_err(mmc_dev(host->mmc), "no platform data!\n");
  306. return -EINVAL;
  307. }
  308. plat_data = (struct mcf_esdhc_platform_data *)
  309. host->mmc->parent->platform_data;
  310. /* Card_detect */
  311. switch (plat_data->cd_type) {
  312. default:
  313. case ESDHC_CD_CONTROLLER:
  314. /* We have a working card_detect back */
  315. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  316. break;
  317. case ESDHC_CD_PERMANENT:
  318. host->mmc->caps |= MMC_CAP_NONREMOVABLE;
  319. break;
  320. case ESDHC_CD_NONE:
  321. break;
  322. }
  323. switch (plat_data->max_bus_width) {
  324. case 4:
  325. host->mmc->caps |= MMC_CAP_4_BIT_DATA;
  326. break;
  327. case 1:
  328. default:
  329. host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
  330. break;
  331. }
  332. return 0;
  333. }
  334. static int sdhci_esdhc_mcf_probe(struct platform_device *pdev)
  335. {
  336. struct sdhci_host *host;
  337. struct sdhci_pltfm_host *pltfm_host;
  338. struct pltfm_mcf_data *mcf_data;
  339. int err;
  340. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_mcf_pdata,
  341. sizeof(*mcf_data));
  342. if (IS_ERR(host))
  343. return PTR_ERR(host);
  344. pltfm_host = sdhci_priv(host);
  345. mcf_data = sdhci_pltfm_priv(pltfm_host);
  346. host->sdma_boundary = 0;
  347. host->flags |= SDHCI_AUTO_CMD12;
  348. mcf_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  349. if (IS_ERR(mcf_data->clk_ipg)) {
  350. err = PTR_ERR(mcf_data->clk_ipg);
  351. goto err_exit;
  352. }
  353. mcf_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  354. if (IS_ERR(mcf_data->clk_ahb)) {
  355. err = PTR_ERR(mcf_data->clk_ahb);
  356. goto err_exit;
  357. }
  358. mcf_data->clk_per = devm_clk_get(&pdev->dev, "per");
  359. if (IS_ERR(mcf_data->clk_per)) {
  360. err = PTR_ERR(mcf_data->clk_per);
  361. goto err_exit;
  362. }
  363. pltfm_host->clk = mcf_data->clk_per;
  364. pltfm_host->clock = clk_get_rate(pltfm_host->clk);
  365. err = clk_prepare_enable(mcf_data->clk_per);
  366. if (err)
  367. goto err_exit;
  368. err = clk_prepare_enable(mcf_data->clk_ipg);
  369. if (err)
  370. goto unprep_per;
  371. err = clk_prepare_enable(mcf_data->clk_ahb);
  372. if (err)
  373. goto unprep_ipg;
  374. err = esdhc_mcf_plat_init(host, mcf_data);
  375. if (err)
  376. goto unprep_ahb;
  377. err = sdhci_setup_host(host);
  378. if (err)
  379. goto unprep_ahb;
  380. if (!host->bounce_buffer) {
  381. dev_err(&pdev->dev, "bounce buffer not allocated");
  382. err = -ENOMEM;
  383. goto cleanup;
  384. }
  385. err = __sdhci_add_host(host);
  386. if (err)
  387. goto cleanup;
  388. return 0;
  389. cleanup:
  390. sdhci_cleanup_host(host);
  391. unprep_ahb:
  392. clk_disable_unprepare(mcf_data->clk_ahb);
  393. unprep_ipg:
  394. clk_disable_unprepare(mcf_data->clk_ipg);
  395. unprep_per:
  396. clk_disable_unprepare(mcf_data->clk_per);
  397. err_exit:
  398. sdhci_pltfm_free(pdev);
  399. return err;
  400. }
  401. static int sdhci_esdhc_mcf_remove(struct platform_device *pdev)
  402. {
  403. struct sdhci_host *host = platform_get_drvdata(pdev);
  404. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  405. struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
  406. sdhci_remove_host(host, 0);
  407. clk_disable_unprepare(mcf_data->clk_ipg);
  408. clk_disable_unprepare(mcf_data->clk_ahb);
  409. clk_disable_unprepare(mcf_data->clk_per);
  410. sdhci_pltfm_free(pdev);
  411. return 0;
  412. }
  413. static struct platform_driver sdhci_esdhc_mcf_driver = {
  414. .driver = {
  415. .name = "sdhci-esdhc-mcf",
  416. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  417. },
  418. .probe = sdhci_esdhc_mcf_probe,
  419. .remove = sdhci_esdhc_mcf_remove,
  420. };
  421. module_platform_driver(sdhci_esdhc_mcf_driver);
  422. MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
  423. MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com>");
  424. MODULE_LICENSE("GPL v2");