sdhci-esdhc-imx.c 58 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale eSDHC i.MX controller driver for the platform bus.
  4. *
  5. * derived from the OF-version.
  6. *
  7. * Copyright (c) 2010 Pengutronix e.K.
  8. * Author: Wolfram Sang <kernel@pengutronix.de>
  9. */
  10. #include <linux/bitfield.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/clk.h>
  16. #include <linux/module.h>
  17. #include <linux/slab.h>
  18. #include <linux/pm_qos.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/mmc.h>
  21. #include <linux/mmc/sdio.h>
  22. #include <linux/mmc/slot-gpio.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/pinctrl/consumer.h>
  26. #include <linux/platform_data/mmc-esdhc-imx.h>
  27. #include <linux/pm_runtime.h>
  28. #include "sdhci-pltfm.h"
  29. #include "sdhci-esdhc.h"
  30. #include "cqhci.h"
  31. #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
  32. #define ESDHC_CTRL_D3CD 0x08
  33. #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
  34. /* VENDOR SPEC register */
  35. #define ESDHC_VENDOR_SPEC 0xc0
  36. #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
  37. #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
  38. #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  39. #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
  40. #define ESDHC_DEBUG_SEL_REG 0xc3
  41. #define ESDHC_DEBUG_SEL_MASK 0xf
  42. #define ESDHC_DEBUG_SEL_CMD_STATE 1
  43. #define ESDHC_DEBUG_SEL_DATA_STATE 2
  44. #define ESDHC_DEBUG_SEL_TRANS_STATE 3
  45. #define ESDHC_DEBUG_SEL_DMA_STATE 4
  46. #define ESDHC_DEBUG_SEL_ADMA_STATE 5
  47. #define ESDHC_DEBUG_SEL_FIFO_STATE 6
  48. #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
  49. #define ESDHC_WTMK_LVL 0x44
  50. #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
  51. #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
  52. #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
  53. #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
  54. #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
  55. #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
  56. #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
  57. #define ESDHC_MIX_CTRL 0x48
  58. #define ESDHC_MIX_CTRL_DDREN (1 << 3)
  59. #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
  60. #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
  61. #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
  62. #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
  63. #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
  64. #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
  65. #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
  66. /* Bits 3 and 6 are not SDHCI standard definitions */
  67. #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
  68. /* Tuning bits */
  69. #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
  70. /* dll control register */
  71. #define ESDHC_DLL_CTRL 0x60
  72. #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
  73. #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
  74. /* tune control register */
  75. #define ESDHC_TUNE_CTRL_STATUS 0x68
  76. #define ESDHC_TUNE_CTRL_STEP 1
  77. #define ESDHC_TUNE_CTRL_MIN 0
  78. #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
  79. /* strobe dll register */
  80. #define ESDHC_STROBE_DLL_CTRL 0x70
  81. #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
  82. #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
  83. #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
  84. #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
  85. #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
  86. #define ESDHC_STROBE_DLL_STATUS 0x74
  87. #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
  88. #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
  89. #define ESDHC_VEND_SPEC2 0xc8
  90. #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
  91. #define ESDHC_TUNING_CTRL 0xcc
  92. #define ESDHC_STD_TUNING_EN (1 << 24)
  93. /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  94. #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
  95. #define ESDHC_TUNING_START_TAP_MASK 0x7f
  96. #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
  97. #define ESDHC_TUNING_STEP_MASK 0x00070000
  98. #define ESDHC_TUNING_STEP_SHIFT 16
  99. /* pinctrl state */
  100. #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
  101. #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
  102. /*
  103. * Our interpretation of the SDHCI_HOST_CONTROL register
  104. */
  105. #define ESDHC_CTRL_4BITBUS (0x1 << 1)
  106. #define ESDHC_CTRL_8BITBUS (0x2 << 1)
  107. #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
  108. /*
  109. * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
  110. * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  111. * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  112. * Define this macro DMA error INT for fsl eSDHC
  113. */
  114. #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
  115. /* the address offset of CQHCI */
  116. #define ESDHC_CQHCI_ADDR_OFFSET 0x100
  117. /*
  118. * The CMDTYPE of the CMD register (offset 0xE) should be set to
  119. * "11" when the STOP CMD12 is issued on imx53 to abort one
  120. * open ended multi-blk IO. Otherwise the TC INT wouldn't
  121. * be generated.
  122. * In exact block transfer, the controller doesn't complete the
  123. * operations automatically as required at the end of the
  124. * transfer and remains on hold if the abort command is not sent.
  125. * As a result, the TC flag is not asserted and SW received timeout
  126. * exception. Bit1 of Vendor Spec register is used to fix it.
  127. */
  128. #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
  129. /*
  130. * The flag tells that the ESDHC controller is an USDHC block that is
  131. * integrated on the i.MX6 series.
  132. */
  133. #define ESDHC_FLAG_USDHC BIT(3)
  134. /* The IP supports manual tuning process */
  135. #define ESDHC_FLAG_MAN_TUNING BIT(4)
  136. /* The IP supports standard tuning process */
  137. #define ESDHC_FLAG_STD_TUNING BIT(5)
  138. /* The IP has SDHCI_CAPABILITIES_1 register */
  139. #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
  140. /*
  141. * The IP has erratum ERR004536
  142. * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
  143. * when reading data from the card
  144. * This flag is also set for i.MX25 and i.MX35 in order to get
  145. * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
  146. */
  147. #define ESDHC_FLAG_ERR004536 BIT(7)
  148. /* The IP supports HS200 mode */
  149. #define ESDHC_FLAG_HS200 BIT(8)
  150. /* The IP supports HS400 mode */
  151. #define ESDHC_FLAG_HS400 BIT(9)
  152. /*
  153. * The IP has errata ERR010450
  154. * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
  155. * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
  156. */
  157. #define ESDHC_FLAG_ERR010450 BIT(10)
  158. /* The IP supports HS400ES mode */
  159. #define ESDHC_FLAG_HS400_ES BIT(11)
  160. /* The IP has Host Controller Interface for Command Queuing */
  161. #define ESDHC_FLAG_CQHCI BIT(12)
  162. /* need request pmqos during low power */
  163. #define ESDHC_FLAG_PMQOS BIT(13)
  164. /* The IP state got lost in low power mode */
  165. #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
  166. /* The IP lost clock rate in PM_RUNTIME */
  167. #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
  168. /*
  169. * The IP do not support the ACMD23 feature completely when use ADMA mode.
  170. * In ADMA mode, it only use the 16 bit block count of the register 0x4
  171. * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
  172. * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
  173. * write operation in RPMB, because RPMB reliable write need to set the bit31
  174. * of the CMD23's argument.
  175. * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
  176. * do not has this limitation. so when these SoC use ADMA mode, it need to
  177. * disable the ACMD23 feature.
  178. */
  179. #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
  180. struct esdhc_soc_data {
  181. u32 flags;
  182. };
  183. static const struct esdhc_soc_data esdhc_imx25_data = {
  184. .flags = ESDHC_FLAG_ERR004536,
  185. };
  186. static const struct esdhc_soc_data esdhc_imx35_data = {
  187. .flags = ESDHC_FLAG_ERR004536,
  188. };
  189. static const struct esdhc_soc_data esdhc_imx51_data = {
  190. .flags = 0,
  191. };
  192. static const struct esdhc_soc_data esdhc_imx53_data = {
  193. .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
  194. };
  195. static const struct esdhc_soc_data usdhc_imx6q_data = {
  196. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
  197. | ESDHC_FLAG_BROKEN_AUTO_CMD23,
  198. };
  199. static const struct esdhc_soc_data usdhc_imx6sl_data = {
  200. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  201. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
  202. | ESDHC_FLAG_HS200
  203. | ESDHC_FLAG_BROKEN_AUTO_CMD23,
  204. };
  205. static const struct esdhc_soc_data usdhc_imx6sll_data = {
  206. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  207. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  208. | ESDHC_FLAG_HS400
  209. | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
  210. };
  211. static const struct esdhc_soc_data usdhc_imx6sx_data = {
  212. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  213. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  214. | ESDHC_FLAG_STATE_LOST_IN_LPMODE
  215. | ESDHC_FLAG_BROKEN_AUTO_CMD23,
  216. };
  217. static const struct esdhc_soc_data usdhc_imx6ull_data = {
  218. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  219. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  220. | ESDHC_FLAG_ERR010450
  221. | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
  222. };
  223. static const struct esdhc_soc_data usdhc_imx7d_data = {
  224. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  225. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  226. | ESDHC_FLAG_HS400
  227. | ESDHC_FLAG_STATE_LOST_IN_LPMODE
  228. | ESDHC_FLAG_BROKEN_AUTO_CMD23,
  229. };
  230. static struct esdhc_soc_data usdhc_imx7ulp_data = {
  231. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  232. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  233. | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
  234. | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
  235. };
  236. static struct esdhc_soc_data usdhc_imx8qxp_data = {
  237. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  238. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  239. | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
  240. | ESDHC_FLAG_STATE_LOST_IN_LPMODE
  241. | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
  242. };
  243. static struct esdhc_soc_data usdhc_imx8mm_data = {
  244. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  245. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  246. | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
  247. | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
  248. };
  249. struct pltfm_imx_data {
  250. u32 scratchpad;
  251. struct pinctrl *pinctrl;
  252. struct pinctrl_state *pins_100mhz;
  253. struct pinctrl_state *pins_200mhz;
  254. const struct esdhc_soc_data *socdata;
  255. struct esdhc_platform_data boarddata;
  256. struct clk *clk_ipg;
  257. struct clk *clk_ahb;
  258. struct clk *clk_per;
  259. unsigned int actual_clock;
  260. enum {
  261. NO_CMD_PENDING, /* no multiblock command pending */
  262. MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
  263. WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
  264. } multiblock_status;
  265. u32 is_ddr;
  266. struct pm_qos_request pm_qos_req;
  267. };
  268. static const struct platform_device_id imx_esdhc_devtype[] = {
  269. {
  270. .name = "sdhci-esdhc-imx25",
  271. .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
  272. }, {
  273. .name = "sdhci-esdhc-imx35",
  274. .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
  275. }, {
  276. .name = "sdhci-esdhc-imx51",
  277. .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
  278. }, {
  279. /* sentinel */
  280. }
  281. };
  282. MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
  283. static const struct of_device_id imx_esdhc_dt_ids[] = {
  284. { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
  285. { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
  286. { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
  287. { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
  288. { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
  289. { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
  290. { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
  291. { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
  292. { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
  293. { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
  294. { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
  295. { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
  296. { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
  297. { /* sentinel */ }
  298. };
  299. MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
  300. static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
  301. {
  302. return data->socdata == &esdhc_imx25_data;
  303. }
  304. static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
  305. {
  306. return data->socdata == &esdhc_imx53_data;
  307. }
  308. static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
  309. {
  310. return data->socdata == &usdhc_imx6q_data;
  311. }
  312. static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
  313. {
  314. return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
  315. }
  316. static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
  317. {
  318. void __iomem *base = host->ioaddr + (reg & ~0x3);
  319. u32 shift = (reg & 0x3) * 8;
  320. writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
  321. }
  322. #define DRIVER_NAME "sdhci-esdhc-imx"
  323. #define ESDHC_IMX_DUMP(f, x...) \
  324. pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  325. static void esdhc_dump_debug_regs(struct sdhci_host *host)
  326. {
  327. int i;
  328. char *debug_status[7] = {
  329. "cmd debug status",
  330. "data debug status",
  331. "trans debug status",
  332. "dma debug status",
  333. "adma debug status",
  334. "fifo debug status",
  335. "async fifo debug status"
  336. };
  337. ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
  338. for (i = 0; i < 7; i++) {
  339. esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
  340. ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
  341. ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
  342. readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
  343. }
  344. esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
  345. }
  346. static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
  347. {
  348. u32 present_state;
  349. int ret;
  350. ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
  351. (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
  352. if (ret == -ETIMEDOUT)
  353. dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
  354. }
  355. static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
  356. {
  357. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  358. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  359. u32 val = readl(host->ioaddr + reg);
  360. if (unlikely(reg == SDHCI_PRESENT_STATE)) {
  361. u32 fsl_prss = val;
  362. /* save the least 20 bits */
  363. val = fsl_prss & 0x000FFFFF;
  364. /* move dat[0-3] bits */
  365. val |= (fsl_prss & 0x0F000000) >> 4;
  366. /* move cmd line bit */
  367. val |= (fsl_prss & 0x00800000) << 1;
  368. }
  369. if (unlikely(reg == SDHCI_CAPABILITIES)) {
  370. /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
  371. if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
  372. val &= 0xffff0000;
  373. /* In FSL esdhc IC module, only bit20 is used to indicate the
  374. * ADMA2 capability of esdhc, but this bit is messed up on
  375. * some SOCs (e.g. on MX25, MX35 this bit is set, but they
  376. * don't actually support ADMA2). So set the BROKEN_ADMA
  377. * quirk on MX25/35 platforms.
  378. */
  379. if (val & SDHCI_CAN_DO_ADMA1) {
  380. val &= ~SDHCI_CAN_DO_ADMA1;
  381. val |= SDHCI_CAN_DO_ADMA2;
  382. }
  383. }
  384. if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
  385. if (esdhc_is_usdhc(imx_data)) {
  386. if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
  387. val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
  388. else
  389. /* imx6q/dl does not have cap_1 register, fake one */
  390. val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
  391. | SDHCI_SUPPORT_SDR50
  392. | SDHCI_USE_SDR50_TUNING
  393. | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
  394. SDHCI_TUNING_MODE_3);
  395. if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
  396. val |= SDHCI_SUPPORT_HS400;
  397. /*
  398. * Do not advertise faster UHS modes if there are no
  399. * pinctrl states for 100MHz/200MHz.
  400. */
  401. if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
  402. IS_ERR_OR_NULL(imx_data->pins_200mhz))
  403. val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
  404. | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
  405. }
  406. }
  407. if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
  408. val = 0;
  409. val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
  410. val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
  411. val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
  412. }
  413. if (unlikely(reg == SDHCI_INT_STATUS)) {
  414. if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
  415. val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
  416. val |= SDHCI_INT_ADMA_ERROR;
  417. }
  418. /*
  419. * mask off the interrupt we get in response to the manually
  420. * sent CMD12
  421. */
  422. if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
  423. ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
  424. val &= ~SDHCI_INT_RESPONSE;
  425. writel(SDHCI_INT_RESPONSE, host->ioaddr +
  426. SDHCI_INT_STATUS);
  427. imx_data->multiblock_status = NO_CMD_PENDING;
  428. }
  429. }
  430. return val;
  431. }
  432. static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
  433. {
  434. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  435. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  436. u32 data;
  437. if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
  438. reg == SDHCI_INT_STATUS)) {
  439. if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
  440. /*
  441. * Clear and then set D3CD bit to avoid missing the
  442. * card interrupt. This is an eSDHC controller problem
  443. * so we need to apply the following workaround: clear
  444. * and set D3CD bit will make eSDHC re-sample the card
  445. * interrupt. In case a card interrupt was lost,
  446. * re-sample it by the following steps.
  447. */
  448. data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
  449. data &= ~ESDHC_CTRL_D3CD;
  450. writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
  451. data |= ESDHC_CTRL_D3CD;
  452. writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
  453. }
  454. if (val & SDHCI_INT_ADMA_ERROR) {
  455. val &= ~SDHCI_INT_ADMA_ERROR;
  456. val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
  457. }
  458. }
  459. if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  460. && (reg == SDHCI_INT_STATUS)
  461. && (val & SDHCI_INT_DATA_END))) {
  462. u32 v;
  463. v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  464. v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
  465. writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
  466. if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
  467. {
  468. /* send a manual CMD12 with RESPTYP=none */
  469. data = MMC_STOP_TRANSMISSION << 24 |
  470. SDHCI_CMD_ABORTCMD << 16;
  471. writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
  472. imx_data->multiblock_status = WAIT_FOR_INT;
  473. }
  474. }
  475. writel(val, host->ioaddr + reg);
  476. }
  477. static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
  478. {
  479. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  480. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  481. u16 ret = 0;
  482. u32 val;
  483. if (unlikely(reg == SDHCI_HOST_VERSION)) {
  484. reg ^= 2;
  485. if (esdhc_is_usdhc(imx_data)) {
  486. /*
  487. * The usdhc register returns a wrong host version.
  488. * Correct it here.
  489. */
  490. return SDHCI_SPEC_300;
  491. }
  492. }
  493. if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
  494. val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  495. if (val & ESDHC_VENDOR_SPEC_VSELECT)
  496. ret |= SDHCI_CTRL_VDD_180;
  497. if (esdhc_is_usdhc(imx_data)) {
  498. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
  499. val = readl(host->ioaddr + ESDHC_MIX_CTRL);
  500. else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
  501. /* the std tuning bits is in ACMD12_ERR for imx6sl */
  502. val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  503. }
  504. if (val & ESDHC_MIX_CTRL_EXE_TUNE)
  505. ret |= SDHCI_CTRL_EXEC_TUNING;
  506. if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
  507. ret |= SDHCI_CTRL_TUNED_CLK;
  508. ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
  509. return ret;
  510. }
  511. if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
  512. if (esdhc_is_usdhc(imx_data)) {
  513. u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  514. ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
  515. /* Swap AC23 bit */
  516. if (m & ESDHC_MIX_CTRL_AC23EN) {
  517. ret &= ~ESDHC_MIX_CTRL_AC23EN;
  518. ret |= SDHCI_TRNS_AUTO_CMD23;
  519. }
  520. } else {
  521. ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
  522. }
  523. return ret;
  524. }
  525. return readw(host->ioaddr + reg);
  526. }
  527. static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
  528. {
  529. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  530. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  531. u32 new_val = 0;
  532. switch (reg) {
  533. case SDHCI_CLOCK_CONTROL:
  534. new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  535. if (val & SDHCI_CLOCK_CARD_EN)
  536. new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
  537. else
  538. new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
  539. writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
  540. if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
  541. esdhc_wait_for_card_clock_gate_off(host);
  542. return;
  543. case SDHCI_HOST_CONTROL2:
  544. new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  545. if (val & SDHCI_CTRL_VDD_180)
  546. new_val |= ESDHC_VENDOR_SPEC_VSELECT;
  547. else
  548. new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
  549. writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
  550. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
  551. new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
  552. if (val & SDHCI_CTRL_TUNED_CLK) {
  553. new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
  554. new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  555. } else {
  556. new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  557. new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  558. }
  559. writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
  560. } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
  561. u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  562. u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  563. if (val & SDHCI_CTRL_TUNED_CLK) {
  564. v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
  565. } else {
  566. v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  567. m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
  568. m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  569. }
  570. if (val & SDHCI_CTRL_EXEC_TUNING) {
  571. v |= ESDHC_MIX_CTRL_EXE_TUNE;
  572. m |= ESDHC_MIX_CTRL_FBCLK_SEL;
  573. m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  574. } else {
  575. v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
  576. }
  577. writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  578. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  579. }
  580. return;
  581. case SDHCI_TRANSFER_MODE:
  582. if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  583. && (host->cmd->opcode == SD_IO_RW_EXTENDED)
  584. && (host->cmd->data->blocks > 1)
  585. && (host->cmd->data->flags & MMC_DATA_READ)) {
  586. u32 v;
  587. v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  588. v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
  589. writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
  590. }
  591. if (esdhc_is_usdhc(imx_data)) {
  592. u32 wml;
  593. u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  594. /* Swap AC23 bit */
  595. if (val & SDHCI_TRNS_AUTO_CMD23) {
  596. val &= ~SDHCI_TRNS_AUTO_CMD23;
  597. val |= ESDHC_MIX_CTRL_AC23EN;
  598. }
  599. m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
  600. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  601. /* Set watermark levels for PIO access to maximum value
  602. * (128 words) to accommodate full 512 bytes buffer.
  603. * For DMA access restore the levels to default value.
  604. */
  605. m = readl(host->ioaddr + ESDHC_WTMK_LVL);
  606. if (val & SDHCI_TRNS_DMA) {
  607. wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
  608. } else {
  609. u8 ctrl;
  610. wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
  611. /*
  612. * Since already disable DMA mode, so also need
  613. * to clear the DMASEL. Otherwise, for standard
  614. * tuning, when send tuning command, usdhc will
  615. * still prefetch the ADMA script from wrong
  616. * DMA address, then we will see IOMMU report
  617. * some error which show lack of TLB mapping.
  618. */
  619. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  620. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  621. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  622. }
  623. m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
  624. ESDHC_WTMK_LVL_WR_WML_MASK);
  625. m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
  626. (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
  627. writel(m, host->ioaddr + ESDHC_WTMK_LVL);
  628. } else {
  629. /*
  630. * Postpone this write, we must do it together with a
  631. * command write that is down below.
  632. */
  633. imx_data->scratchpad = val;
  634. }
  635. return;
  636. case SDHCI_COMMAND:
  637. if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
  638. val |= SDHCI_CMD_ABORTCMD;
  639. if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
  640. (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
  641. imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
  642. if (esdhc_is_usdhc(imx_data))
  643. writel(val << 16,
  644. host->ioaddr + SDHCI_TRANSFER_MODE);
  645. else
  646. writel(val << 16 | imx_data->scratchpad,
  647. host->ioaddr + SDHCI_TRANSFER_MODE);
  648. return;
  649. case SDHCI_BLOCK_SIZE:
  650. val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  651. break;
  652. }
  653. esdhc_clrset_le(host, 0xffff, val, reg);
  654. }
  655. static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
  656. {
  657. u8 ret;
  658. u32 val;
  659. switch (reg) {
  660. case SDHCI_HOST_CONTROL:
  661. val = readl(host->ioaddr + reg);
  662. ret = val & SDHCI_CTRL_LED;
  663. ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
  664. ret |= (val & ESDHC_CTRL_4BITBUS);
  665. ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
  666. return ret;
  667. }
  668. return readb(host->ioaddr + reg);
  669. }
  670. static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
  671. {
  672. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  673. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  674. u32 new_val = 0;
  675. u32 mask;
  676. switch (reg) {
  677. case SDHCI_POWER_CONTROL:
  678. /*
  679. * FSL put some DMA bits here
  680. * If your board has a regulator, code should be here
  681. */
  682. return;
  683. case SDHCI_HOST_CONTROL:
  684. /* FSL messed up here, so we need to manually compose it. */
  685. new_val = val & SDHCI_CTRL_LED;
  686. /* ensure the endianness */
  687. new_val |= ESDHC_HOST_CONTROL_LE;
  688. /* bits 8&9 are reserved on mx25 */
  689. if (!is_imx25_esdhc(imx_data)) {
  690. /* DMA mode bits are shifted */
  691. new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
  692. }
  693. /*
  694. * Do not touch buswidth bits here. This is done in
  695. * esdhc_pltfm_bus_width.
  696. * Do not touch the D3CD bit either which is used for the
  697. * SDIO interrupt erratum workaround.
  698. */
  699. mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
  700. esdhc_clrset_le(host, mask, new_val, reg);
  701. return;
  702. case SDHCI_SOFTWARE_RESET:
  703. if (val & SDHCI_RESET_DATA)
  704. new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
  705. break;
  706. }
  707. esdhc_clrset_le(host, 0xff, val, reg);
  708. if (reg == SDHCI_SOFTWARE_RESET) {
  709. if (val & SDHCI_RESET_ALL) {
  710. /*
  711. * The esdhc has a design violation to SDHC spec which
  712. * tells that software reset should not affect card
  713. * detection circuit. But esdhc clears its SYSCTL
  714. * register bits [0..2] during the software reset. This
  715. * will stop those clocks that card detection circuit
  716. * relies on. To work around it, we turn the clocks on
  717. * back to keep card detection circuit functional.
  718. */
  719. esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
  720. /*
  721. * The reset on usdhc fails to clear MIX_CTRL register.
  722. * Do it manually here.
  723. */
  724. if (esdhc_is_usdhc(imx_data)) {
  725. /*
  726. * the tuning bits should be kept during reset
  727. */
  728. new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
  729. writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
  730. host->ioaddr + ESDHC_MIX_CTRL);
  731. imx_data->is_ddr = 0;
  732. }
  733. } else if (val & SDHCI_RESET_DATA) {
  734. /*
  735. * The eSDHC DAT line software reset clears at least the
  736. * data transfer width on i.MX25, so make sure that the
  737. * Host Control register is unaffected.
  738. */
  739. esdhc_clrset_le(host, 0xff, new_val,
  740. SDHCI_HOST_CONTROL);
  741. }
  742. }
  743. }
  744. static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
  745. {
  746. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  747. return pltfm_host->clock;
  748. }
  749. static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
  750. {
  751. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  752. return pltfm_host->clock / 256 / 16;
  753. }
  754. static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
  755. unsigned int clock)
  756. {
  757. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  758. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  759. unsigned int host_clock = pltfm_host->clock;
  760. int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
  761. int pre_div = 1;
  762. int div = 1;
  763. int ret;
  764. u32 temp, val;
  765. if (esdhc_is_usdhc(imx_data)) {
  766. val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  767. writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
  768. host->ioaddr + ESDHC_VENDOR_SPEC);
  769. esdhc_wait_for_card_clock_gate_off(host);
  770. }
  771. if (clock == 0) {
  772. host->mmc->actual_clock = 0;
  773. return;
  774. }
  775. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  776. if (is_imx53_esdhc(imx_data)) {
  777. /*
  778. * According to the i.MX53 reference manual, if DLLCTRL[10] can
  779. * be set, then the controller is eSDHCv3, else it is eSDHCv2.
  780. */
  781. val = readl(host->ioaddr + ESDHC_DLL_CTRL);
  782. writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
  783. temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
  784. writel(val, host->ioaddr + ESDHC_DLL_CTRL);
  785. if (temp & BIT(10))
  786. pre_div = 2;
  787. }
  788. temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  789. temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
  790. | ESDHC_CLOCK_MASK);
  791. sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
  792. if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
  793. unsigned int max_clock;
  794. max_clock = imx_data->is_ddr ? 45000000 : 150000000;
  795. clock = min(clock, max_clock);
  796. }
  797. while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
  798. pre_div < 256)
  799. pre_div *= 2;
  800. while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
  801. div++;
  802. host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
  803. dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
  804. clock, host->mmc->actual_clock);
  805. pre_div >>= 1;
  806. div--;
  807. temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  808. temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
  809. | (div << ESDHC_DIVIDER_SHIFT)
  810. | (pre_div << ESDHC_PREDIV_SHIFT));
  811. sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
  812. /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
  813. ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
  814. (temp & ESDHC_CLOCK_STABLE), 2, 100);
  815. if (ret == -ETIMEDOUT)
  816. dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
  817. if (esdhc_is_usdhc(imx_data)) {
  818. val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
  819. writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
  820. host->ioaddr + ESDHC_VENDOR_SPEC);
  821. }
  822. }
  823. static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
  824. {
  825. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  826. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  827. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  828. switch (boarddata->wp_type) {
  829. case ESDHC_WP_GPIO:
  830. return mmc_gpio_get_ro(host->mmc);
  831. case ESDHC_WP_CONTROLLER:
  832. return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  833. SDHCI_WRITE_PROTECT);
  834. case ESDHC_WP_NONE:
  835. break;
  836. }
  837. return -ENOSYS;
  838. }
  839. static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
  840. {
  841. u32 ctrl;
  842. switch (width) {
  843. case MMC_BUS_WIDTH_8:
  844. ctrl = ESDHC_CTRL_8BITBUS;
  845. break;
  846. case MMC_BUS_WIDTH_4:
  847. ctrl = ESDHC_CTRL_4BITBUS;
  848. break;
  849. default:
  850. ctrl = 0;
  851. break;
  852. }
  853. esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
  854. SDHCI_HOST_CONTROL);
  855. }
  856. static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
  857. {
  858. struct sdhci_host *host = mmc_priv(mmc);
  859. /*
  860. * i.MX uSDHC internally already uses a fixed optimized timing for
  861. * DDR50, normally does not require tuning for DDR50 mode.
  862. */
  863. if (host->timing == MMC_TIMING_UHS_DDR50)
  864. return 0;
  865. return sdhci_execute_tuning(mmc, opcode);
  866. }
  867. static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
  868. {
  869. u32 reg;
  870. u8 sw_rst;
  871. int ret;
  872. /* FIXME: delay a bit for card to be ready for next tuning due to errors */
  873. mdelay(1);
  874. /* IC suggest to reset USDHC before every tuning command */
  875. esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
  876. ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
  877. !(sw_rst & SDHCI_RESET_ALL), 10, 100);
  878. if (ret == -ETIMEDOUT)
  879. dev_warn(mmc_dev(host->mmc),
  880. "warning! RESET_ALL never complete before sending tuning command\n");
  881. reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
  882. reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
  883. ESDHC_MIX_CTRL_FBCLK_SEL;
  884. writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
  885. writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
  886. dev_dbg(mmc_dev(host->mmc),
  887. "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
  888. val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
  889. }
  890. static void esdhc_post_tuning(struct sdhci_host *host)
  891. {
  892. u32 reg;
  893. reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
  894. reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
  895. reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
  896. writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
  897. }
  898. static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
  899. {
  900. int min, max, avg, ret;
  901. /* find the mininum delay first which can pass tuning */
  902. min = ESDHC_TUNE_CTRL_MIN;
  903. while (min < ESDHC_TUNE_CTRL_MAX) {
  904. esdhc_prepare_tuning(host, min);
  905. if (!mmc_send_tuning(host->mmc, opcode, NULL))
  906. break;
  907. min += ESDHC_TUNE_CTRL_STEP;
  908. }
  909. /* find the maxinum delay which can not pass tuning */
  910. max = min + ESDHC_TUNE_CTRL_STEP;
  911. while (max < ESDHC_TUNE_CTRL_MAX) {
  912. esdhc_prepare_tuning(host, max);
  913. if (mmc_send_tuning(host->mmc, opcode, NULL)) {
  914. max -= ESDHC_TUNE_CTRL_STEP;
  915. break;
  916. }
  917. max += ESDHC_TUNE_CTRL_STEP;
  918. }
  919. /* use average delay to get the best timing */
  920. avg = (min + max) / 2;
  921. esdhc_prepare_tuning(host, avg);
  922. ret = mmc_send_tuning(host->mmc, opcode, NULL);
  923. esdhc_post_tuning(host);
  924. dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
  925. ret ? "failed" : "passed", avg, ret);
  926. return ret;
  927. }
  928. static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
  929. {
  930. struct sdhci_host *host = mmc_priv(mmc);
  931. u32 m;
  932. m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  933. if (ios->enhanced_strobe)
  934. m |= ESDHC_MIX_CTRL_HS400_ES_EN;
  935. else
  936. m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
  937. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  938. }
  939. static int esdhc_change_pinstate(struct sdhci_host *host,
  940. unsigned int uhs)
  941. {
  942. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  943. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  944. struct pinctrl_state *pinctrl;
  945. dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
  946. if (IS_ERR(imx_data->pinctrl) ||
  947. IS_ERR(imx_data->pins_100mhz) ||
  948. IS_ERR(imx_data->pins_200mhz))
  949. return -EINVAL;
  950. switch (uhs) {
  951. case MMC_TIMING_UHS_SDR50:
  952. case MMC_TIMING_UHS_DDR50:
  953. pinctrl = imx_data->pins_100mhz;
  954. break;
  955. case MMC_TIMING_UHS_SDR104:
  956. case MMC_TIMING_MMC_HS200:
  957. case MMC_TIMING_MMC_HS400:
  958. pinctrl = imx_data->pins_200mhz;
  959. break;
  960. default:
  961. /* back to default state for other legacy timing */
  962. return pinctrl_select_default_state(mmc_dev(host->mmc));
  963. }
  964. return pinctrl_select_state(imx_data->pinctrl, pinctrl);
  965. }
  966. /*
  967. * For HS400 eMMC, there is a data_strobe line. This signal is generated
  968. * by the device and used for data output and CRC status response output
  969. * in HS400 mode. The frequency of this signal follows the frequency of
  970. * CLK generated by host. The host receives the data which is aligned to the
  971. * edge of data_strobe line. Due to the time delay between CLK line and
  972. * data_strobe line, if the delay time is larger than one clock cycle,
  973. * then CLK and data_strobe line will be misaligned, read error shows up.
  974. */
  975. static void esdhc_set_strobe_dll(struct sdhci_host *host)
  976. {
  977. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  978. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  979. u32 strobe_delay;
  980. u32 v;
  981. int ret;
  982. /* disable clock before enabling strobe dll */
  983. writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
  984. ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
  985. host->ioaddr + ESDHC_VENDOR_SPEC);
  986. esdhc_wait_for_card_clock_gate_off(host);
  987. /* force a reset on strobe dll */
  988. writel(ESDHC_STROBE_DLL_CTRL_RESET,
  989. host->ioaddr + ESDHC_STROBE_DLL_CTRL);
  990. /* clear the reset bit on strobe dll before any setting */
  991. writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
  992. /*
  993. * enable strobe dll ctrl and adjust the delay target
  994. * for the uSDHC loopback read clock
  995. */
  996. if (imx_data->boarddata.strobe_dll_delay_target)
  997. strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
  998. else
  999. strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
  1000. v = ESDHC_STROBE_DLL_CTRL_ENABLE |
  1001. ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
  1002. (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  1003. writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
  1004. /* wait max 50us to get the REF/SLV lock */
  1005. ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
  1006. ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
  1007. if (ret == -ETIMEDOUT)
  1008. dev_warn(mmc_dev(host->mmc),
  1009. "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
  1010. }
  1011. static void esdhc_reset_tuning(struct sdhci_host *host)
  1012. {
  1013. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1014. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1015. u32 ctrl;
  1016. int ret;
  1017. /* Reset the tuning circuit */
  1018. if (esdhc_is_usdhc(imx_data)) {
  1019. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
  1020. ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
  1021. ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  1022. ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
  1023. writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
  1024. writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
  1025. } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
  1026. ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  1027. ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
  1028. ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
  1029. writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  1030. /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
  1031. ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
  1032. ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
  1033. if (ret == -ETIMEDOUT)
  1034. dev_warn(mmc_dev(host->mmc),
  1035. "Warning! clear execute tuning bit failed\n");
  1036. /*
  1037. * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
  1038. * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
  1039. * will finally make sure the normal data transfer logic correct.
  1040. */
  1041. ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
  1042. ctrl |= SDHCI_INT_DATA_AVAIL;
  1043. writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
  1044. }
  1045. }
  1046. }
  1047. static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
  1048. {
  1049. u32 m;
  1050. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1051. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1052. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  1053. /* disable ddr mode and disable HS400 mode */
  1054. m = readl(host->ioaddr + ESDHC_MIX_CTRL);
  1055. m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
  1056. imx_data->is_ddr = 0;
  1057. switch (timing) {
  1058. case MMC_TIMING_UHS_SDR12:
  1059. case MMC_TIMING_UHS_SDR25:
  1060. case MMC_TIMING_UHS_SDR50:
  1061. case MMC_TIMING_UHS_SDR104:
  1062. case MMC_TIMING_MMC_HS:
  1063. case MMC_TIMING_MMC_HS200:
  1064. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  1065. break;
  1066. case MMC_TIMING_UHS_DDR50:
  1067. case MMC_TIMING_MMC_DDR52:
  1068. m |= ESDHC_MIX_CTRL_DDREN;
  1069. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  1070. imx_data->is_ddr = 1;
  1071. if (boarddata->delay_line) {
  1072. u32 v;
  1073. v = boarddata->delay_line <<
  1074. ESDHC_DLL_OVERRIDE_VAL_SHIFT |
  1075. (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
  1076. if (is_imx53_esdhc(imx_data))
  1077. v <<= 1;
  1078. writel(v, host->ioaddr + ESDHC_DLL_CTRL);
  1079. }
  1080. break;
  1081. case MMC_TIMING_MMC_HS400:
  1082. m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
  1083. writel(m, host->ioaddr + ESDHC_MIX_CTRL);
  1084. imx_data->is_ddr = 1;
  1085. /* update clock after enable DDR for strobe DLL lock */
  1086. host->ops->set_clock(host, host->clock);
  1087. esdhc_set_strobe_dll(host);
  1088. break;
  1089. case MMC_TIMING_LEGACY:
  1090. default:
  1091. esdhc_reset_tuning(host);
  1092. break;
  1093. }
  1094. esdhc_change_pinstate(host, timing);
  1095. }
  1096. static void esdhc_reset(struct sdhci_host *host, u8 mask)
  1097. {
  1098. sdhci_reset(host, mask);
  1099. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  1100. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  1101. }
  1102. static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
  1103. {
  1104. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1105. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1106. /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
  1107. return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
  1108. }
  1109. static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
  1110. {
  1111. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1112. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1113. /* use maximum timeout counter */
  1114. esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
  1115. esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
  1116. SDHCI_TIMEOUT_CONTROL);
  1117. }
  1118. static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
  1119. {
  1120. int cmd_error = 0;
  1121. int data_error = 0;
  1122. if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
  1123. return intmask;
  1124. cqhci_irq(host->mmc, intmask, cmd_error, data_error);
  1125. return 0;
  1126. }
  1127. static struct sdhci_ops sdhci_esdhc_ops = {
  1128. .read_l = esdhc_readl_le,
  1129. .read_w = esdhc_readw_le,
  1130. .read_b = esdhc_readb_le,
  1131. .write_l = esdhc_writel_le,
  1132. .write_w = esdhc_writew_le,
  1133. .write_b = esdhc_writeb_le,
  1134. .set_clock = esdhc_pltfm_set_clock,
  1135. .get_max_clock = esdhc_pltfm_get_max_clock,
  1136. .get_min_clock = esdhc_pltfm_get_min_clock,
  1137. .get_max_timeout_count = esdhc_get_max_timeout_count,
  1138. .get_ro = esdhc_pltfm_get_ro,
  1139. .set_timeout = esdhc_set_timeout,
  1140. .set_bus_width = esdhc_pltfm_set_bus_width,
  1141. .set_uhs_signaling = esdhc_set_uhs_signaling,
  1142. .reset = esdhc_reset,
  1143. .irq = esdhc_cqhci_irq,
  1144. .dump_vendor_regs = esdhc_dump_debug_regs,
  1145. };
  1146. static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
  1147. .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
  1148. | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
  1149. | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
  1150. | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  1151. .ops = &sdhci_esdhc_ops,
  1152. };
  1153. static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
  1154. {
  1155. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1156. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1157. struct cqhci_host *cq_host = host->mmc->cqe_private;
  1158. int tmp;
  1159. if (esdhc_is_usdhc(imx_data)) {
  1160. /*
  1161. * The imx6q ROM code will change the default watermark
  1162. * level setting to something insane. Change it back here.
  1163. */
  1164. writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
  1165. /*
  1166. * ROM code will change the bit burst_length_enable setting
  1167. * to zero if this usdhc is chosen to boot system. Change
  1168. * it back here, otherwise it will impact the performance a
  1169. * lot. This bit is used to enable/disable the burst length
  1170. * for the external AHB2AXI bridge. It's useful especially
  1171. * for INCR transfer because without burst length indicator,
  1172. * the AHB2AXI bridge does not know the burst length in
  1173. * advance. And without burst length indicator, AHB INCR
  1174. * transfer can only be converted to singles on the AXI side.
  1175. */
  1176. writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
  1177. | ESDHC_BURST_LEN_EN_INCR,
  1178. host->ioaddr + SDHCI_HOST_CONTROL);
  1179. /*
  1180. * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
  1181. * TO1.1, it's harmless for MX6SL
  1182. */
  1183. writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
  1184. host->ioaddr + 0x6c);
  1185. /* disable DLL_CTRL delay line settings */
  1186. writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
  1187. /*
  1188. * For the case of command with busy, if set the bit
  1189. * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
  1190. * transfer complete interrupt when busy is deasserted.
  1191. * When CQHCI use DCMD to send a CMD need R1b respons,
  1192. * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
  1193. * otherwise DCMD will always meet timeout waiting for
  1194. * hardware interrupt issue.
  1195. */
  1196. if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
  1197. tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
  1198. tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
  1199. writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
  1200. host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
  1201. }
  1202. if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
  1203. tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
  1204. tmp |= ESDHC_STD_TUNING_EN |
  1205. ESDHC_TUNING_START_TAP_DEFAULT;
  1206. if (imx_data->boarddata.tuning_start_tap) {
  1207. tmp &= ~ESDHC_TUNING_START_TAP_MASK;
  1208. tmp |= imx_data->boarddata.tuning_start_tap;
  1209. }
  1210. if (imx_data->boarddata.tuning_step) {
  1211. tmp &= ~ESDHC_TUNING_STEP_MASK;
  1212. tmp |= imx_data->boarddata.tuning_step
  1213. << ESDHC_TUNING_STEP_SHIFT;
  1214. }
  1215. /* Disable the CMD CRC check for tuning, if not, need to
  1216. * add some delay after every tuning command, because
  1217. * hardware standard tuning logic will directly go to next
  1218. * step once it detect the CMD CRC error, will not wait for
  1219. * the card side to finally send out the tuning data, trigger
  1220. * the buffer read ready interrupt immediately. If usdhc send
  1221. * the next tuning command some eMMC card will stuck, can't
  1222. * response, block the tuning procedure or the first command
  1223. * after the whole tuning procedure always can't get any response.
  1224. */
  1225. tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
  1226. writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
  1227. } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
  1228. /*
  1229. * ESDHC_STD_TUNING_EN may be configed in bootloader
  1230. * or ROM code, so clear this bit here to make sure
  1231. * the manual tuning can work.
  1232. */
  1233. tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
  1234. tmp &= ~ESDHC_STD_TUNING_EN;
  1235. writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
  1236. }
  1237. /*
  1238. * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
  1239. * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
  1240. * the 1st linux configure power/clock for the 2nd Linux.
  1241. *
  1242. * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
  1243. * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
  1244. * After we clear the pending interrupt and halt CQCTL, issue gone.
  1245. */
  1246. if (cq_host) {
  1247. tmp = cqhci_readl(cq_host, CQHCI_IS);
  1248. cqhci_writel(cq_host, tmp, CQHCI_IS);
  1249. cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
  1250. }
  1251. }
  1252. }
  1253. static void esdhc_cqe_enable(struct mmc_host *mmc)
  1254. {
  1255. struct sdhci_host *host = mmc_priv(mmc);
  1256. struct cqhci_host *cq_host = mmc->cqe_private;
  1257. u32 reg;
  1258. u16 mode;
  1259. int count = 10;
  1260. /*
  1261. * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
  1262. * the case after tuning, so ensure the buffer is drained.
  1263. */
  1264. reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
  1265. while (reg & SDHCI_DATA_AVAILABLE) {
  1266. sdhci_readl(host, SDHCI_BUFFER);
  1267. reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
  1268. if (count-- == 0) {
  1269. dev_warn(mmc_dev(host->mmc),
  1270. "CQE may get stuck because the Buffer Read Enable bit is set\n");
  1271. break;
  1272. }
  1273. mdelay(1);
  1274. }
  1275. /*
  1276. * Runtime resume will reset the entire host controller, which
  1277. * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
  1278. * Here set DMAEN and BCEN when enable CMDQ.
  1279. */
  1280. mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
  1281. if (host->flags & SDHCI_REQ_USE_DMA)
  1282. mode |= SDHCI_TRNS_DMA;
  1283. if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
  1284. mode |= SDHCI_TRNS_BLK_CNT_EN;
  1285. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  1286. /*
  1287. * Though Runtime resume reset the entire host controller,
  1288. * but do not impact the CQHCI side, need to clear the
  1289. * HALT bit, avoid CQHCI stuck in the first request when
  1290. * system resume back.
  1291. */
  1292. cqhci_writel(cq_host, 0, CQHCI_CTL);
  1293. if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
  1294. dev_err(mmc_dev(host->mmc),
  1295. "failed to exit halt state when enable CQE\n");
  1296. sdhci_cqe_enable(mmc);
  1297. }
  1298. static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
  1299. {
  1300. sdhci_dumpregs(mmc_priv(mmc));
  1301. }
  1302. static const struct cqhci_host_ops esdhc_cqhci_ops = {
  1303. .enable = esdhc_cqe_enable,
  1304. .disable = sdhci_cqe_disable,
  1305. .dumpregs = esdhc_sdhci_dumpregs,
  1306. };
  1307. #ifdef CONFIG_OF
  1308. static int
  1309. sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
  1310. struct sdhci_host *host,
  1311. struct pltfm_imx_data *imx_data)
  1312. {
  1313. struct device_node *np = pdev->dev.of_node;
  1314. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  1315. int ret;
  1316. if (of_get_property(np, "fsl,wp-controller", NULL))
  1317. boarddata->wp_type = ESDHC_WP_CONTROLLER;
  1318. /*
  1319. * If we have this property, then activate WP check.
  1320. * Retrieveing and requesting the actual WP GPIO will happen
  1321. * in the call to mmc_of_parse().
  1322. */
  1323. if (of_property_read_bool(np, "wp-gpios"))
  1324. boarddata->wp_type = ESDHC_WP_GPIO;
  1325. of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
  1326. of_property_read_u32(np, "fsl,tuning-start-tap",
  1327. &boarddata->tuning_start_tap);
  1328. of_property_read_u32(np, "fsl,strobe-dll-delay-target",
  1329. &boarddata->strobe_dll_delay_target);
  1330. if (of_find_property(np, "no-1-8-v", NULL))
  1331. host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
  1332. if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
  1333. boarddata->delay_line = 0;
  1334. mmc_of_parse_voltage(np, &host->ocr_mask);
  1335. if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
  1336. imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
  1337. ESDHC_PINCTRL_STATE_100MHZ);
  1338. imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
  1339. ESDHC_PINCTRL_STATE_200MHZ);
  1340. }
  1341. /* call to generic mmc_of_parse to support additional capabilities */
  1342. ret = mmc_of_parse(host->mmc);
  1343. if (ret)
  1344. return ret;
  1345. if (mmc_gpio_get_cd(host->mmc) >= 0)
  1346. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  1347. return 0;
  1348. }
  1349. #else
  1350. static inline int
  1351. sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
  1352. struct sdhci_host *host,
  1353. struct pltfm_imx_data *imx_data)
  1354. {
  1355. return -ENODEV;
  1356. }
  1357. #endif
  1358. static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
  1359. struct sdhci_host *host,
  1360. struct pltfm_imx_data *imx_data)
  1361. {
  1362. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  1363. int err;
  1364. if (!host->mmc->parent->platform_data) {
  1365. dev_err(mmc_dev(host->mmc), "no board data!\n");
  1366. return -EINVAL;
  1367. }
  1368. imx_data->boarddata = *((struct esdhc_platform_data *)
  1369. host->mmc->parent->platform_data);
  1370. /* write_protect */
  1371. if (boarddata->wp_type == ESDHC_WP_GPIO) {
  1372. host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
  1373. err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
  1374. if (err) {
  1375. dev_err(mmc_dev(host->mmc),
  1376. "failed to request write-protect gpio!\n");
  1377. return err;
  1378. }
  1379. }
  1380. /* card_detect */
  1381. switch (boarddata->cd_type) {
  1382. case ESDHC_CD_GPIO:
  1383. err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
  1384. if (err) {
  1385. dev_err(mmc_dev(host->mmc),
  1386. "failed to request card-detect gpio!\n");
  1387. return err;
  1388. }
  1389. fallthrough;
  1390. case ESDHC_CD_CONTROLLER:
  1391. /* we have a working card_detect back */
  1392. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  1393. break;
  1394. case ESDHC_CD_PERMANENT:
  1395. host->mmc->caps |= MMC_CAP_NONREMOVABLE;
  1396. break;
  1397. case ESDHC_CD_NONE:
  1398. break;
  1399. }
  1400. switch (boarddata->max_bus_width) {
  1401. case 8:
  1402. host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
  1403. break;
  1404. case 4:
  1405. host->mmc->caps |= MMC_CAP_4_BIT_DATA;
  1406. break;
  1407. case 1:
  1408. default:
  1409. host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
  1410. break;
  1411. }
  1412. return 0;
  1413. }
  1414. static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
  1415. {
  1416. const struct of_device_id *of_id =
  1417. of_match_device(imx_esdhc_dt_ids, &pdev->dev);
  1418. struct sdhci_pltfm_host *pltfm_host;
  1419. struct sdhci_host *host;
  1420. struct cqhci_host *cq_host;
  1421. int err;
  1422. struct pltfm_imx_data *imx_data;
  1423. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
  1424. sizeof(*imx_data));
  1425. if (IS_ERR(host))
  1426. return PTR_ERR(host);
  1427. pltfm_host = sdhci_priv(host);
  1428. imx_data = sdhci_pltfm_priv(pltfm_host);
  1429. imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
  1430. pdev->id_entry->driver_data;
  1431. if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
  1432. cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
  1433. imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1434. if (IS_ERR(imx_data->clk_ipg)) {
  1435. err = PTR_ERR(imx_data->clk_ipg);
  1436. goto free_sdhci;
  1437. }
  1438. imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1439. if (IS_ERR(imx_data->clk_ahb)) {
  1440. err = PTR_ERR(imx_data->clk_ahb);
  1441. goto free_sdhci;
  1442. }
  1443. imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
  1444. if (IS_ERR(imx_data->clk_per)) {
  1445. err = PTR_ERR(imx_data->clk_per);
  1446. goto free_sdhci;
  1447. }
  1448. pltfm_host->clk = imx_data->clk_per;
  1449. pltfm_host->clock = clk_get_rate(pltfm_host->clk);
  1450. err = clk_prepare_enable(imx_data->clk_per);
  1451. if (err)
  1452. goto free_sdhci;
  1453. err = clk_prepare_enable(imx_data->clk_ipg);
  1454. if (err)
  1455. goto disable_per_clk;
  1456. err = clk_prepare_enable(imx_data->clk_ahb);
  1457. if (err)
  1458. goto disable_ipg_clk;
  1459. imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
  1460. if (IS_ERR(imx_data->pinctrl))
  1461. dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
  1462. if (esdhc_is_usdhc(imx_data)) {
  1463. host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
  1464. host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
  1465. /* GPIO CD can be set as a wakeup source */
  1466. host->mmc->caps |= MMC_CAP_CD_WAKE;
  1467. if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
  1468. host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
  1469. /* clear tuning bits in case ROM has set it already */
  1470. writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
  1471. writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
  1472. writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
  1473. /*
  1474. * Link usdhc specific mmc_host_ops execute_tuning function,
  1475. * to replace the standard one in sdhci_ops.
  1476. */
  1477. host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
  1478. }
  1479. if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
  1480. sdhci_esdhc_ops.platform_execute_tuning =
  1481. esdhc_executing_tuning;
  1482. if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
  1483. host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
  1484. if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
  1485. host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
  1486. if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
  1487. host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
  1488. if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
  1489. host->mmc->caps2 |= MMC_CAP2_HS400_ES;
  1490. host->mmc_host_ops.hs400_enhanced_strobe =
  1491. esdhc_hs400_enhanced_strobe;
  1492. }
  1493. if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
  1494. host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
  1495. cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
  1496. if (!cq_host) {
  1497. err = -ENOMEM;
  1498. goto disable_ahb_clk;
  1499. }
  1500. cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
  1501. cq_host->ops = &esdhc_cqhci_ops;
  1502. err = cqhci_init(cq_host, host->mmc, false);
  1503. if (err)
  1504. goto disable_ahb_clk;
  1505. }
  1506. if (of_id)
  1507. err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
  1508. else
  1509. err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
  1510. if (err)
  1511. goto disable_ahb_clk;
  1512. sdhci_esdhc_imx_hwinit(host);
  1513. err = sdhci_add_host(host);
  1514. if (err)
  1515. goto disable_ahb_clk;
  1516. pm_runtime_set_active(&pdev->dev);
  1517. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  1518. pm_runtime_use_autosuspend(&pdev->dev);
  1519. pm_suspend_ignore_children(&pdev->dev, 1);
  1520. pm_runtime_enable(&pdev->dev);
  1521. return 0;
  1522. disable_ahb_clk:
  1523. clk_disable_unprepare(imx_data->clk_ahb);
  1524. disable_ipg_clk:
  1525. clk_disable_unprepare(imx_data->clk_ipg);
  1526. disable_per_clk:
  1527. clk_disable_unprepare(imx_data->clk_per);
  1528. free_sdhci:
  1529. if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
  1530. cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
  1531. sdhci_pltfm_free(pdev);
  1532. return err;
  1533. }
  1534. static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
  1535. {
  1536. struct sdhci_host *host = platform_get_drvdata(pdev);
  1537. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1538. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1539. int dead;
  1540. pm_runtime_get_sync(&pdev->dev);
  1541. dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  1542. pm_runtime_disable(&pdev->dev);
  1543. pm_runtime_put_noidle(&pdev->dev);
  1544. sdhci_remove_host(host, dead);
  1545. clk_disable_unprepare(imx_data->clk_per);
  1546. clk_disable_unprepare(imx_data->clk_ipg);
  1547. clk_disable_unprepare(imx_data->clk_ahb);
  1548. if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
  1549. cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
  1550. sdhci_pltfm_free(pdev);
  1551. return 0;
  1552. }
  1553. #ifdef CONFIG_PM_SLEEP
  1554. static int sdhci_esdhc_suspend(struct device *dev)
  1555. {
  1556. struct sdhci_host *host = dev_get_drvdata(dev);
  1557. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1558. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1559. int ret;
  1560. if (host->mmc->caps2 & MMC_CAP2_CQE) {
  1561. ret = cqhci_suspend(host->mmc);
  1562. if (ret)
  1563. return ret;
  1564. }
  1565. if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
  1566. (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
  1567. mmc_retune_timer_stop(host->mmc);
  1568. mmc_retune_needed(host->mmc);
  1569. }
  1570. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  1571. mmc_retune_needed(host->mmc);
  1572. ret = sdhci_suspend_host(host);
  1573. if (ret)
  1574. return ret;
  1575. ret = pinctrl_pm_select_sleep_state(dev);
  1576. if (ret)
  1577. return ret;
  1578. ret = mmc_gpio_set_cd_wake(host->mmc, true);
  1579. return ret;
  1580. }
  1581. static int sdhci_esdhc_resume(struct device *dev)
  1582. {
  1583. struct sdhci_host *host = dev_get_drvdata(dev);
  1584. int ret;
  1585. ret = pinctrl_pm_select_default_state(dev);
  1586. if (ret)
  1587. return ret;
  1588. /* re-initialize hw state in case it's lost in low power mode */
  1589. sdhci_esdhc_imx_hwinit(host);
  1590. ret = sdhci_resume_host(host);
  1591. if (ret)
  1592. return ret;
  1593. if (host->mmc->caps2 & MMC_CAP2_CQE)
  1594. ret = cqhci_resume(host->mmc);
  1595. if (!ret)
  1596. ret = mmc_gpio_set_cd_wake(host->mmc, false);
  1597. return ret;
  1598. }
  1599. #endif
  1600. #ifdef CONFIG_PM
  1601. static int sdhci_esdhc_runtime_suspend(struct device *dev)
  1602. {
  1603. struct sdhci_host *host = dev_get_drvdata(dev);
  1604. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1605. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1606. int ret;
  1607. if (host->mmc->caps2 & MMC_CAP2_CQE) {
  1608. ret = cqhci_suspend(host->mmc);
  1609. if (ret)
  1610. return ret;
  1611. }
  1612. ret = sdhci_runtime_suspend_host(host);
  1613. if (ret)
  1614. return ret;
  1615. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  1616. mmc_retune_needed(host->mmc);
  1617. imx_data->actual_clock = host->mmc->actual_clock;
  1618. esdhc_pltfm_set_clock(host, 0);
  1619. clk_disable_unprepare(imx_data->clk_per);
  1620. clk_disable_unprepare(imx_data->clk_ipg);
  1621. clk_disable_unprepare(imx_data->clk_ahb);
  1622. if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
  1623. cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
  1624. return ret;
  1625. }
  1626. static int sdhci_esdhc_runtime_resume(struct device *dev)
  1627. {
  1628. struct sdhci_host *host = dev_get_drvdata(dev);
  1629. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  1630. struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
  1631. int err;
  1632. if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
  1633. cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
  1634. if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
  1635. clk_set_rate(imx_data->clk_per, pltfm_host->clock);
  1636. err = clk_prepare_enable(imx_data->clk_ahb);
  1637. if (err)
  1638. goto remove_pm_qos_request;
  1639. err = clk_prepare_enable(imx_data->clk_per);
  1640. if (err)
  1641. goto disable_ahb_clk;
  1642. err = clk_prepare_enable(imx_data->clk_ipg);
  1643. if (err)
  1644. goto disable_per_clk;
  1645. esdhc_pltfm_set_clock(host, imx_data->actual_clock);
  1646. err = sdhci_runtime_resume_host(host, 0);
  1647. if (err)
  1648. goto disable_ipg_clk;
  1649. if (host->mmc->caps2 & MMC_CAP2_CQE)
  1650. err = cqhci_resume(host->mmc);
  1651. return err;
  1652. disable_ipg_clk:
  1653. clk_disable_unprepare(imx_data->clk_ipg);
  1654. disable_per_clk:
  1655. clk_disable_unprepare(imx_data->clk_per);
  1656. disable_ahb_clk:
  1657. clk_disable_unprepare(imx_data->clk_ahb);
  1658. remove_pm_qos_request:
  1659. if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
  1660. cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
  1661. return err;
  1662. }
  1663. #endif
  1664. static const struct dev_pm_ops sdhci_esdhc_pmops = {
  1665. SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
  1666. SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
  1667. sdhci_esdhc_runtime_resume, NULL)
  1668. };
  1669. static struct platform_driver sdhci_esdhc_imx_driver = {
  1670. .driver = {
  1671. .name = "sdhci-esdhc-imx",
  1672. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1673. .of_match_table = imx_esdhc_dt_ids,
  1674. .pm = &sdhci_esdhc_pmops,
  1675. },
  1676. .id_table = imx_esdhc_devtype,
  1677. .probe = sdhci_esdhc_imx_probe,
  1678. .remove = sdhci_esdhc_imx_remove,
  1679. };
  1680. module_platform_driver(sdhci_esdhc_imx_driver);
  1681. MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
  1682. MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
  1683. MODULE_LICENSE("GPL v2");