sdhci-brcmstb.c 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
  4. *
  5. * Copyright (C) 2015 Broadcom Corporation
  6. */
  7. #include <linux/io.h>
  8. #include <linux/mmc/host.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/bitops.h>
  12. #include <linux/delay.h>
  13. #include "sdhci-pltfm.h"
  14. #include "cqhci.h"
  15. #define SDHCI_VENDOR 0x78
  16. #define SDHCI_VENDOR_ENHANCED_STRB 0x1
  17. #define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0)
  18. #define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1)
  19. #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
  20. struct sdhci_brcmstb_priv {
  21. void __iomem *cfg_regs;
  22. bool has_cqe;
  23. };
  24. struct brcmstb_match_priv {
  25. void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
  26. struct sdhci_ops *ops;
  27. unsigned int flags;
  28. };
  29. static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
  30. {
  31. struct sdhci_host *host = mmc_priv(mmc);
  32. u32 reg;
  33. dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
  34. __func__);
  35. reg = readl(host->ioaddr + SDHCI_VENDOR);
  36. if (ios->enhanced_strobe)
  37. reg |= SDHCI_VENDOR_ENHANCED_STRB;
  38. else
  39. reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
  40. writel(reg, host->ioaddr + SDHCI_VENDOR);
  41. }
  42. static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
  43. {
  44. u16 clk;
  45. host->mmc->actual_clock = 0;
  46. clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  47. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  48. if (clock == 0)
  49. return;
  50. sdhci_enable_clk(host, clk);
  51. }
  52. static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
  53. unsigned int timing)
  54. {
  55. u16 ctrl_2;
  56. dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
  57. __func__, timing);
  58. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  59. /* Select Bus Speed Mode for host */
  60. ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
  61. if ((timing == MMC_TIMING_MMC_HS200) ||
  62. (timing == MMC_TIMING_UHS_SDR104))
  63. ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
  64. else if (timing == MMC_TIMING_UHS_SDR12)
  65. ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
  66. else if (timing == MMC_TIMING_SD_HS ||
  67. timing == MMC_TIMING_MMC_HS ||
  68. timing == MMC_TIMING_UHS_SDR25)
  69. ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
  70. else if (timing == MMC_TIMING_UHS_SDR50)
  71. ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
  72. else if ((timing == MMC_TIMING_UHS_DDR50) ||
  73. (timing == MMC_TIMING_MMC_DDR52))
  74. ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
  75. else if (timing == MMC_TIMING_MMC_HS400)
  76. ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
  77. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  78. }
  79. static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
  80. {
  81. sdhci_dumpregs(mmc_priv(mmc));
  82. }
  83. static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
  84. {
  85. struct sdhci_host *host = mmc_priv(mmc);
  86. u32 reg;
  87. reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
  88. while (reg & SDHCI_DATA_AVAILABLE) {
  89. sdhci_readl(host, SDHCI_BUFFER);
  90. reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
  91. }
  92. sdhci_cqe_enable(mmc);
  93. }
  94. static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
  95. .enable = sdhci_brcmstb_cqe_enable,
  96. .disable = sdhci_cqe_disable,
  97. .dumpregs = sdhci_brcmstb_dumpregs,
  98. };
  99. static struct sdhci_ops sdhci_brcmstb_ops = {
  100. .set_clock = sdhci_set_clock,
  101. .set_bus_width = sdhci_set_bus_width,
  102. .reset = sdhci_reset,
  103. .set_uhs_signaling = sdhci_set_uhs_signaling,
  104. };
  105. static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
  106. .set_clock = sdhci_brcmstb_set_clock,
  107. .set_bus_width = sdhci_set_bus_width,
  108. .reset = sdhci_reset,
  109. .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
  110. };
  111. static struct brcmstb_match_priv match_priv_7425 = {
  112. .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT |
  113. BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT,
  114. .ops = &sdhci_brcmstb_ops,
  115. };
  116. static struct brcmstb_match_priv match_priv_7445 = {
  117. .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT,
  118. .ops = &sdhci_brcmstb_ops,
  119. };
  120. static const struct brcmstb_match_priv match_priv_7216 = {
  121. .hs400es = sdhci_brcmstb_hs400es,
  122. .ops = &sdhci_brcmstb_ops_7216,
  123. };
  124. static const struct of_device_id sdhci_brcm_of_match[] = {
  125. { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
  126. { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
  127. { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
  128. {},
  129. };
  130. static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
  131. {
  132. int cmd_error = 0;
  133. int data_error = 0;
  134. if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
  135. return intmask;
  136. cqhci_irq(host->mmc, intmask, cmd_error, data_error);
  137. return 0;
  138. }
  139. static int sdhci_brcmstb_add_host(struct sdhci_host *host,
  140. struct sdhci_brcmstb_priv *priv)
  141. {
  142. struct cqhci_host *cq_host;
  143. bool dma64;
  144. int ret;
  145. if (!priv->has_cqe)
  146. return sdhci_add_host(host);
  147. dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
  148. host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
  149. ret = sdhci_setup_host(host);
  150. if (ret)
  151. return ret;
  152. cq_host = devm_kzalloc(mmc_dev(host->mmc),
  153. sizeof(*cq_host), GFP_KERNEL);
  154. if (!cq_host) {
  155. ret = -ENOMEM;
  156. goto cleanup;
  157. }
  158. cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
  159. cq_host->ops = &sdhci_brcmstb_cqhci_ops;
  160. dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
  161. if (dma64) {
  162. dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
  163. cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  164. }
  165. ret = cqhci_init(cq_host, host->mmc, dma64);
  166. if (ret)
  167. goto cleanup;
  168. ret = __sdhci_add_host(host);
  169. if (ret)
  170. goto cleanup;
  171. return 0;
  172. cleanup:
  173. sdhci_cleanup_host(host);
  174. return ret;
  175. }
  176. static int sdhci_brcmstb_probe(struct platform_device *pdev)
  177. {
  178. const struct brcmstb_match_priv *match_priv;
  179. struct sdhci_pltfm_data brcmstb_pdata;
  180. struct sdhci_pltfm_host *pltfm_host;
  181. const struct of_device_id *match;
  182. struct sdhci_brcmstb_priv *priv;
  183. struct sdhci_host *host;
  184. struct resource *iomem;
  185. bool has_cqe = false;
  186. struct clk *clk;
  187. int res;
  188. match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
  189. match_priv = match->data;
  190. dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible);
  191. clk = devm_clk_get_optional(&pdev->dev, NULL);
  192. if (IS_ERR(clk))
  193. return dev_err_probe(&pdev->dev, PTR_ERR(clk),
  194. "Failed to get clock from Device Tree\n");
  195. res = clk_prepare_enable(clk);
  196. if (res)
  197. return res;
  198. memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
  199. if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
  200. has_cqe = true;
  201. match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
  202. }
  203. brcmstb_pdata.ops = match_priv->ops;
  204. host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
  205. sizeof(struct sdhci_brcmstb_priv));
  206. if (IS_ERR(host)) {
  207. res = PTR_ERR(host);
  208. goto err_clk;
  209. }
  210. pltfm_host = sdhci_priv(host);
  211. priv = sdhci_pltfm_priv(pltfm_host);
  212. priv->has_cqe = has_cqe;
  213. /* Map in the non-standard CFG registers */
  214. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  215. priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem);
  216. if (IS_ERR(priv->cfg_regs)) {
  217. res = PTR_ERR(priv->cfg_regs);
  218. goto err;
  219. }
  220. sdhci_get_of_property(pdev);
  221. res = mmc_of_parse(host->mmc);
  222. if (res)
  223. goto err;
  224. /*
  225. * If the chip has enhanced strobe and it's enabled, add
  226. * callback
  227. */
  228. if (match_priv->hs400es &&
  229. (host->mmc->caps2 & MMC_CAP2_HS400_ES))
  230. host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
  231. /*
  232. * Supply the existing CAPS, but clear the UHS modes. This
  233. * will allow these modes to be specified by device tree
  234. * properties through mmc_of_parse().
  235. */
  236. host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  237. if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT)
  238. host->caps &= ~SDHCI_CAN_64BIT;
  239. host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  240. host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
  241. SDHCI_SUPPORT_DDR50);
  242. host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
  243. if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT)
  244. host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
  245. res = sdhci_brcmstb_add_host(host, priv);
  246. if (res)
  247. goto err;
  248. pltfm_host->clk = clk;
  249. return res;
  250. err:
  251. sdhci_pltfm_free(pdev);
  252. err_clk:
  253. clk_disable_unprepare(clk);
  254. return res;
  255. }
  256. static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
  257. {
  258. sdhci_pltfm_suspend(&pdev->dev);
  259. }
  260. MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
  261. static struct platform_driver sdhci_brcmstb_driver = {
  262. .driver = {
  263. .name = "sdhci-brcmstb",
  264. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  265. .pm = &sdhci_pltfm_pmops,
  266. .of_match_table = of_match_ptr(sdhci_brcm_of_match),
  267. },
  268. .probe = sdhci_brcmstb_probe,
  269. .remove = sdhci_pltfm_unregister,
  270. .shutdown = sdhci_brcmstb_shutdown,
  271. };
  272. module_platform_driver(sdhci_brcmstb_driver);
  273. MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
  274. MODULE_AUTHOR("Broadcom");
  275. MODULE_LICENSE("GPL v2");