renesas_sdhi_sys_dmac.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  4. *
  5. * Copyright (C) 2016-19 Renesas Electronics Corporation
  6. * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
  7. * Copyright (C) 2017 Horms Solutions, Simon Horman
  8. * Copyright (C) 2010-2011 Guennadi Liakhovetski
  9. */
  10. #include <linux/device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/mfd/tmio.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/module.h>
  17. #include <linux/of_device.h>
  18. #include <linux/pagemap.h>
  19. #include <linux/scatterlist.h>
  20. #include <linux/sys_soc.h>
  21. #include "renesas_sdhi.h"
  22. #include "tmio_mmc.h"
  23. #define TMIO_MMC_MIN_DMA_LEN 8
  24. static const struct renesas_sdhi_of_data of_default_cfg = {
  25. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  26. };
  27. static const struct renesas_sdhi_of_data of_rz_compatible = {
  28. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
  29. TMIO_MMC_HAVE_CBSY,
  30. .tmio_ocr_mask = MMC_VDD_32_33,
  31. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  32. };
  33. static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
  34. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
  35. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  36. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  37. };
  38. /* Definitions for sampling clocks */
  39. static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
  40. {
  41. .clk_rate = 156000000,
  42. .tap = 0x00000703,
  43. },
  44. {
  45. .clk_rate = 0,
  46. .tap = 0x00000300,
  47. },
  48. };
  49. static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
  50. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  51. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  52. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  53. MMC_CAP_CMD23,
  54. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  55. .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
  56. .dma_rx_offset = 0x2000,
  57. .scc_offset = 0x0300,
  58. .taps = rcar_gen2_scc_taps,
  59. .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
  60. .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
  61. };
  62. static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
  63. { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
  64. { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
  65. { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
  66. { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
  67. { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
  68. { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
  69. { .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
  70. { .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
  71. { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
  72. { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
  73. { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
  74. { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
  75. { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
  76. { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
  77. { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
  78. { .compatible = "renesas,sdhi-shmobile" },
  79. {},
  80. };
  81. MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
  82. static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
  83. bool enable)
  84. {
  85. struct renesas_sdhi *priv = host_to_priv(host);
  86. if (!host->chan_tx || !host->chan_rx)
  87. return;
  88. if (priv->dma_priv.enable)
  89. priv->dma_priv.enable(host, enable);
  90. }
  91. static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
  92. {
  93. renesas_sdhi_sys_dmac_enable_dma(host, false);
  94. if (host->chan_rx)
  95. dmaengine_terminate_all(host->chan_rx);
  96. if (host->chan_tx)
  97. dmaengine_terminate_all(host->chan_tx);
  98. renesas_sdhi_sys_dmac_enable_dma(host, true);
  99. }
  100. static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
  101. {
  102. struct renesas_sdhi *priv = host_to_priv(host);
  103. complete(&priv->dma_priv.dma_dataend);
  104. }
  105. static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
  106. {
  107. struct tmio_mmc_host *host = arg;
  108. struct renesas_sdhi *priv = host_to_priv(host);
  109. spin_lock_irq(&host->lock);
  110. if (!host->data)
  111. goto out;
  112. if (host->data->flags & MMC_DATA_READ)
  113. dma_unmap_sg(host->chan_rx->device->dev,
  114. host->sg_ptr, host->sg_len,
  115. DMA_FROM_DEVICE);
  116. else
  117. dma_unmap_sg(host->chan_tx->device->dev,
  118. host->sg_ptr, host->sg_len,
  119. DMA_TO_DEVICE);
  120. spin_unlock_irq(&host->lock);
  121. wait_for_completion(&priv->dma_priv.dma_dataend);
  122. spin_lock_irq(&host->lock);
  123. tmio_mmc_do_data_irq(host);
  124. out:
  125. spin_unlock_irq(&host->lock);
  126. }
  127. static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
  128. {
  129. struct renesas_sdhi *priv = host_to_priv(host);
  130. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  131. struct dma_async_tx_descriptor *desc = NULL;
  132. struct dma_chan *chan = host->chan_rx;
  133. dma_cookie_t cookie;
  134. int ret, i;
  135. bool aligned = true, multiple = true;
  136. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  137. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  138. if (sg_tmp->offset & align)
  139. aligned = false;
  140. if (sg_tmp->length & align) {
  141. multiple = false;
  142. break;
  143. }
  144. }
  145. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  146. (align & PAGE_MASK))) || !multiple) {
  147. ret = -EINVAL;
  148. goto pio;
  149. }
  150. if (sg->length < TMIO_MMC_MIN_DMA_LEN)
  151. return;
  152. /* The only sg element can be unaligned, use our bounce buffer then */
  153. if (!aligned) {
  154. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  155. host->sg_ptr = &host->bounce_sg;
  156. sg = host->sg_ptr;
  157. }
  158. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
  159. if (ret > 0)
  160. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
  161. DMA_CTRL_ACK);
  162. if (desc) {
  163. reinit_completion(&priv->dma_priv.dma_dataend);
  164. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  165. desc->callback_param = host;
  166. cookie = dmaengine_submit(desc);
  167. if (cookie < 0) {
  168. desc = NULL;
  169. ret = cookie;
  170. }
  171. host->dma_on = true;
  172. }
  173. pio:
  174. if (!desc) {
  175. /* DMA failed, fall back to PIO */
  176. renesas_sdhi_sys_dmac_enable_dma(host, false);
  177. if (ret >= 0)
  178. ret = -EIO;
  179. host->chan_rx = NULL;
  180. dma_release_channel(chan);
  181. /* Free the Tx channel too */
  182. chan = host->chan_tx;
  183. if (chan) {
  184. host->chan_tx = NULL;
  185. dma_release_channel(chan);
  186. }
  187. dev_warn(&host->pdev->dev,
  188. "DMA failed: %d, falling back to PIO\n", ret);
  189. }
  190. }
  191. static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
  192. {
  193. struct renesas_sdhi *priv = host_to_priv(host);
  194. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  195. struct dma_async_tx_descriptor *desc = NULL;
  196. struct dma_chan *chan = host->chan_tx;
  197. dma_cookie_t cookie;
  198. int ret, i;
  199. bool aligned = true, multiple = true;
  200. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  201. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  202. if (sg_tmp->offset & align)
  203. aligned = false;
  204. if (sg_tmp->length & align) {
  205. multiple = false;
  206. break;
  207. }
  208. }
  209. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  210. (align & PAGE_MASK))) || !multiple) {
  211. ret = -EINVAL;
  212. goto pio;
  213. }
  214. if (sg->length < TMIO_MMC_MIN_DMA_LEN)
  215. return;
  216. /* The only sg element can be unaligned, use our bounce buffer then */
  217. if (!aligned) {
  218. unsigned long flags;
  219. void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
  220. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  221. memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
  222. tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
  223. host->sg_ptr = &host->bounce_sg;
  224. sg = host->sg_ptr;
  225. }
  226. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
  227. if (ret > 0)
  228. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
  229. DMA_CTRL_ACK);
  230. if (desc) {
  231. reinit_completion(&priv->dma_priv.dma_dataend);
  232. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  233. desc->callback_param = host;
  234. cookie = dmaengine_submit(desc);
  235. if (cookie < 0) {
  236. desc = NULL;
  237. ret = cookie;
  238. }
  239. host->dma_on = true;
  240. }
  241. pio:
  242. if (!desc) {
  243. /* DMA failed, fall back to PIO */
  244. renesas_sdhi_sys_dmac_enable_dma(host, false);
  245. if (ret >= 0)
  246. ret = -EIO;
  247. host->chan_tx = NULL;
  248. dma_release_channel(chan);
  249. /* Free the Rx channel too */
  250. chan = host->chan_rx;
  251. if (chan) {
  252. host->chan_rx = NULL;
  253. dma_release_channel(chan);
  254. }
  255. dev_warn(&host->pdev->dev,
  256. "DMA failed: %d, falling back to PIO\n", ret);
  257. }
  258. }
  259. static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
  260. struct mmc_data *data)
  261. {
  262. if (data->flags & MMC_DATA_READ) {
  263. if (host->chan_rx)
  264. renesas_sdhi_sys_dmac_start_dma_rx(host);
  265. } else {
  266. if (host->chan_tx)
  267. renesas_sdhi_sys_dmac_start_dma_tx(host);
  268. }
  269. }
  270. static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
  271. {
  272. struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
  273. struct dma_chan *chan = NULL;
  274. spin_lock_irq(&host->lock);
  275. if (host->data) {
  276. if (host->data->flags & MMC_DATA_READ)
  277. chan = host->chan_rx;
  278. else
  279. chan = host->chan_tx;
  280. }
  281. spin_unlock_irq(&host->lock);
  282. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  283. if (chan)
  284. dma_async_issue_pending(chan);
  285. }
  286. static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
  287. struct tmio_mmc_data *pdata)
  288. {
  289. struct renesas_sdhi *priv = host_to_priv(host);
  290. /* We can only either use DMA for both Tx and Rx or not use it at all */
  291. if (!host->pdev->dev.of_node &&
  292. (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
  293. return;
  294. if (!host->chan_tx && !host->chan_rx) {
  295. struct resource *res = platform_get_resource(host->pdev,
  296. IORESOURCE_MEM, 0);
  297. struct dma_slave_config cfg = {};
  298. dma_cap_mask_t mask;
  299. int ret;
  300. if (!res)
  301. return;
  302. dma_cap_zero(mask);
  303. dma_cap_set(DMA_SLAVE, mask);
  304. host->chan_tx = dma_request_slave_channel_compat(mask,
  305. priv->dma_priv.filter, pdata->chan_priv_tx,
  306. &host->pdev->dev, "tx");
  307. dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
  308. host->chan_tx);
  309. if (!host->chan_tx)
  310. return;
  311. cfg.direction = DMA_MEM_TO_DEV;
  312. cfg.dst_addr = res->start +
  313. (CTL_SD_DATA_PORT << host->bus_shift);
  314. cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
  315. if (!cfg.dst_addr_width)
  316. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  317. cfg.src_addr = 0;
  318. ret = dmaengine_slave_config(host->chan_tx, &cfg);
  319. if (ret < 0)
  320. goto ecfgtx;
  321. host->chan_rx = dma_request_slave_channel_compat(mask,
  322. priv->dma_priv.filter, pdata->chan_priv_rx,
  323. &host->pdev->dev, "rx");
  324. dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
  325. host->chan_rx);
  326. if (!host->chan_rx)
  327. goto ereqrx;
  328. cfg.direction = DMA_DEV_TO_MEM;
  329. cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
  330. cfg.src_addr_width = priv->dma_priv.dma_buswidth;
  331. if (!cfg.src_addr_width)
  332. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  333. cfg.dst_addr = 0;
  334. ret = dmaengine_slave_config(host->chan_rx, &cfg);
  335. if (ret < 0)
  336. goto ecfgrx;
  337. host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
  338. if (!host->bounce_buf)
  339. goto ebouncebuf;
  340. init_completion(&priv->dma_priv.dma_dataend);
  341. tasklet_init(&host->dma_issue,
  342. renesas_sdhi_sys_dmac_issue_tasklet_fn,
  343. (unsigned long)host);
  344. }
  345. renesas_sdhi_sys_dmac_enable_dma(host, true);
  346. return;
  347. ebouncebuf:
  348. ecfgrx:
  349. dma_release_channel(host->chan_rx);
  350. host->chan_rx = NULL;
  351. ereqrx:
  352. ecfgtx:
  353. dma_release_channel(host->chan_tx);
  354. host->chan_tx = NULL;
  355. }
  356. static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
  357. {
  358. if (host->chan_tx) {
  359. struct dma_chan *chan = host->chan_tx;
  360. host->chan_tx = NULL;
  361. dma_release_channel(chan);
  362. }
  363. if (host->chan_rx) {
  364. struct dma_chan *chan = host->chan_rx;
  365. host->chan_rx = NULL;
  366. dma_release_channel(chan);
  367. }
  368. if (host->bounce_buf) {
  369. free_pages((unsigned long)host->bounce_buf, 0);
  370. host->bounce_buf = NULL;
  371. }
  372. }
  373. static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
  374. .start = renesas_sdhi_sys_dmac_start_dma,
  375. .enable = renesas_sdhi_sys_dmac_enable_dma,
  376. .request = renesas_sdhi_sys_dmac_request_dma,
  377. .release = renesas_sdhi_sys_dmac_release_dma,
  378. .abort = renesas_sdhi_sys_dmac_abort_dma,
  379. .dataend = renesas_sdhi_sys_dmac_dataend_dma,
  380. };
  381. static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
  382. {
  383. return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
  384. }
  385. static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
  386. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  387. pm_runtime_force_resume)
  388. SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
  389. tmio_mmc_host_runtime_resume,
  390. NULL)
  391. };
  392. static struct platform_driver renesas_sys_dmac_sdhi_driver = {
  393. .driver = {
  394. .name = "sh_mobile_sdhi",
  395. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  396. .pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
  397. .of_match_table = renesas_sdhi_sys_dmac_of_match,
  398. },
  399. .probe = renesas_sdhi_sys_dmac_probe,
  400. .remove = renesas_sdhi_remove,
  401. };
  402. module_platform_driver(renesas_sys_dmac_sdhi_driver);
  403. MODULE_DESCRIPTION("Renesas SDHI driver");
  404. MODULE_AUTHOR("Magnus Damm");
  405. MODULE_LICENSE("GPL v2");
  406. MODULE_ALIAS("platform:sh_mobile_sdhi");