renesas_sdhi_internal_dmac.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * DMA support for Internal DMAC with SDHI SD/SDIO controller
  4. *
  5. * Copyright (C) 2016-19 Renesas Electronics Corporation
  6. * Copyright (C) 2016-17 Horms Solutions, Simon Horman
  7. * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/io-64-nonatomic-hi-lo.h>
  13. #include <linux/mfd/tmio.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/module.h>
  17. #include <linux/pagemap.h>
  18. #include <linux/scatterlist.h>
  19. #include <linux/sys_soc.h>
  20. #include "renesas_sdhi.h"
  21. #include "tmio_mmc.h"
  22. #define DM_CM_DTRAN_MODE 0x820
  23. #define DM_CM_DTRAN_CTRL 0x828
  24. #define DM_CM_RST 0x830
  25. #define DM_CM_INFO1 0x840
  26. #define DM_CM_INFO1_MASK 0x848
  27. #define DM_CM_INFO2 0x850
  28. #define DM_CM_INFO2_MASK 0x858
  29. #define DM_DTRAN_ADDR 0x880
  30. /* DM_CM_DTRAN_MODE */
  31. #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
  32. #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
  33. #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
  34. #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
  35. /* DM_CM_DTRAN_CTRL */
  36. #define DTRAN_CTRL_DM_START BIT(0)
  37. /* DM_CM_RST */
  38. #define RST_DTRANRST1 BIT(9)
  39. #define RST_DTRANRST0 BIT(8)
  40. #define RST_RESERVED_BITS GENMASK_ULL(31, 0)
  41. /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
  42. #define INFO1_CLEAR 0
  43. #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
  44. #define INFO1_DTRANEND1 BIT(17)
  45. #define INFO1_DTRANEND0 BIT(16)
  46. /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
  47. #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0)
  48. #define INFO2_DTRANERR1 BIT(17)
  49. #define INFO2_DTRANERR0 BIT(16)
  50. /*
  51. * Specification of this driver:
  52. * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
  53. * - Since this SDHI DMAC register set has 16 but 32-bit width, we
  54. * need a custom accessor.
  55. */
  56. static unsigned long global_flags;
  57. /*
  58. * Workaround for avoiding to use RX DMAC by multiple channels.
  59. * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
  60. * RX DMAC simultaneously, sometimes hundreds of bytes data are not
  61. * stored into the system memory even if the DMAC interrupt happened.
  62. * So, this driver then uses one RX DMAC channel only.
  63. */
  64. #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0
  65. #define SDHI_INTERNAL_DMAC_RX_IN_USE 1
  66. /* RZ/A2 does not have the ADRR_MODE bit */
  67. #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
  68. /* Definitions for sampling clocks */
  69. static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  70. {
  71. .clk_rate = 0,
  72. .tap = 0x00000300,
  73. .tap_hs400_4tap = 0x00000100,
  74. },
  75. };
  76. static const struct renesas_sdhi_of_data of_rza2_compatible = {
  77. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  78. TMIO_MMC_HAVE_CBSY,
  79. .tmio_ocr_mask = MMC_VDD_32_33,
  80. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  81. MMC_CAP_CMD23,
  82. .bus_shift = 2,
  83. .scc_offset = 0 - 0x1000,
  84. .taps = rcar_gen3_scc_taps,
  85. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  86. /* DMAC can handle 32bit blk count but only 1 segment */
  87. .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
  88. .max_segs = 1,
  89. };
  90. static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  91. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  92. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  93. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  94. MMC_CAP_CMD23,
  95. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
  96. .bus_shift = 2,
  97. .scc_offset = 0x1000,
  98. .taps = rcar_gen3_scc_taps,
  99. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  100. /* DMAC can handle 32bit blk count but only 1 segment */
  101. .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
  102. .max_segs = 1,
  103. };
  104. static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
  105. { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
  106. { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
  107. { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
  108. { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
  109. { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
  110. {},
  111. };
  112. MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
  113. static void
  114. renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
  115. int addr, u64 val)
  116. {
  117. writeq(val, host->ctl + addr);
  118. }
  119. static void
  120. renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
  121. {
  122. struct renesas_sdhi *priv = host_to_priv(host);
  123. if (!host->chan_tx || !host->chan_rx)
  124. return;
  125. if (!enable)
  126. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
  127. INFO1_CLEAR);
  128. if (priv->dma_priv.enable)
  129. priv->dma_priv.enable(host, enable);
  130. }
  131. static void
  132. renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
  133. u64 val = RST_DTRANRST1 | RST_DTRANRST0;
  134. renesas_sdhi_internal_dmac_enable_dma(host, false);
  135. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
  136. RST_RESERVED_BITS & ~val);
  137. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
  138. RST_RESERVED_BITS | val);
  139. clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
  140. renesas_sdhi_internal_dmac_enable_dma(host, true);
  141. }
  142. static void
  143. renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
  144. struct renesas_sdhi *priv = host_to_priv(host);
  145. tasklet_schedule(&priv->dma_priv.dma_complete);
  146. }
  147. static void
  148. renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
  149. struct mmc_data *data)
  150. {
  151. struct scatterlist *sg = host->sg_ptr;
  152. u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
  153. if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags))
  154. dtran_mode |= DTRAN_MODE_ADDR_MODE;
  155. if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
  156. mmc_get_dma_dir(data)))
  157. goto force_pio;
  158. /* This DMAC cannot handle if buffer is not 128-bytes alignment */
  159. if (!IS_ALIGNED(sg_dma_address(sg), 128))
  160. goto force_pio_with_unmap;
  161. if (data->flags & MMC_DATA_READ) {
  162. dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
  163. if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
  164. test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
  165. goto force_pio_with_unmap;
  166. } else {
  167. dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
  168. }
  169. renesas_sdhi_internal_dmac_enable_dma(host, true);
  170. /* set dma parameters */
  171. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
  172. dtran_mode);
  173. renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
  174. sg_dma_address(sg));
  175. host->dma_on = true;
  176. return;
  177. force_pio_with_unmap:
  178. dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
  179. force_pio:
  180. renesas_sdhi_internal_dmac_enable_dma(host, false);
  181. }
  182. static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
  183. {
  184. struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
  185. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  186. /* start the DMAC */
  187. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
  188. DTRAN_CTRL_DM_START);
  189. }
  190. static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
  191. {
  192. enum dma_data_direction dir;
  193. if (!host->dma_on)
  194. return false;
  195. if (!host->data)
  196. return false;
  197. if (host->data->flags & MMC_DATA_READ)
  198. dir = DMA_FROM_DEVICE;
  199. else
  200. dir = DMA_TO_DEVICE;
  201. renesas_sdhi_internal_dmac_enable_dma(host, false);
  202. dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
  203. if (dir == DMA_FROM_DEVICE)
  204. clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
  205. host->dma_on = false;
  206. return true;
  207. }
  208. static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
  209. {
  210. struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
  211. spin_lock_irq(&host->lock);
  212. if (!renesas_sdhi_internal_dmac_complete(host))
  213. goto out;
  214. tmio_mmc_do_data_irq(host);
  215. out:
  216. spin_unlock_irq(&host->lock);
  217. }
  218. static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
  219. {
  220. if (host->data)
  221. renesas_sdhi_internal_dmac_complete(host);
  222. }
  223. static void
  224. renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
  225. struct tmio_mmc_data *pdata)
  226. {
  227. struct renesas_sdhi *priv = host_to_priv(host);
  228. /* Disable DMAC interrupts, we don't use them */
  229. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
  230. INFO1_MASK_CLEAR);
  231. renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
  232. INFO2_MASK_CLEAR);
  233. /* Each value is set to non-zero to assume "enabling" each DMA */
  234. host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
  235. tasklet_init(&priv->dma_priv.dma_complete,
  236. renesas_sdhi_internal_dmac_complete_tasklet_fn,
  237. (unsigned long)host);
  238. tasklet_init(&host->dma_issue,
  239. renesas_sdhi_internal_dmac_issue_tasklet_fn,
  240. (unsigned long)host);
  241. }
  242. static void
  243. renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
  244. {
  245. /* Each value is set to zero to assume "disabling" each DMA */
  246. host->chan_rx = host->chan_tx = NULL;
  247. }
  248. static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
  249. .start = renesas_sdhi_internal_dmac_start_dma,
  250. .enable = renesas_sdhi_internal_dmac_enable_dma,
  251. .request = renesas_sdhi_internal_dmac_request_dma,
  252. .release = renesas_sdhi_internal_dmac_release_dma,
  253. .abort = renesas_sdhi_internal_dmac_abort_dma,
  254. .dataend = renesas_sdhi_internal_dmac_dataend_dma,
  255. .end = renesas_sdhi_internal_dmac_end_dma,
  256. };
  257. /*
  258. * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
  259. * implementation as others may use a different implementation.
  260. */
  261. static const struct soc_device_attribute soc_dma_quirks[] = {
  262. { .soc_id = "r7s9210",
  263. .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
  264. { .soc_id = "r8a7795", .revision = "ES1.*",
  265. .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
  266. { .soc_id = "r8a7796", .revision = "ES1.0",
  267. .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
  268. { /* sentinel */ }
  269. };
  270. static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
  271. {
  272. const struct soc_device_attribute *soc = soc_device_match(soc_dma_quirks);
  273. struct device *dev = &pdev->dev;
  274. if (soc)
  275. global_flags |= (unsigned long)soc->data;
  276. /* value is max of SD_SECCNT. Confirmed by HW engineers */
  277. dma_set_max_seg_size(dev, 0xffffffff);
  278. return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
  279. }
  280. static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
  281. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  282. pm_runtime_force_resume)
  283. SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
  284. tmio_mmc_host_runtime_resume,
  285. NULL)
  286. };
  287. static struct platform_driver renesas_internal_dmac_sdhi_driver = {
  288. .driver = {
  289. .name = "renesas_sdhi_internal_dmac",
  290. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  291. .pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
  292. .of_match_table = renesas_sdhi_internal_dmac_of_match,
  293. },
  294. .probe = renesas_sdhi_internal_dmac_probe,
  295. .remove = renesas_sdhi_remove,
  296. };
  297. module_platform_driver(renesas_internal_dmac_sdhi_driver);
  298. MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
  299. MODULE_AUTHOR("Yoshihiro Shimoda");
  300. MODULE_LICENSE("GPL v2");