renesas_sdhi_core.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas SDHI
  4. *
  5. * Copyright (C) 2015-19 Renesas Electronics Corporation
  6. * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
  7. * Copyright (C) 2016-17 Horms Solutions, Simon Horman
  8. * Copyright (C) 2009 Magnus Damm
  9. *
  10. * Based on "Compaq ASIC3 support":
  11. *
  12. * Copyright 2001 Compaq Computer Corporation.
  13. * Copyright 2004-2005 Phil Blundell
  14. * Copyright 2007-2008 OpenedHand Ltd.
  15. *
  16. * Authors: Phil Blundell <pb@handhelds.org>,
  17. * Samuel Ortiz <sameo@openedhand.com>
  18. *
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/clk.h>
  22. #include <linux/slab.h>
  23. #include <linux/module.h>
  24. #include <linux/of_device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pm_domain.h>
  27. #include <linux/mmc/host.h>
  28. #include <linux/mmc/mmc.h>
  29. #include <linux/mmc/slot-gpio.h>
  30. #include <linux/mfd/tmio.h>
  31. #include <linux/sh_dma.h>
  32. #include <linux/delay.h>
  33. #include <linux/pinctrl/consumer.h>
  34. #include <linux/pinctrl/pinctrl-state.h>
  35. #include <linux/regulator/consumer.h>
  36. #include <linux/sys_soc.h>
  37. #include "renesas_sdhi.h"
  38. #include "tmio_mmc.h"
  39. #define HOST_MODE 0xe4
  40. #define SDHI_VER_GEN2_SDR50 0x490c
  41. #define SDHI_VER_RZ_A1 0x820b
  42. /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  43. #define SDHI_VER_GEN2_SDR104 0xcb0d
  44. #define SDHI_VER_GEN3_SD 0xcc10
  45. #define SDHI_VER_GEN3_SDMMC 0xcd10
  46. #define SDHI_GEN3_MMC0_ADDR 0xee140000
  47. static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  48. {
  49. u32 val;
  50. /*
  51. * see also
  52. * renesas_sdhi_of_data :: dma_buswidth
  53. */
  54. switch (sd_ctrl_read16(host, CTL_VERSION)) {
  55. case SDHI_VER_GEN2_SDR50:
  56. val = (width == 32) ? 0x0001 : 0x0000;
  57. break;
  58. case SDHI_VER_GEN2_SDR104:
  59. val = (width == 32) ? 0x0000 : 0x0001;
  60. break;
  61. case SDHI_VER_GEN3_SD:
  62. case SDHI_VER_GEN3_SDMMC:
  63. if (width == 64)
  64. val = 0x0000;
  65. else if (width == 32)
  66. val = 0x0101;
  67. else
  68. val = 0x0001;
  69. break;
  70. default:
  71. /* nothing to do */
  72. return;
  73. }
  74. sd_ctrl_write16(host, HOST_MODE, val);
  75. }
  76. static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  77. {
  78. struct mmc_host *mmc = host->mmc;
  79. struct renesas_sdhi *priv = host_to_priv(host);
  80. int ret;
  81. ret = clk_prepare_enable(priv->clk_cd);
  82. if (ret < 0)
  83. return ret;
  84. /*
  85. * The clock driver may not know what maximum frequency
  86. * actually works, so it should be set with the max-frequency
  87. * property which will already have been read to f_max. If it
  88. * was missing, assume the current frequency is the maximum.
  89. */
  90. if (!mmc->f_max)
  91. mmc->f_max = clk_get_rate(priv->clk);
  92. /*
  93. * Minimum frequency is the minimum input clock frequency
  94. * divided by our maximum divider.
  95. */
  96. mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
  97. /* enable 16bit data access on SDBUF as default */
  98. renesas_sdhi_sdbuf_width(host, 16);
  99. return 0;
  100. }
  101. static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
  102. unsigned int new_clock)
  103. {
  104. struct renesas_sdhi *priv = host_to_priv(host);
  105. unsigned int freq, diff, best_freq = 0, diff_min = ~0;
  106. int i;
  107. /*
  108. * We simply return the current rate if a) we are not on a R-Car Gen2+
  109. * SoC (may work for others, but untested) or b) if the SCC needs its
  110. * clock during tuning, so we don't change the external clock setup.
  111. */
  112. if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
  113. return clk_get_rate(priv->clk);
  114. /*
  115. * We want the bus clock to be as close as possible to, but no
  116. * greater than, new_clock. As we can divide by 1 << i for
  117. * any i in [0, 9] we want the input clock to be as close as
  118. * possible, but no greater than, new_clock << i.
  119. */
  120. for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
  121. freq = clk_round_rate(priv->clk, new_clock << i);
  122. if (freq > (new_clock << i)) {
  123. /* Too fast; look for a slightly slower option */
  124. freq = clk_round_rate(priv->clk,
  125. (new_clock << i) / 4 * 3);
  126. if (freq > (new_clock << i))
  127. continue;
  128. }
  129. diff = new_clock - (freq >> i);
  130. if (diff <= diff_min) {
  131. best_freq = freq;
  132. diff_min = diff;
  133. }
  134. }
  135. clk_set_rate(priv->clk, best_freq);
  136. return clk_get_rate(priv->clk);
  137. }
  138. static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
  139. unsigned int new_clock)
  140. {
  141. u32 clk = 0, clock;
  142. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  143. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  144. if (new_clock == 0) {
  145. host->mmc->actual_clock = 0;
  146. goto out;
  147. }
  148. host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
  149. clock = host->mmc->actual_clock / 512;
  150. for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
  151. clock <<= 1;
  152. /* 1/1 clock is option */
  153. if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
  154. if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
  155. clk |= 0xff;
  156. else
  157. clk &= ~0xff;
  158. }
  159. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
  160. if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
  161. usleep_range(10000, 11000);
  162. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  163. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  164. out:
  165. /* HW engineers overrode docs: no sleep needed on R-Car2+ */
  166. if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
  167. usleep_range(10000, 11000);
  168. }
  169. static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
  170. {
  171. struct renesas_sdhi *priv = host_to_priv(host);
  172. clk_disable_unprepare(priv->clk_cd);
  173. }
  174. static int renesas_sdhi_card_busy(struct mmc_host *mmc)
  175. {
  176. struct tmio_mmc_host *host = mmc_priv(mmc);
  177. return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
  178. TMIO_STAT_DAT0);
  179. }
  180. static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
  181. struct mmc_ios *ios)
  182. {
  183. struct tmio_mmc_host *host = mmc_priv(mmc);
  184. struct renesas_sdhi *priv = host_to_priv(host);
  185. struct pinctrl_state *pin_state;
  186. int ret;
  187. switch (ios->signal_voltage) {
  188. case MMC_SIGNAL_VOLTAGE_330:
  189. pin_state = priv->pins_default;
  190. break;
  191. case MMC_SIGNAL_VOLTAGE_180:
  192. pin_state = priv->pins_uhs;
  193. break;
  194. default:
  195. return -EINVAL;
  196. }
  197. /*
  198. * If anything is missing, assume signal voltage is fixed at
  199. * 3.3V and succeed/fail accordingly.
  200. */
  201. if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
  202. return ios->signal_voltage ==
  203. MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
  204. ret = mmc_regulator_set_vqmmc(host->mmc, ios);
  205. if (ret < 0)
  206. return ret;
  207. return pinctrl_select_state(priv->pinctrl, pin_state);
  208. }
  209. /* SCC registers */
  210. #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
  211. #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
  212. #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
  213. #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
  214. #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
  215. #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
  216. #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
  217. #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
  218. #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
  219. #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
  220. #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
  221. #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
  222. #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
  223. #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
  224. #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
  225. #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
  226. #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
  227. #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
  228. #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
  229. #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
  230. #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
  231. #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
  232. #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
  233. #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
  234. #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
  235. #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
  236. /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
  237. #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  238. /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
  239. #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
  240. #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
  241. #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
  242. /* Definitions for values the SH_MOBILE_SDHI_SCC register */
  243. #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
  244. #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
  245. #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
  246. static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
  247. { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
  248. 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
  249. { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
  250. 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
  251. };
  252. static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
  253. { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
  254. 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
  255. { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
  256. 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
  257. };
  258. static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
  259. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  260. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  261. { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
  262. 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
  263. };
  264. static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
  265. struct renesas_sdhi *priv, int addr)
  266. {
  267. return readl(priv->scc_ctl + (addr << host->bus_shift));
  268. }
  269. static inline void sd_scc_write32(struct tmio_mmc_host *host,
  270. struct renesas_sdhi *priv,
  271. int addr, u32 val)
  272. {
  273. writel(val, priv->scc_ctl + (addr << host->bus_shift));
  274. }
  275. static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
  276. {
  277. struct renesas_sdhi *priv;
  278. priv = host_to_priv(host);
  279. /* Initialize SCC */
  280. sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
  281. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  282. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  283. /* set sampling clock selection range */
  284. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
  285. SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
  286. 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
  287. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
  288. SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
  289. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
  290. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  291. ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
  292. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  293. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
  294. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  295. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  296. /* Read TAPNUM */
  297. return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
  298. SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  299. SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  300. }
  301. static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
  302. {
  303. struct tmio_mmc_host *host = mmc_priv(mmc);
  304. struct renesas_sdhi *priv = host_to_priv(host);
  305. u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
  306. bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
  307. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  308. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  309. /* Set HS400 mode */
  310. sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
  311. sd_ctrl_read16(host, CTL_SDIF_MODE));
  312. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
  313. priv->scc_tappos_hs400);
  314. /* Gen3 can't do automatic tap correction with HS400, so disable it */
  315. if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
  316. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  317. ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
  318. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  319. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
  320. (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
  321. SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
  322. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
  323. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
  324. SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
  325. sd_scc_read32(host, priv,
  326. SH_MOBILE_SDHI_SCC_DTCNTL));
  327. /* Avoid bad TAP */
  328. if (bad_taps & BIT(priv->tap_set)) {
  329. u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
  330. if (bad_taps & BIT(new_tap))
  331. new_tap = (priv->tap_set - 1) % priv->tap_num;
  332. if (bad_taps & BIT(new_tap)) {
  333. new_tap = priv->tap_set;
  334. dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
  335. }
  336. priv->tap_set = new_tap;
  337. }
  338. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
  339. priv->tap_set / (use_4tap ? 2 : 1));
  340. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
  341. SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
  342. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
  343. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  344. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  345. if (priv->adjust_hs400_calib_table)
  346. priv->needs_adjust_hs400 = true;
  347. }
  348. static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
  349. struct renesas_sdhi *priv)
  350. {
  351. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  352. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  353. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
  354. ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
  355. sd_scc_read32(host, priv,
  356. SH_MOBILE_SDHI_SCC_CKSEL));
  357. }
  358. static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
  359. {
  360. struct tmio_mmc_host *host = mmc_priv(mmc);
  361. struct renesas_sdhi *priv = host_to_priv(host);
  362. renesas_sdhi_reset_scc(host, priv);
  363. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
  364. ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
  365. sd_scc_read32(host, priv,
  366. SH_MOBILE_SDHI_SCC_DTCNTL));
  367. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  368. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  369. }
  370. static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
  371. struct renesas_sdhi *priv, u32 addr)
  372. {
  373. /* read mode */
  374. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
  375. SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  376. (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
  377. /* access start and stop */
  378. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
  379. SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
  380. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
  381. return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
  382. }
  383. static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
  384. struct renesas_sdhi *priv, u32 addr, u32 val)
  385. {
  386. /* write mode */
  387. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
  388. SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  389. (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
  390. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
  391. /* access start and stop */
  392. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
  393. SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
  394. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
  395. }
  396. static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
  397. {
  398. struct renesas_sdhi *priv = host_to_priv(host);
  399. u32 calib_code;
  400. /* disable write protect */
  401. sd_scc_tmpport_write32(host, priv, 0x00,
  402. SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
  403. /* read calibration code and adjust */
  404. calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
  405. calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
  406. sd_scc_tmpport_write32(host, priv, 0x22,
  407. SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
  408. priv->adjust_hs400_calib_table[calib_code]);
  409. /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
  410. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
  411. /* adjustment done, clear flag */
  412. priv->needs_adjust_hs400 = false;
  413. }
  414. static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
  415. {
  416. struct renesas_sdhi *priv = host_to_priv(host);
  417. /* disable write protect */
  418. sd_scc_tmpport_write32(host, priv, 0x00,
  419. SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
  420. /* disable manual calibration */
  421. sd_scc_tmpport_write32(host, priv, 0x22, 0);
  422. /* clear offset value of TMPPORT3 */
  423. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
  424. }
  425. static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
  426. struct renesas_sdhi *priv)
  427. {
  428. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
  429. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  430. /* Reset HS400 mode */
  431. sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
  432. sd_ctrl_read16(host, CTL_SDIF_MODE));
  433. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
  434. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
  435. ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
  436. SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
  437. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
  438. if (priv->adjust_hs400_calib_table)
  439. renesas_sdhi_adjust_hs400_mode_disable(host);
  440. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  441. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  442. }
  443. static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
  444. {
  445. struct tmio_mmc_host *host = mmc_priv(mmc);
  446. renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
  447. return 0;
  448. }
  449. static void renesas_sdhi_reset(struct tmio_mmc_host *host)
  450. {
  451. struct renesas_sdhi *priv = host_to_priv(host);
  452. renesas_sdhi_reset_scc(host, priv);
  453. renesas_sdhi_reset_hs400_mode(host, priv);
  454. priv->needs_adjust_hs400 = false;
  455. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
  456. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  457. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  458. ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
  459. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  460. if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
  461. sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
  462. TMIO_MASK_INIT_RCAR2);
  463. }
  464. #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
  465. static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
  466. {
  467. struct renesas_sdhi *priv = host_to_priv(host);
  468. unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
  469. unsigned int taps_size = priv->tap_num * 2, min_tap_row;
  470. unsigned long *bitmap;
  471. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
  472. /*
  473. * When tuning CMD19 is issued twice for each tap, merge the
  474. * result requiring the tap to be good in both runs before
  475. * considering it for tuning selection.
  476. */
  477. for (i = 0; i < taps_size; i++) {
  478. int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
  479. if (!test_bit(i, priv->taps))
  480. clear_bit(i + offset, priv->taps);
  481. if (!test_bit(i, priv->smpcmp))
  482. clear_bit(i + offset, priv->smpcmp);
  483. }
  484. /*
  485. * If all TAP are OK, the sampling clock position is selected by
  486. * identifying the change point of data.
  487. */
  488. if (bitmap_full(priv->taps, taps_size)) {
  489. bitmap = priv->smpcmp;
  490. min_tap_row = 1;
  491. } else {
  492. bitmap = priv->taps;
  493. min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
  494. }
  495. /*
  496. * Find the longest consecutive run of successful probes. If that
  497. * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
  498. * center index as the tap, otherwise bail out.
  499. */
  500. bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
  501. if (re - rs > tap_cnt) {
  502. tap_end = re;
  503. tap_start = rs;
  504. tap_cnt = tap_end - tap_start;
  505. }
  506. }
  507. if (tap_cnt >= min_tap_row)
  508. priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
  509. else
  510. return -EIO;
  511. /* Set SCC */
  512. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
  513. /* Enable auto re-tuning */
  514. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
  515. SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
  516. sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
  517. return 0;
  518. }
  519. static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
  520. {
  521. struct tmio_mmc_host *host = mmc_priv(mmc);
  522. struct renesas_sdhi *priv = host_to_priv(host);
  523. int i, ret;
  524. priv->tap_num = renesas_sdhi_init_tuning(host);
  525. if (!priv->tap_num)
  526. return 0; /* Tuning is not supported */
  527. if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
  528. dev_err(&host->pdev->dev,
  529. "Too many taps, please update 'taps' in tmio_mmc_host!\n");
  530. return -EINVAL;
  531. }
  532. bitmap_zero(priv->taps, priv->tap_num * 2);
  533. bitmap_zero(priv->smpcmp, priv->tap_num * 2);
  534. /* Issue CMD19 twice for each tap */
  535. for (i = 0; i < 2 * priv->tap_num; i++) {
  536. int cmd_error = 0;
  537. /* Set sampling clock position */
  538. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
  539. if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
  540. set_bit(i, priv->taps);
  541. if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
  542. set_bit(i, priv->smpcmp);
  543. if (cmd_error)
  544. mmc_abort_tuning(mmc, opcode);
  545. }
  546. ret = renesas_sdhi_select_tuning(host);
  547. if (ret < 0)
  548. renesas_sdhi_reset(host);
  549. return ret;
  550. }
  551. static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
  552. {
  553. struct renesas_sdhi *priv = host_to_priv(host);
  554. unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
  555. u32 val;
  556. val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
  557. if (!val)
  558. return false;
  559. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
  560. /* Change TAP position according to correction status */
  561. if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
  562. host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
  563. u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
  564. /*
  565. * With HS400, the DAT signal is based on DS, not CLK.
  566. * Therefore, use only CMD status.
  567. */
  568. u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
  569. SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
  570. if (!smpcmp) {
  571. return false; /* no error in CMD signal */
  572. } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
  573. new_tap++;
  574. error_tap--;
  575. } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
  576. new_tap--;
  577. error_tap++;
  578. } else {
  579. return true; /* need retune */
  580. }
  581. /*
  582. * When new_tap is a bad tap, we cannot change. Then, we compare
  583. * with the HS200 tuning result. When smpcmp[error_tap] is OK,
  584. * we can at least retune.
  585. */
  586. if (bad_taps & BIT(new_tap % priv->tap_num))
  587. return test_bit(error_tap % priv->tap_num, priv->smpcmp);
  588. } else {
  589. if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
  590. return true; /* need retune */
  591. else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
  592. new_tap++;
  593. else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
  594. new_tap--;
  595. else
  596. return false;
  597. }
  598. priv->tap_set = (new_tap % priv->tap_num);
  599. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
  600. priv->tap_set / (use_4tap ? 2 : 1));
  601. return false;
  602. }
  603. static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
  604. {
  605. struct renesas_sdhi *priv = host_to_priv(host);
  606. /* Check SCC error */
  607. if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
  608. SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
  609. sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
  610. return true;
  611. }
  612. return false;
  613. }
  614. static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
  615. {
  616. struct renesas_sdhi *priv = host_to_priv(host);
  617. bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
  618. /*
  619. * Skip checking SCC errors when running on 4 taps in HS400 mode as
  620. * any retuning would still result in the same 4 taps being used.
  621. */
  622. if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
  623. !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
  624. !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
  625. return false;
  626. if (mmc_doing_tune(host->mmc))
  627. return false;
  628. if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
  629. SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
  630. return renesas_sdhi_auto_correction(host);
  631. return renesas_sdhi_manual_correction(host, use_4tap);
  632. }
  633. static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
  634. {
  635. int timeout = 1000;
  636. /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
  637. u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
  638. while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
  639. & bit) == wait_state)
  640. udelay(1);
  641. if (!timeout) {
  642. dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
  643. return -EBUSY;
  644. }
  645. return 0;
  646. }
  647. static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
  648. {
  649. u32 bit = TMIO_STAT_SCLKDIVEN;
  650. switch (addr) {
  651. case CTL_SD_CMD:
  652. case CTL_STOP_INTERNAL_ACTION:
  653. case CTL_XFER_BLK_COUNT:
  654. case CTL_SD_XFER_LEN:
  655. case CTL_SD_MEM_CARD_OPT:
  656. case CTL_TRANSACTION_CTL:
  657. case CTL_DMA_ENABLE:
  658. case HOST_MODE:
  659. if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
  660. bit = TMIO_STAT_CMD_BUSY;
  661. fallthrough;
  662. case CTL_SD_CARD_CLK_CTL:
  663. return renesas_sdhi_wait_idle(host, bit);
  664. }
  665. return 0;
  666. }
  667. static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
  668. unsigned int direction, int blk_size)
  669. {
  670. /*
  671. * In Renesas controllers, when performing a
  672. * multiple block read of one or two blocks,
  673. * depending on the timing with which the
  674. * response register is read, the response
  675. * value may not be read properly.
  676. * Use single block read for this HW bug
  677. */
  678. if ((direction == MMC_DATA_READ) &&
  679. blk_size == 2)
  680. return 1;
  681. return blk_size;
  682. }
  683. static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
  684. {
  685. struct renesas_sdhi *priv = host_to_priv(host);
  686. if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
  687. renesas_sdhi_adjust_hs400_mode_enable(host);
  688. }
  689. static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
  690. {
  691. /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
  692. int width = (host->bus_shift == 2) ? 64 : 32;
  693. sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
  694. renesas_sdhi_sdbuf_width(host, enable ? width : 16);
  695. }
  696. static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
  697. .hs400_disabled = true,
  698. .hs400_4taps = true,
  699. };
  700. static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
  701. .hs400_4taps = true,
  702. .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
  703. };
  704. static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
  705. .hs400_disabled = true,
  706. };
  707. static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
  708. .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
  709. };
  710. static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
  711. .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
  712. };
  713. static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
  714. .hs400_4taps = true,
  715. .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
  716. .hs400_calib_table = r8a7796_es13_calib_table,
  717. };
  718. static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
  719. .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
  720. .hs400_calib_table = r8a77965_calib_table,
  721. };
  722. static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
  723. .hs400_calib_table = r8a77990_calib_table,
  724. };
  725. /*
  726. * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
  727. * So, we want to treat them equally and only have a match for ES1.2 to enforce
  728. * this if there ever will be a way to distinguish ES1.2.
  729. */
  730. static const struct soc_device_attribute sdhi_quirks_match[] = {
  731. { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
  732. { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
  733. { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
  734. { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
  735. { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
  736. { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
  737. { .soc_id = "r8a77961", .data = &sdhi_quirks_bad_taps1357 },
  738. { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
  739. { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
  740. { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
  741. { /* Sentinel. */ },
  742. };
  743. int renesas_sdhi_probe(struct platform_device *pdev,
  744. const struct tmio_mmc_dma_ops *dma_ops)
  745. {
  746. struct tmio_mmc_data *mmd = pdev->dev.platform_data;
  747. const struct renesas_sdhi_quirks *quirks = NULL;
  748. const struct renesas_sdhi_of_data *of_data;
  749. const struct soc_device_attribute *attr;
  750. struct tmio_mmc_data *mmc_data;
  751. struct tmio_mmc_dma *dma_priv;
  752. struct tmio_mmc_host *host;
  753. struct renesas_sdhi *priv;
  754. int num_irqs, irq, ret, i;
  755. struct resource *res;
  756. u16 ver;
  757. of_data = of_device_get_match_data(&pdev->dev);
  758. attr = soc_device_match(sdhi_quirks_match);
  759. if (attr)
  760. quirks = attr->data;
  761. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  762. if (!res)
  763. return -EINVAL;
  764. priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
  765. GFP_KERNEL);
  766. if (!priv)
  767. return -ENOMEM;
  768. priv->quirks = quirks;
  769. mmc_data = &priv->mmc_data;
  770. dma_priv = &priv->dma_priv;
  771. priv->clk = devm_clk_get(&pdev->dev, NULL);
  772. if (IS_ERR(priv->clk)) {
  773. ret = PTR_ERR(priv->clk);
  774. dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
  775. return ret;
  776. }
  777. /*
  778. * Some controllers provide a 2nd clock just to run the internal card
  779. * detection logic. Unfortunately, the existing driver architecture does
  780. * not support a separation of clocks for runtime PM usage. When
  781. * native hotplug is used, the tmio driver assumes that the core
  782. * must continue to run for card detect to stay active, so we cannot
  783. * disable it.
  784. * Additionally, it is prohibited to supply a clock to the core but not
  785. * to the card detect circuit. That leaves us with if separate clocks
  786. * are presented, we must treat them both as virtually 1 clock.
  787. */
  788. priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
  789. if (IS_ERR(priv->clk_cd))
  790. priv->clk_cd = NULL;
  791. priv->pinctrl = devm_pinctrl_get(&pdev->dev);
  792. if (!IS_ERR(priv->pinctrl)) {
  793. priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
  794. PINCTRL_STATE_DEFAULT);
  795. priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
  796. "state_uhs");
  797. }
  798. host = tmio_mmc_host_alloc(pdev, mmc_data);
  799. if (IS_ERR(host))
  800. return PTR_ERR(host);
  801. if (of_data) {
  802. mmc_data->flags |= of_data->tmio_flags;
  803. mmc_data->ocr_mask = of_data->tmio_ocr_mask;
  804. mmc_data->capabilities |= of_data->capabilities;
  805. mmc_data->capabilities2 |= of_data->capabilities2;
  806. mmc_data->dma_rx_offset = of_data->dma_rx_offset;
  807. mmc_data->max_blk_count = of_data->max_blk_count;
  808. mmc_data->max_segs = of_data->max_segs;
  809. dma_priv->dma_buswidth = of_data->dma_buswidth;
  810. host->bus_shift = of_data->bus_shift;
  811. }
  812. host->write16_hook = renesas_sdhi_write16_hook;
  813. host->clk_enable = renesas_sdhi_clk_enable;
  814. host->clk_disable = renesas_sdhi_clk_disable;
  815. host->set_clock = renesas_sdhi_set_clock;
  816. host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
  817. host->dma_ops = dma_ops;
  818. if (quirks && quirks->hs400_disabled)
  819. host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
  820. /* For some SoC, we disable internal WP. GPIO may override this */
  821. if (mmc_can_gpio_ro(host->mmc))
  822. mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
  823. /* SDR speeds are only available on Gen2+ */
  824. if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
  825. /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
  826. host->ops.card_busy = renesas_sdhi_card_busy;
  827. host->ops.start_signal_voltage_switch =
  828. renesas_sdhi_start_signal_voltage_switch;
  829. host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
  830. if (of_data && of_data->scc_offset) {
  831. priv->scc_ctl = host->ctl + of_data->scc_offset;
  832. host->reset = renesas_sdhi_reset;
  833. }
  834. }
  835. /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
  836. if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
  837. host->bus_shift = 1;
  838. if (mmd)
  839. *mmc_data = *mmd;
  840. dma_priv->filter = shdma_chan_filter;
  841. dma_priv->enable = renesas_sdhi_enable_dma;
  842. mmc_data->alignment_shift = 1; /* 2-byte alignment */
  843. mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
  844. /*
  845. * All SDHI blocks support 2-byte and larger block sizes in 4-bit
  846. * bus width mode.
  847. */
  848. mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
  849. /*
  850. * All SDHI blocks support SDIO IRQ signalling.
  851. */
  852. mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
  853. /* All SDHI have CMD12 control bit */
  854. mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
  855. /* All SDHI have SDIO status bits which must be 1 */
  856. mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
  857. dev_pm_domain_start(&pdev->dev);
  858. ret = renesas_sdhi_clk_enable(host);
  859. if (ret)
  860. goto efree;
  861. ver = sd_ctrl_read16(host, CTL_VERSION);
  862. /* GEN2_SDR104 is first known SDHI to use 32bit block count */
  863. if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
  864. mmc_data->max_blk_count = U16_MAX;
  865. /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
  866. if (ver == SDHI_VER_GEN2_SDR50)
  867. mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
  868. if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
  869. host->fixup_request = renesas_sdhi_fixup_request;
  870. priv->adjust_hs400_calib_table = *(
  871. res->start == SDHI_GEN3_MMC0_ADDR ?
  872. quirks->hs400_calib_table :
  873. quirks->hs400_calib_table + 1);
  874. }
  875. ret = tmio_mmc_host_probe(host);
  876. if (ret < 0)
  877. goto edisclk;
  878. /* Enable tuning iff we have an SCC and a supported mode */
  879. if (of_data && of_data->scc_offset &&
  880. (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
  881. host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
  882. MMC_CAP2_HS400_1_8V))) {
  883. const struct renesas_sdhi_scc *taps = of_data->taps;
  884. bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
  885. bool hit = false;
  886. for (i = 0; i < of_data->taps_num; i++) {
  887. if (taps[i].clk_rate == 0 ||
  888. taps[i].clk_rate == host->mmc->f_max) {
  889. priv->scc_tappos = taps->tap;
  890. priv->scc_tappos_hs400 = use_4tap ?
  891. taps->tap_hs400_4tap :
  892. taps->tap;
  893. hit = true;
  894. break;
  895. }
  896. }
  897. if (!hit)
  898. dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
  899. host->check_retune = renesas_sdhi_check_scc_error;
  900. host->ops.execute_tuning = renesas_sdhi_execute_tuning;
  901. host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
  902. host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
  903. host->ops.hs400_complete = renesas_sdhi_hs400_complete;
  904. }
  905. num_irqs = platform_irq_count(pdev);
  906. if (num_irqs < 0) {
  907. ret = num_irqs;
  908. goto eirq;
  909. }
  910. /* There must be at least one IRQ source */
  911. if (!num_irqs) {
  912. ret = -ENXIO;
  913. goto eirq;
  914. }
  915. for (i = 0; i < num_irqs; i++) {
  916. irq = platform_get_irq(pdev, i);
  917. if (irq < 0) {
  918. ret = irq;
  919. goto eirq;
  920. }
  921. ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
  922. dev_name(&pdev->dev), host);
  923. if (ret)
  924. goto eirq;
  925. }
  926. dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
  927. mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
  928. return ret;
  929. eirq:
  930. tmio_mmc_host_remove(host);
  931. edisclk:
  932. renesas_sdhi_clk_disable(host);
  933. efree:
  934. tmio_mmc_host_free(host);
  935. return ret;
  936. }
  937. EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
  938. int renesas_sdhi_remove(struct platform_device *pdev)
  939. {
  940. struct tmio_mmc_host *host = platform_get_drvdata(pdev);
  941. tmio_mmc_host_remove(host);
  942. renesas_sdhi_clk_disable(host);
  943. tmio_mmc_host_free(host);
  944. return 0;
  945. }
  946. EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
  947. MODULE_LICENSE("GPL v2");