owl-mmc.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Actions Semi Owl SoCs SD/MMC driver
  4. *
  5. * Copyright (c) 2014 Actions Semi Inc.
  6. * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7. *
  8. * TODO: SDIO support
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/dma-direction.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mmc/host.h>
  17. #include <linux/mmc/slot-gpio.h>
  18. #include <linux/module.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/reset.h>
  21. #include <linux/spinlock.h>
  22. /*
  23. * SDC registers
  24. */
  25. #define OWL_REG_SD_EN 0x0000
  26. #define OWL_REG_SD_CTL 0x0004
  27. #define OWL_REG_SD_STATE 0x0008
  28. #define OWL_REG_SD_CMD 0x000c
  29. #define OWL_REG_SD_ARG 0x0010
  30. #define OWL_REG_SD_RSPBUF0 0x0014
  31. #define OWL_REG_SD_RSPBUF1 0x0018
  32. #define OWL_REG_SD_RSPBUF2 0x001c
  33. #define OWL_REG_SD_RSPBUF3 0x0020
  34. #define OWL_REG_SD_RSPBUF4 0x0024
  35. #define OWL_REG_SD_DAT 0x0028
  36. #define OWL_REG_SD_BLK_SIZE 0x002c
  37. #define OWL_REG_SD_BLK_NUM 0x0030
  38. #define OWL_REG_SD_BUF_SIZE 0x0034
  39. /* SD_EN Bits */
  40. #define OWL_SD_EN_RANE BIT(31)
  41. #define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
  42. #define OWL_SD_EN_S18EN BIT(12)
  43. #define OWL_SD_EN_RESE BIT(10)
  44. #define OWL_SD_EN_DAT1_S BIT(9)
  45. #define OWL_SD_EN_CLK_S BIT(8)
  46. #define OWL_SD_ENABLE BIT(7)
  47. #define OWL_SD_EN_BSEL BIT(6)
  48. #define OWL_SD_EN_SDIOEN BIT(3)
  49. #define OWL_SD_EN_DDREN BIT(2)
  50. #define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
  51. /* SD_CTL Bits */
  52. #define OWL_SD_CTL_TOUTEN BIT(31)
  53. #define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
  54. #define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
  55. #define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
  56. #define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
  57. #define OWL_SD_CTL_CMDLEN BIT(13)
  58. #define OWL_SD_CTL_SCC BIT(12)
  59. #define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
  60. #define OWL_SD_CTL_TS BIT(7)
  61. #define OWL_SD_CTL_LBE BIT(6)
  62. #define OWL_SD_CTL_C7EN BIT(5)
  63. #define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
  64. #define OWL_SD_DELAY_LOW_CLK 0x0f
  65. #define OWL_SD_DELAY_MID_CLK 0x0a
  66. #define OWL_SD_DELAY_HIGH_CLK 0x09
  67. #define OWL_SD_RDELAY_DDR50 0x0a
  68. #define OWL_SD_WDELAY_DDR50 0x08
  69. /* SD_STATE Bits */
  70. #define OWL_SD_STATE_DAT1BS BIT(18)
  71. #define OWL_SD_STATE_SDIOB_P BIT(17)
  72. #define OWL_SD_STATE_SDIOB_EN BIT(16)
  73. #define OWL_SD_STATE_TOUTE BIT(15)
  74. #define OWL_SD_STATE_BAEP BIT(14)
  75. #define OWL_SD_STATE_MEMRDY BIT(12)
  76. #define OWL_SD_STATE_CMDS BIT(11)
  77. #define OWL_SD_STATE_DAT1AS BIT(10)
  78. #define OWL_SD_STATE_SDIOA_P BIT(9)
  79. #define OWL_SD_STATE_SDIOA_EN BIT(8)
  80. #define OWL_SD_STATE_DAT0S BIT(7)
  81. #define OWL_SD_STATE_TEIE BIT(6)
  82. #define OWL_SD_STATE_TEI BIT(5)
  83. #define OWL_SD_STATE_CLNR BIT(4)
  84. #define OWL_SD_STATE_CLC BIT(3)
  85. #define OWL_SD_STATE_WC16ER BIT(2)
  86. #define OWL_SD_STATE_RC16ER BIT(1)
  87. #define OWL_SD_STATE_CRC7ER BIT(0)
  88. #define OWL_CMD_TIMEOUT_MS 30000
  89. struct owl_mmc_host {
  90. struct device *dev;
  91. struct reset_control *reset;
  92. void __iomem *base;
  93. struct clk *clk;
  94. struct completion sdc_complete;
  95. spinlock_t lock;
  96. int irq;
  97. u32 clock;
  98. bool ddr_50;
  99. enum dma_data_direction dma_dir;
  100. struct dma_chan *dma;
  101. struct dma_async_tx_descriptor *desc;
  102. struct dma_slave_config dma_cfg;
  103. struct completion dma_complete;
  104. struct mmc_host *mmc;
  105. struct mmc_request *mrq;
  106. struct mmc_command *cmd;
  107. struct mmc_data *data;
  108. };
  109. static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
  110. {
  111. unsigned int regval;
  112. regval = readl(reg);
  113. if (state)
  114. regval |= val;
  115. else
  116. regval &= ~val;
  117. writel(regval, reg);
  118. }
  119. static irqreturn_t owl_irq_handler(int irq, void *devid)
  120. {
  121. struct owl_mmc_host *owl_host = devid;
  122. unsigned long flags;
  123. u32 state;
  124. spin_lock_irqsave(&owl_host->lock, flags);
  125. state = readl(owl_host->base + OWL_REG_SD_STATE);
  126. if (state & OWL_SD_STATE_TEI) {
  127. state = readl(owl_host->base + OWL_REG_SD_STATE);
  128. state |= OWL_SD_STATE_TEI;
  129. writel(state, owl_host->base + OWL_REG_SD_STATE);
  130. complete(&owl_host->sdc_complete);
  131. }
  132. spin_unlock_irqrestore(&owl_host->lock, flags);
  133. return IRQ_HANDLED;
  134. }
  135. static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
  136. {
  137. struct mmc_request *mrq = owl_host->mrq;
  138. struct mmc_data *data = mrq->data;
  139. /* Should never be NULL */
  140. WARN_ON(!mrq);
  141. owl_host->mrq = NULL;
  142. if (data)
  143. dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
  144. owl_host->dma_dir);
  145. /* Finally finish request */
  146. mmc_request_done(owl_host->mmc, mrq);
  147. }
  148. static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
  149. struct mmc_command *cmd,
  150. struct mmc_data *data)
  151. {
  152. unsigned long timeout;
  153. u32 mode, state, resp[2];
  154. u32 cmd_rsp_mask = 0;
  155. init_completion(&owl_host->sdc_complete);
  156. switch (mmc_resp_type(cmd)) {
  157. case MMC_RSP_NONE:
  158. mode = OWL_SD_CTL_TM(0);
  159. break;
  160. case MMC_RSP_R1:
  161. if (data) {
  162. if (data->flags & MMC_DATA_READ)
  163. mode = OWL_SD_CTL_TM(4);
  164. else
  165. mode = OWL_SD_CTL_TM(5);
  166. } else {
  167. mode = OWL_SD_CTL_TM(1);
  168. }
  169. cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
  170. break;
  171. case MMC_RSP_R1B:
  172. mode = OWL_SD_CTL_TM(3);
  173. cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
  174. break;
  175. case MMC_RSP_R2:
  176. mode = OWL_SD_CTL_TM(2);
  177. cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
  178. break;
  179. case MMC_RSP_R3:
  180. mode = OWL_SD_CTL_TM(1);
  181. cmd_rsp_mask = OWL_SD_STATE_CLNR;
  182. break;
  183. default:
  184. dev_warn(owl_host->dev, "Unknown MMC command\n");
  185. cmd->error = -EINVAL;
  186. return;
  187. }
  188. /* Keep current WDELAY and RDELAY */
  189. mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
  190. /* Start to send corresponding command type */
  191. writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
  192. writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
  193. /* Set LBE to send clk at the end of last read block */
  194. if (data) {
  195. mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
  196. } else {
  197. mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
  198. mode |= OWL_SD_CTL_TS;
  199. }
  200. owl_host->cmd = cmd;
  201. /* Start transfer */
  202. writel(mode, owl_host->base + OWL_REG_SD_CTL);
  203. if (data)
  204. return;
  205. timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout :
  206. OWL_CMD_TIMEOUT_MS);
  207. if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) {
  208. dev_err(owl_host->dev, "CMD interrupt timeout\n");
  209. cmd->error = -ETIMEDOUT;
  210. return;
  211. }
  212. state = readl(owl_host->base + OWL_REG_SD_STATE);
  213. if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
  214. if (cmd_rsp_mask & state) {
  215. if (state & OWL_SD_STATE_CLNR) {
  216. dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
  217. cmd->error = -EILSEQ;
  218. return;
  219. }
  220. if (state & OWL_SD_STATE_CRC7ER) {
  221. dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
  222. cmd->error = -EILSEQ;
  223. return;
  224. }
  225. }
  226. if (mmc_resp_type(cmd) & MMC_RSP_136) {
  227. cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
  228. cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
  229. cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
  230. cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
  231. } else {
  232. resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
  233. resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
  234. cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
  235. cmd->resp[1] = resp[1] >> 8;
  236. }
  237. }
  238. }
  239. static void owl_mmc_dma_complete(void *param)
  240. {
  241. struct owl_mmc_host *owl_host = param;
  242. struct mmc_data *data = owl_host->data;
  243. if (data)
  244. complete(&owl_host->dma_complete);
  245. }
  246. static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
  247. struct mmc_data *data)
  248. {
  249. u32 total;
  250. owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
  251. true);
  252. writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
  253. writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
  254. total = data->blksz * data->blocks;
  255. if (total < 512)
  256. writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
  257. else
  258. writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
  259. if (data->flags & MMC_DATA_WRITE) {
  260. owl_host->dma_dir = DMA_TO_DEVICE;
  261. owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
  262. } else {
  263. owl_host->dma_dir = DMA_FROM_DEVICE;
  264. owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
  265. }
  266. dma_map_sg(owl_host->dma->device->dev, data->sg,
  267. data->sg_len, owl_host->dma_dir);
  268. dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
  269. owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
  270. data->sg_len,
  271. owl_host->dma_cfg.direction,
  272. DMA_PREP_INTERRUPT |
  273. DMA_CTRL_ACK);
  274. if (!owl_host->desc) {
  275. dev_err(owl_host->dev, "Can't prepare slave sg\n");
  276. return -EBUSY;
  277. }
  278. owl_host->data = data;
  279. owl_host->desc->callback = owl_mmc_dma_complete;
  280. owl_host->desc->callback_param = (void *)owl_host;
  281. data->error = 0;
  282. return 0;
  283. }
  284. static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  285. {
  286. struct owl_mmc_host *owl_host = mmc_priv(mmc);
  287. struct mmc_data *data = mrq->data;
  288. int ret;
  289. owl_host->mrq = mrq;
  290. if (mrq->data) {
  291. ret = owl_mmc_prepare_data(owl_host, data);
  292. if (ret < 0) {
  293. data->error = ret;
  294. goto err_out;
  295. }
  296. init_completion(&owl_host->dma_complete);
  297. dmaengine_submit(owl_host->desc);
  298. dma_async_issue_pending(owl_host->dma);
  299. }
  300. owl_mmc_send_cmd(owl_host, mrq->cmd, data);
  301. if (data) {
  302. if (!wait_for_completion_timeout(&owl_host->sdc_complete,
  303. 10 * HZ)) {
  304. dev_err(owl_host->dev, "CMD interrupt timeout\n");
  305. mrq->cmd->error = -ETIMEDOUT;
  306. dmaengine_terminate_all(owl_host->dma);
  307. goto err_out;
  308. }
  309. if (!wait_for_completion_timeout(&owl_host->dma_complete,
  310. 5 * HZ)) {
  311. dev_err(owl_host->dev, "DMA interrupt timeout\n");
  312. mrq->cmd->error = -ETIMEDOUT;
  313. dmaengine_terminate_all(owl_host->dma);
  314. goto err_out;
  315. }
  316. if (data->stop)
  317. owl_mmc_send_cmd(owl_host, data->stop, NULL);
  318. data->bytes_xfered = data->blocks * data->blksz;
  319. }
  320. err_out:
  321. owl_mmc_finish_request(owl_host);
  322. }
  323. static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
  324. unsigned int rate)
  325. {
  326. unsigned long clk_rate;
  327. int ret;
  328. u32 reg;
  329. reg = readl(owl_host->base + OWL_REG_SD_CTL);
  330. reg &= ~OWL_SD_CTL_DELAY_MSK;
  331. /* Set RDELAY and WDELAY based on the clock */
  332. if (rate <= 1000000) {
  333. writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
  334. OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
  335. owl_host->base + OWL_REG_SD_CTL);
  336. } else if ((rate > 1000000) && (rate <= 26000000)) {
  337. writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
  338. OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
  339. owl_host->base + OWL_REG_SD_CTL);
  340. } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
  341. writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
  342. OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
  343. owl_host->base + OWL_REG_SD_CTL);
  344. /* DDR50 mode has special delay chain */
  345. } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
  346. writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
  347. OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
  348. owl_host->base + OWL_REG_SD_CTL);
  349. } else {
  350. dev_err(owl_host->dev, "SD clock rate not supported\n");
  351. return -EINVAL;
  352. }
  353. clk_rate = clk_round_rate(owl_host->clk, rate << 1);
  354. ret = clk_set_rate(owl_host->clk, clk_rate);
  355. return ret;
  356. }
  357. static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios)
  358. {
  359. if (!ios->clock)
  360. return;
  361. owl_host->clock = ios->clock;
  362. owl_mmc_set_clk_rate(owl_host, ios->clock);
  363. }
  364. static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
  365. struct mmc_ios *ios)
  366. {
  367. u32 reg;
  368. reg = readl(owl_host->base + OWL_REG_SD_EN);
  369. reg &= ~0x03;
  370. switch (ios->bus_width) {
  371. case MMC_BUS_WIDTH_1:
  372. break;
  373. case MMC_BUS_WIDTH_4:
  374. reg |= OWL_SD_EN_DATAWID(1);
  375. break;
  376. case MMC_BUS_WIDTH_8:
  377. reg |= OWL_SD_EN_DATAWID(2);
  378. break;
  379. }
  380. writel(reg, owl_host->base + OWL_REG_SD_EN);
  381. }
  382. static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
  383. {
  384. reset_control_assert(owl_host->reset);
  385. udelay(20);
  386. reset_control_deassert(owl_host->reset);
  387. }
  388. static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
  389. {
  390. u32 mode;
  391. init_completion(&owl_host->sdc_complete);
  392. /* Enable transfer end IRQ */
  393. owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
  394. OWL_SD_STATE_TEIE, true);
  395. /* Send init clk */
  396. mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
  397. mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8);
  398. writel(mode, owl_host->base + OWL_REG_SD_CTL);
  399. if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
  400. dev_err(owl_host->dev, "CMD interrupt timeout\n");
  401. return;
  402. }
  403. }
  404. static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  405. {
  406. struct owl_mmc_host *owl_host = mmc_priv(mmc);
  407. switch (ios->power_mode) {
  408. case MMC_POWER_UP:
  409. dev_dbg(owl_host->dev, "Powering card up\n");
  410. /* Reset the SDC controller to clear all previous states */
  411. owl_mmc_ctr_reset(owl_host);
  412. clk_prepare_enable(owl_host->clk);
  413. writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
  414. owl_host->base + OWL_REG_SD_EN);
  415. break;
  416. case MMC_POWER_ON:
  417. dev_dbg(owl_host->dev, "Powering card on\n");
  418. owl_mmc_power_on(owl_host);
  419. break;
  420. case MMC_POWER_OFF:
  421. dev_dbg(owl_host->dev, "Powering card off\n");
  422. clk_disable_unprepare(owl_host->clk);
  423. return;
  424. default:
  425. dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
  426. break;
  427. }
  428. if (ios->clock != owl_host->clock)
  429. owl_mmc_set_clk(owl_host, ios);
  430. owl_mmc_set_bus_width(owl_host, ios);
  431. /* Enable DDR mode if requested */
  432. if (ios->timing == MMC_TIMING_UHS_DDR50) {
  433. owl_host->ddr_50 = 1;
  434. owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
  435. OWL_SD_EN_DDREN, true);
  436. } else {
  437. owl_host->ddr_50 = 0;
  438. }
  439. }
  440. static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
  441. struct mmc_ios *ios)
  442. {
  443. struct owl_mmc_host *owl_host = mmc_priv(mmc);
  444. /* It is enough to change the pad ctrl bit for voltage switch */
  445. switch (ios->signal_voltage) {
  446. case MMC_SIGNAL_VOLTAGE_330:
  447. owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
  448. OWL_SD_EN_S18EN, false);
  449. break;
  450. case MMC_SIGNAL_VOLTAGE_180:
  451. owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
  452. OWL_SD_EN_S18EN, true);
  453. break;
  454. default:
  455. return -ENOTSUPP;
  456. }
  457. return 0;
  458. }
  459. static const struct mmc_host_ops owl_mmc_ops = {
  460. .request = owl_mmc_request,
  461. .set_ios = owl_mmc_set_ios,
  462. .get_ro = mmc_gpio_get_ro,
  463. .get_cd = mmc_gpio_get_cd,
  464. .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
  465. };
  466. static int owl_mmc_probe(struct platform_device *pdev)
  467. {
  468. struct owl_mmc_host *owl_host;
  469. struct mmc_host *mmc;
  470. struct resource *res;
  471. int ret;
  472. mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
  473. if (!mmc) {
  474. dev_err(&pdev->dev, "mmc alloc host failed\n");
  475. return -ENOMEM;
  476. }
  477. platform_set_drvdata(pdev, mmc);
  478. owl_host = mmc_priv(mmc);
  479. owl_host->dev = &pdev->dev;
  480. owl_host->mmc = mmc;
  481. spin_lock_init(&owl_host->lock);
  482. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  483. owl_host->base = devm_ioremap_resource(&pdev->dev, res);
  484. if (IS_ERR(owl_host->base)) {
  485. dev_err(&pdev->dev, "Failed to remap registers\n");
  486. ret = PTR_ERR(owl_host->base);
  487. goto err_free_host;
  488. }
  489. owl_host->clk = devm_clk_get(&pdev->dev, NULL);
  490. if (IS_ERR(owl_host->clk)) {
  491. dev_err(&pdev->dev, "No clock defined\n");
  492. ret = PTR_ERR(owl_host->clk);
  493. goto err_free_host;
  494. }
  495. owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  496. if (IS_ERR(owl_host->reset)) {
  497. dev_err(&pdev->dev, "Could not get reset control\n");
  498. ret = PTR_ERR(owl_host->reset);
  499. goto err_free_host;
  500. }
  501. mmc->ops = &owl_mmc_ops;
  502. mmc->max_blk_count = 512;
  503. mmc->max_blk_size = 512;
  504. mmc->max_segs = 256;
  505. mmc->max_seg_size = 262144;
  506. mmc->max_req_size = 262144;
  507. /* 100kHz ~ 52MHz */
  508. mmc->f_min = 100000;
  509. mmc->f_max = 52000000;
  510. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  511. MMC_CAP_4_BIT_DATA;
  512. mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);
  513. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 |
  514. MMC_VDD_165_195;
  515. ret = mmc_of_parse(mmc);
  516. if (ret)
  517. goto err_free_host;
  518. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  519. pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
  520. owl_host->dma = dma_request_chan(&pdev->dev, "mmc");
  521. if (IS_ERR(owl_host->dma)) {
  522. dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
  523. ret = PTR_ERR(owl_host->dma);
  524. goto err_free_host;
  525. }
  526. dev_info(&pdev->dev, "Using %s for DMA transfers\n",
  527. dma_chan_name(owl_host->dma));
  528. owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
  529. owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
  530. owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  531. owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  532. owl_host->dma_cfg.device_fc = false;
  533. owl_host->irq = platform_get_irq(pdev, 0);
  534. if (owl_host->irq < 0) {
  535. ret = -EINVAL;
  536. goto err_release_channel;
  537. }
  538. ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
  539. 0, dev_name(&pdev->dev), owl_host);
  540. if (ret) {
  541. dev_err(&pdev->dev, "Failed to request irq %d\n",
  542. owl_host->irq);
  543. goto err_release_channel;
  544. }
  545. ret = mmc_add_host(mmc);
  546. if (ret) {
  547. dev_err(&pdev->dev, "Failed to add host\n");
  548. goto err_release_channel;
  549. }
  550. dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
  551. return 0;
  552. err_release_channel:
  553. dma_release_channel(owl_host->dma);
  554. err_free_host:
  555. mmc_free_host(mmc);
  556. return ret;
  557. }
  558. static int owl_mmc_remove(struct platform_device *pdev)
  559. {
  560. struct mmc_host *mmc = platform_get_drvdata(pdev);
  561. struct owl_mmc_host *owl_host = mmc_priv(mmc);
  562. mmc_remove_host(mmc);
  563. disable_irq(owl_host->irq);
  564. dma_release_channel(owl_host->dma);
  565. mmc_free_host(mmc);
  566. return 0;
  567. }
  568. static const struct of_device_id owl_mmc_of_match[] = {
  569. {.compatible = "actions,owl-mmc",},
  570. { /* sentinel */ }
  571. };
  572. MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
  573. static struct platform_driver owl_mmc_driver = {
  574. .driver = {
  575. .name = "owl_mmc",
  576. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  577. .of_match_table = owl_mmc_of_match,
  578. },
  579. .probe = owl_mmc_probe,
  580. .remove = owl_mmc_remove,
  581. };
  582. module_platform_driver(owl_mmc_driver);
  583. MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
  584. MODULE_AUTHOR("Actions Semi");
  585. MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
  586. MODULE_LICENSE("GPL");