omap.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/host/omap.c
  4. *
  5. * Copyright (C) 2004 Nokia Corporation
  6. * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
  7. * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
  8. * Other hacks (DMA, SD, etc) by David Brownell
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/init.h>
  13. #include <linux/ioport.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/dmaengine.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/delay.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/timer.h>
  21. #include <linux/of.h>
  22. #include <linux/mmc/host.h>
  23. #include <linux/mmc/card.h>
  24. #include <linux/mmc/mmc.h>
  25. #include <linux/clk.h>
  26. #include <linux/scatterlist.h>
  27. #include <linux/slab.h>
  28. #include <linux/platform_data/mmc-omap.h>
  29. #define OMAP_MMC_REG_CMD 0x00
  30. #define OMAP_MMC_REG_ARGL 0x01
  31. #define OMAP_MMC_REG_ARGH 0x02
  32. #define OMAP_MMC_REG_CON 0x03
  33. #define OMAP_MMC_REG_STAT 0x04
  34. #define OMAP_MMC_REG_IE 0x05
  35. #define OMAP_MMC_REG_CTO 0x06
  36. #define OMAP_MMC_REG_DTO 0x07
  37. #define OMAP_MMC_REG_DATA 0x08
  38. #define OMAP_MMC_REG_BLEN 0x09
  39. #define OMAP_MMC_REG_NBLK 0x0a
  40. #define OMAP_MMC_REG_BUF 0x0b
  41. #define OMAP_MMC_REG_SDIO 0x0d
  42. #define OMAP_MMC_REG_REV 0x0f
  43. #define OMAP_MMC_REG_RSP0 0x10
  44. #define OMAP_MMC_REG_RSP1 0x11
  45. #define OMAP_MMC_REG_RSP2 0x12
  46. #define OMAP_MMC_REG_RSP3 0x13
  47. #define OMAP_MMC_REG_RSP4 0x14
  48. #define OMAP_MMC_REG_RSP5 0x15
  49. #define OMAP_MMC_REG_RSP6 0x16
  50. #define OMAP_MMC_REG_RSP7 0x17
  51. #define OMAP_MMC_REG_IOSR 0x18
  52. #define OMAP_MMC_REG_SYSC 0x19
  53. #define OMAP_MMC_REG_SYSS 0x1a
  54. #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
  55. #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
  56. #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
  57. #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
  58. #define OMAP_MMC_STAT_A_FULL (1 << 10)
  59. #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
  60. #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
  61. #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
  62. #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
  63. #define OMAP_MMC_STAT_END_BUSY (1 << 4)
  64. #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
  65. #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
  66. #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
  67. #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
  68. #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
  69. #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
  70. #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
  71. #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
  72. #define mmc_omap2() (!mmc_omap1())
  73. #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
  74. #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
  75. #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
  76. /*
  77. * Command types
  78. */
  79. #define OMAP_MMC_CMDTYPE_BC 0
  80. #define OMAP_MMC_CMDTYPE_BCR 1
  81. #define OMAP_MMC_CMDTYPE_AC 2
  82. #define OMAP_MMC_CMDTYPE_ADTC 3
  83. #define DRIVER_NAME "mmci-omap"
  84. /* Specifies how often in millisecs to poll for card status changes
  85. * when the cover switch is open */
  86. #define OMAP_MMC_COVER_POLL_DELAY 500
  87. struct mmc_omap_host;
  88. struct mmc_omap_slot {
  89. int id;
  90. unsigned int vdd;
  91. u16 saved_con;
  92. u16 bus_mode;
  93. u16 power_mode;
  94. unsigned int fclk_freq;
  95. struct tasklet_struct cover_tasklet;
  96. struct timer_list cover_timer;
  97. unsigned cover_open;
  98. struct mmc_request *mrq;
  99. struct mmc_omap_host *host;
  100. struct mmc_host *mmc;
  101. struct omap_mmc_slot_data *pdata;
  102. };
  103. struct mmc_omap_host {
  104. int initialized;
  105. struct mmc_request * mrq;
  106. struct mmc_command * cmd;
  107. struct mmc_data * data;
  108. struct mmc_host * mmc;
  109. struct device * dev;
  110. unsigned char id; /* 16xx chips have 2 MMC blocks */
  111. struct clk * iclk;
  112. struct clk * fclk;
  113. struct dma_chan *dma_rx;
  114. u32 dma_rx_burst;
  115. struct dma_chan *dma_tx;
  116. u32 dma_tx_burst;
  117. void __iomem *virt_base;
  118. unsigned int phys_base;
  119. int irq;
  120. unsigned char bus_mode;
  121. unsigned int reg_shift;
  122. struct work_struct cmd_abort_work;
  123. unsigned abort:1;
  124. struct timer_list cmd_abort_timer;
  125. struct work_struct slot_release_work;
  126. struct mmc_omap_slot *next_slot;
  127. struct work_struct send_stop_work;
  128. struct mmc_data *stop_data;
  129. unsigned int sg_len;
  130. int sg_idx;
  131. u16 * buffer;
  132. u32 buffer_bytes_left;
  133. u32 total_bytes_left;
  134. unsigned features;
  135. unsigned brs_received:1, dma_done:1;
  136. unsigned dma_in_use:1;
  137. spinlock_t dma_lock;
  138. struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
  139. struct mmc_omap_slot *current_slot;
  140. spinlock_t slot_lock;
  141. wait_queue_head_t slot_wq;
  142. int nr_slots;
  143. struct timer_list clk_timer;
  144. spinlock_t clk_lock; /* for changing enabled state */
  145. unsigned int fclk_enabled:1;
  146. struct workqueue_struct *mmc_omap_wq;
  147. struct omap_mmc_platform_data *pdata;
  148. };
  149. static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
  150. {
  151. unsigned long tick_ns;
  152. if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
  153. tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
  154. ndelay(8 * tick_ns);
  155. }
  156. }
  157. static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
  158. {
  159. unsigned long flags;
  160. spin_lock_irqsave(&host->clk_lock, flags);
  161. if (host->fclk_enabled != enable) {
  162. host->fclk_enabled = enable;
  163. if (enable)
  164. clk_enable(host->fclk);
  165. else
  166. clk_disable(host->fclk);
  167. }
  168. spin_unlock_irqrestore(&host->clk_lock, flags);
  169. }
  170. static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
  171. {
  172. struct mmc_omap_host *host = slot->host;
  173. unsigned long flags;
  174. if (claimed)
  175. goto no_claim;
  176. spin_lock_irqsave(&host->slot_lock, flags);
  177. while (host->mmc != NULL) {
  178. spin_unlock_irqrestore(&host->slot_lock, flags);
  179. wait_event(host->slot_wq, host->mmc == NULL);
  180. spin_lock_irqsave(&host->slot_lock, flags);
  181. }
  182. host->mmc = slot->mmc;
  183. spin_unlock_irqrestore(&host->slot_lock, flags);
  184. no_claim:
  185. del_timer(&host->clk_timer);
  186. if (host->current_slot != slot || !claimed)
  187. mmc_omap_fclk_offdelay(host->current_slot);
  188. if (host->current_slot != slot) {
  189. OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
  190. if (host->pdata->switch_slot != NULL)
  191. host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
  192. host->current_slot = slot;
  193. }
  194. if (claimed) {
  195. mmc_omap_fclk_enable(host, 1);
  196. /* Doing the dummy read here seems to work around some bug
  197. * at least in OMAP24xx silicon where the command would not
  198. * start after writing the CMD register. Sigh. */
  199. OMAP_MMC_READ(host, CON);
  200. OMAP_MMC_WRITE(host, CON, slot->saved_con);
  201. } else
  202. mmc_omap_fclk_enable(host, 0);
  203. }
  204. static void mmc_omap_start_request(struct mmc_omap_host *host,
  205. struct mmc_request *req);
  206. static void mmc_omap_slot_release_work(struct work_struct *work)
  207. {
  208. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  209. slot_release_work);
  210. struct mmc_omap_slot *next_slot = host->next_slot;
  211. struct mmc_request *rq;
  212. host->next_slot = NULL;
  213. mmc_omap_select_slot(next_slot, 1);
  214. rq = next_slot->mrq;
  215. next_slot->mrq = NULL;
  216. mmc_omap_start_request(host, rq);
  217. }
  218. static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
  219. {
  220. struct mmc_omap_host *host = slot->host;
  221. unsigned long flags;
  222. int i;
  223. BUG_ON(slot == NULL || host->mmc == NULL);
  224. if (clk_enabled)
  225. /* Keeps clock running for at least 8 cycles on valid freq */
  226. mod_timer(&host->clk_timer, jiffies + HZ/10);
  227. else {
  228. del_timer(&host->clk_timer);
  229. mmc_omap_fclk_offdelay(slot);
  230. mmc_omap_fclk_enable(host, 0);
  231. }
  232. spin_lock_irqsave(&host->slot_lock, flags);
  233. /* Check for any pending requests */
  234. for (i = 0; i < host->nr_slots; i++) {
  235. struct mmc_omap_slot *new_slot;
  236. if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
  237. continue;
  238. BUG_ON(host->next_slot != NULL);
  239. new_slot = host->slots[i];
  240. /* The current slot should not have a request in queue */
  241. BUG_ON(new_slot == host->current_slot);
  242. host->next_slot = new_slot;
  243. host->mmc = new_slot->mmc;
  244. spin_unlock_irqrestore(&host->slot_lock, flags);
  245. queue_work(host->mmc_omap_wq, &host->slot_release_work);
  246. return;
  247. }
  248. host->mmc = NULL;
  249. wake_up(&host->slot_wq);
  250. spin_unlock_irqrestore(&host->slot_lock, flags);
  251. }
  252. static inline
  253. int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
  254. {
  255. if (slot->pdata->get_cover_state)
  256. return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
  257. slot->id);
  258. return 0;
  259. }
  260. static ssize_t
  261. mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
  262. char *buf)
  263. {
  264. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  265. struct mmc_omap_slot *slot = mmc_priv(mmc);
  266. return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
  267. "closed");
  268. }
  269. static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
  270. static ssize_t
  271. mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
  272. char *buf)
  273. {
  274. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  275. struct mmc_omap_slot *slot = mmc_priv(mmc);
  276. return sprintf(buf, "%s\n", slot->pdata->name);
  277. }
  278. static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
  279. static void
  280. mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
  281. {
  282. u32 cmdreg;
  283. u32 resptype;
  284. u32 cmdtype;
  285. u16 irq_mask;
  286. host->cmd = cmd;
  287. resptype = 0;
  288. cmdtype = 0;
  289. /* Our hardware needs to know exact type */
  290. switch (mmc_resp_type(cmd)) {
  291. case MMC_RSP_NONE:
  292. break;
  293. case MMC_RSP_R1:
  294. case MMC_RSP_R1B:
  295. /* resp 1, 1b, 6, 7 */
  296. resptype = 1;
  297. break;
  298. case MMC_RSP_R2:
  299. resptype = 2;
  300. break;
  301. case MMC_RSP_R3:
  302. resptype = 3;
  303. break;
  304. default:
  305. dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
  306. break;
  307. }
  308. if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
  309. cmdtype = OMAP_MMC_CMDTYPE_ADTC;
  310. } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
  311. cmdtype = OMAP_MMC_CMDTYPE_BC;
  312. } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
  313. cmdtype = OMAP_MMC_CMDTYPE_BCR;
  314. } else {
  315. cmdtype = OMAP_MMC_CMDTYPE_AC;
  316. }
  317. cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
  318. if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
  319. cmdreg |= 1 << 6;
  320. if (cmd->flags & MMC_RSP_BUSY)
  321. cmdreg |= 1 << 11;
  322. if (host->data && !(host->data->flags & MMC_DATA_WRITE))
  323. cmdreg |= 1 << 15;
  324. mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
  325. OMAP_MMC_WRITE(host, CTO, 200);
  326. OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
  327. OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
  328. irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
  329. OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
  330. OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
  331. OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
  332. OMAP_MMC_STAT_END_OF_DATA;
  333. if (cmd->opcode == MMC_ERASE)
  334. irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
  335. OMAP_MMC_WRITE(host, IE, irq_mask);
  336. OMAP_MMC_WRITE(host, CMD, cmdreg);
  337. }
  338. static void
  339. mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
  340. int abort)
  341. {
  342. enum dma_data_direction dma_data_dir;
  343. struct device *dev = mmc_dev(host->mmc);
  344. struct dma_chan *c;
  345. if (data->flags & MMC_DATA_WRITE) {
  346. dma_data_dir = DMA_TO_DEVICE;
  347. c = host->dma_tx;
  348. } else {
  349. dma_data_dir = DMA_FROM_DEVICE;
  350. c = host->dma_rx;
  351. }
  352. if (c) {
  353. if (data->error) {
  354. dmaengine_terminate_all(c);
  355. /* Claim nothing transferred on error... */
  356. data->bytes_xfered = 0;
  357. }
  358. dev = c->device->dev;
  359. }
  360. dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
  361. }
  362. static void mmc_omap_send_stop_work(struct work_struct *work)
  363. {
  364. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  365. send_stop_work);
  366. struct mmc_omap_slot *slot = host->current_slot;
  367. struct mmc_data *data = host->stop_data;
  368. unsigned long tick_ns;
  369. tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
  370. ndelay(8*tick_ns);
  371. mmc_omap_start_command(host, data->stop);
  372. }
  373. static void
  374. mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
  375. {
  376. if (host->dma_in_use)
  377. mmc_omap_release_dma(host, data, data->error);
  378. host->data = NULL;
  379. host->sg_len = 0;
  380. /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
  381. * dozens of requests until the card finishes writing data.
  382. * It'd be cheaper to just wait till an EOFB interrupt arrives...
  383. */
  384. if (!data->stop) {
  385. struct mmc_host *mmc;
  386. host->mrq = NULL;
  387. mmc = host->mmc;
  388. mmc_omap_release_slot(host->current_slot, 1);
  389. mmc_request_done(mmc, data->mrq);
  390. return;
  391. }
  392. host->stop_data = data;
  393. queue_work(host->mmc_omap_wq, &host->send_stop_work);
  394. }
  395. static void
  396. mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
  397. {
  398. struct mmc_omap_slot *slot = host->current_slot;
  399. unsigned int restarts, passes, timeout;
  400. u16 stat = 0;
  401. /* Sending abort takes 80 clocks. Have some extra and round up */
  402. timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
  403. restarts = 0;
  404. while (restarts < maxloops) {
  405. OMAP_MMC_WRITE(host, STAT, 0xFFFF);
  406. OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
  407. passes = 0;
  408. while (passes < timeout) {
  409. stat = OMAP_MMC_READ(host, STAT);
  410. if (stat & OMAP_MMC_STAT_END_OF_CMD)
  411. goto out;
  412. udelay(1);
  413. passes++;
  414. }
  415. restarts++;
  416. }
  417. out:
  418. OMAP_MMC_WRITE(host, STAT, stat);
  419. }
  420. static void
  421. mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
  422. {
  423. if (host->dma_in_use)
  424. mmc_omap_release_dma(host, data, 1);
  425. host->data = NULL;
  426. host->sg_len = 0;
  427. mmc_omap_send_abort(host, 10000);
  428. }
  429. static void
  430. mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
  431. {
  432. unsigned long flags;
  433. int done;
  434. if (!host->dma_in_use) {
  435. mmc_omap_xfer_done(host, data);
  436. return;
  437. }
  438. done = 0;
  439. spin_lock_irqsave(&host->dma_lock, flags);
  440. if (host->dma_done)
  441. done = 1;
  442. else
  443. host->brs_received = 1;
  444. spin_unlock_irqrestore(&host->dma_lock, flags);
  445. if (done)
  446. mmc_omap_xfer_done(host, data);
  447. }
  448. static void
  449. mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
  450. {
  451. unsigned long flags;
  452. int done;
  453. done = 0;
  454. spin_lock_irqsave(&host->dma_lock, flags);
  455. if (host->brs_received)
  456. done = 1;
  457. else
  458. host->dma_done = 1;
  459. spin_unlock_irqrestore(&host->dma_lock, flags);
  460. if (done)
  461. mmc_omap_xfer_done(host, data);
  462. }
  463. static void
  464. mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
  465. {
  466. host->cmd = NULL;
  467. del_timer(&host->cmd_abort_timer);
  468. if (cmd->flags & MMC_RSP_PRESENT) {
  469. if (cmd->flags & MMC_RSP_136) {
  470. /* response type 2 */
  471. cmd->resp[3] =
  472. OMAP_MMC_READ(host, RSP0) |
  473. (OMAP_MMC_READ(host, RSP1) << 16);
  474. cmd->resp[2] =
  475. OMAP_MMC_READ(host, RSP2) |
  476. (OMAP_MMC_READ(host, RSP3) << 16);
  477. cmd->resp[1] =
  478. OMAP_MMC_READ(host, RSP4) |
  479. (OMAP_MMC_READ(host, RSP5) << 16);
  480. cmd->resp[0] =
  481. OMAP_MMC_READ(host, RSP6) |
  482. (OMAP_MMC_READ(host, RSP7) << 16);
  483. } else {
  484. /* response types 1, 1b, 3, 4, 5, 6 */
  485. cmd->resp[0] =
  486. OMAP_MMC_READ(host, RSP6) |
  487. (OMAP_MMC_READ(host, RSP7) << 16);
  488. }
  489. }
  490. if (host->data == NULL || cmd->error) {
  491. struct mmc_host *mmc;
  492. if (host->data != NULL)
  493. mmc_omap_abort_xfer(host, host->data);
  494. host->mrq = NULL;
  495. mmc = host->mmc;
  496. mmc_omap_release_slot(host->current_slot, 1);
  497. mmc_request_done(mmc, cmd->mrq);
  498. }
  499. }
  500. /*
  501. * Abort stuck command. Can occur when card is removed while it is being
  502. * read.
  503. */
  504. static void mmc_omap_abort_command(struct work_struct *work)
  505. {
  506. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  507. cmd_abort_work);
  508. BUG_ON(!host->cmd);
  509. dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
  510. host->cmd->opcode);
  511. if (host->cmd->error == 0)
  512. host->cmd->error = -ETIMEDOUT;
  513. if (host->data == NULL) {
  514. struct mmc_command *cmd;
  515. struct mmc_host *mmc;
  516. cmd = host->cmd;
  517. host->cmd = NULL;
  518. mmc_omap_send_abort(host, 10000);
  519. host->mrq = NULL;
  520. mmc = host->mmc;
  521. mmc_omap_release_slot(host->current_slot, 1);
  522. mmc_request_done(mmc, cmd->mrq);
  523. } else
  524. mmc_omap_cmd_done(host, host->cmd);
  525. host->abort = 0;
  526. enable_irq(host->irq);
  527. }
  528. static void
  529. mmc_omap_cmd_timer(struct timer_list *t)
  530. {
  531. struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
  532. unsigned long flags;
  533. spin_lock_irqsave(&host->slot_lock, flags);
  534. if (host->cmd != NULL && !host->abort) {
  535. OMAP_MMC_WRITE(host, IE, 0);
  536. disable_irq(host->irq);
  537. host->abort = 1;
  538. queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
  539. }
  540. spin_unlock_irqrestore(&host->slot_lock, flags);
  541. }
  542. /* PIO only */
  543. static void
  544. mmc_omap_sg_to_buf(struct mmc_omap_host *host)
  545. {
  546. struct scatterlist *sg;
  547. sg = host->data->sg + host->sg_idx;
  548. host->buffer_bytes_left = sg->length;
  549. host->buffer = sg_virt(sg);
  550. if (host->buffer_bytes_left > host->total_bytes_left)
  551. host->buffer_bytes_left = host->total_bytes_left;
  552. }
  553. static void
  554. mmc_omap_clk_timer(struct timer_list *t)
  555. {
  556. struct mmc_omap_host *host = from_timer(host, t, clk_timer);
  557. mmc_omap_fclk_enable(host, 0);
  558. }
  559. /* PIO only */
  560. static void
  561. mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
  562. {
  563. int n, nwords;
  564. if (host->buffer_bytes_left == 0) {
  565. host->sg_idx++;
  566. BUG_ON(host->sg_idx == host->sg_len);
  567. mmc_omap_sg_to_buf(host);
  568. }
  569. n = 64;
  570. if (n > host->buffer_bytes_left)
  571. n = host->buffer_bytes_left;
  572. /* Round up to handle odd number of bytes to transfer */
  573. nwords = DIV_ROUND_UP(n, 2);
  574. host->buffer_bytes_left -= n;
  575. host->total_bytes_left -= n;
  576. host->data->bytes_xfered += n;
  577. if (write) {
  578. __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
  579. host->buffer, nwords);
  580. } else {
  581. __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
  582. host->buffer, nwords);
  583. }
  584. host->buffer += nwords;
  585. }
  586. #ifdef CONFIG_MMC_DEBUG
  587. static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
  588. {
  589. static const char *mmc_omap_status_bits[] = {
  590. "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
  591. "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
  592. };
  593. int i;
  594. char res[64], *buf = res;
  595. buf += sprintf(buf, "MMC IRQ 0x%x:", status);
  596. for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
  597. if (status & (1 << i))
  598. buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
  599. dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
  600. }
  601. #else
  602. static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
  603. {
  604. }
  605. #endif
  606. static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
  607. {
  608. struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
  609. u16 status;
  610. int end_command;
  611. int end_transfer;
  612. int transfer_error, cmd_error;
  613. if (host->cmd == NULL && host->data == NULL) {
  614. status = OMAP_MMC_READ(host, STAT);
  615. dev_info(mmc_dev(host->slots[0]->mmc),
  616. "Spurious IRQ 0x%04x\n", status);
  617. if (status != 0) {
  618. OMAP_MMC_WRITE(host, STAT, status);
  619. OMAP_MMC_WRITE(host, IE, 0);
  620. }
  621. return IRQ_HANDLED;
  622. }
  623. end_command = 0;
  624. end_transfer = 0;
  625. transfer_error = 0;
  626. cmd_error = 0;
  627. while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
  628. int cmd;
  629. OMAP_MMC_WRITE(host, STAT, status);
  630. if (host->cmd != NULL)
  631. cmd = host->cmd->opcode;
  632. else
  633. cmd = -1;
  634. dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
  635. status, cmd);
  636. mmc_omap_report_irq(host, status);
  637. if (host->total_bytes_left) {
  638. if ((status & OMAP_MMC_STAT_A_FULL) ||
  639. (status & OMAP_MMC_STAT_END_OF_DATA))
  640. mmc_omap_xfer_data(host, 0);
  641. if (status & OMAP_MMC_STAT_A_EMPTY)
  642. mmc_omap_xfer_data(host, 1);
  643. }
  644. if (status & OMAP_MMC_STAT_END_OF_DATA)
  645. end_transfer = 1;
  646. if (status & OMAP_MMC_STAT_DATA_TOUT) {
  647. dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
  648. cmd);
  649. if (host->data) {
  650. host->data->error = -ETIMEDOUT;
  651. transfer_error = 1;
  652. }
  653. }
  654. if (status & OMAP_MMC_STAT_DATA_CRC) {
  655. if (host->data) {
  656. host->data->error = -EILSEQ;
  657. dev_dbg(mmc_dev(host->mmc),
  658. "data CRC error, bytes left %d\n",
  659. host->total_bytes_left);
  660. transfer_error = 1;
  661. } else {
  662. dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
  663. }
  664. }
  665. if (status & OMAP_MMC_STAT_CMD_TOUT) {
  666. /* Timeouts are routine with some commands */
  667. if (host->cmd) {
  668. struct mmc_omap_slot *slot =
  669. host->current_slot;
  670. if (slot == NULL ||
  671. !mmc_omap_cover_is_open(slot))
  672. dev_err(mmc_dev(host->mmc),
  673. "command timeout (CMD%d)\n",
  674. cmd);
  675. host->cmd->error = -ETIMEDOUT;
  676. end_command = 1;
  677. cmd_error = 1;
  678. }
  679. }
  680. if (status & OMAP_MMC_STAT_CMD_CRC) {
  681. if (host->cmd) {
  682. dev_err(mmc_dev(host->mmc),
  683. "command CRC error (CMD%d, arg 0x%08x)\n",
  684. cmd, host->cmd->arg);
  685. host->cmd->error = -EILSEQ;
  686. end_command = 1;
  687. cmd_error = 1;
  688. } else
  689. dev_err(mmc_dev(host->mmc),
  690. "command CRC error without cmd?\n");
  691. }
  692. if (status & OMAP_MMC_STAT_CARD_ERR) {
  693. dev_dbg(mmc_dev(host->mmc),
  694. "ignoring card status error (CMD%d)\n",
  695. cmd);
  696. end_command = 1;
  697. }
  698. /*
  699. * NOTE: On 1610 the END_OF_CMD may come too early when
  700. * starting a write
  701. */
  702. if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
  703. (!(status & OMAP_MMC_STAT_A_EMPTY))) {
  704. end_command = 1;
  705. }
  706. }
  707. if (cmd_error && host->data) {
  708. del_timer(&host->cmd_abort_timer);
  709. host->abort = 1;
  710. OMAP_MMC_WRITE(host, IE, 0);
  711. disable_irq_nosync(host->irq);
  712. queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
  713. return IRQ_HANDLED;
  714. }
  715. if (end_command && host->cmd)
  716. mmc_omap_cmd_done(host, host->cmd);
  717. if (host->data != NULL) {
  718. if (transfer_error)
  719. mmc_omap_xfer_done(host, host->data);
  720. else if (end_transfer)
  721. mmc_omap_end_of_data(host, host->data);
  722. }
  723. return IRQ_HANDLED;
  724. }
  725. void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
  726. {
  727. int cover_open;
  728. struct mmc_omap_host *host = dev_get_drvdata(dev);
  729. struct mmc_omap_slot *slot = host->slots[num];
  730. BUG_ON(num >= host->nr_slots);
  731. /* Other subsystems can call in here before we're initialised. */
  732. if (host->nr_slots == 0 || !host->slots[num])
  733. return;
  734. cover_open = mmc_omap_cover_is_open(slot);
  735. if (cover_open != slot->cover_open) {
  736. slot->cover_open = cover_open;
  737. sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
  738. }
  739. tasklet_hi_schedule(&slot->cover_tasklet);
  740. }
  741. static void mmc_omap_cover_timer(struct timer_list *t)
  742. {
  743. struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
  744. tasklet_schedule(&slot->cover_tasklet);
  745. }
  746. static void mmc_omap_cover_handler(unsigned long param)
  747. {
  748. struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
  749. int cover_open = mmc_omap_cover_is_open(slot);
  750. mmc_detect_change(slot->mmc, 0);
  751. if (!cover_open)
  752. return;
  753. /*
  754. * If no card is inserted, we postpone polling until
  755. * the cover has been closed.
  756. */
  757. if (slot->mmc->card == NULL)
  758. return;
  759. mod_timer(&slot->cover_timer,
  760. jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
  761. }
  762. static void mmc_omap_dma_callback(void *priv)
  763. {
  764. struct mmc_omap_host *host = priv;
  765. struct mmc_data *data = host->data;
  766. /* If we got to the end of DMA, assume everything went well */
  767. data->bytes_xfered += data->blocks * data->blksz;
  768. mmc_omap_dma_done(host, data);
  769. }
  770. static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
  771. {
  772. u16 reg;
  773. reg = OMAP_MMC_READ(host, SDIO);
  774. reg &= ~(1 << 5);
  775. OMAP_MMC_WRITE(host, SDIO, reg);
  776. /* Set maximum timeout */
  777. OMAP_MMC_WRITE(host, CTO, 0xfd);
  778. }
  779. static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
  780. {
  781. unsigned int timeout, cycle_ns;
  782. u16 reg;
  783. cycle_ns = 1000000000 / host->current_slot->fclk_freq;
  784. timeout = req->data->timeout_ns / cycle_ns;
  785. timeout += req->data->timeout_clks;
  786. /* Check if we need to use timeout multiplier register */
  787. reg = OMAP_MMC_READ(host, SDIO);
  788. if (timeout > 0xffff) {
  789. reg |= (1 << 5);
  790. timeout /= 1024;
  791. } else
  792. reg &= ~(1 << 5);
  793. OMAP_MMC_WRITE(host, SDIO, reg);
  794. OMAP_MMC_WRITE(host, DTO, timeout);
  795. }
  796. static void
  797. mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
  798. {
  799. struct mmc_data *data = req->data;
  800. int i, use_dma = 1, block_size;
  801. struct scatterlist *sg;
  802. unsigned sg_len;
  803. host->data = data;
  804. if (data == NULL) {
  805. OMAP_MMC_WRITE(host, BLEN, 0);
  806. OMAP_MMC_WRITE(host, NBLK, 0);
  807. OMAP_MMC_WRITE(host, BUF, 0);
  808. host->dma_in_use = 0;
  809. set_cmd_timeout(host, req);
  810. return;
  811. }
  812. block_size = data->blksz;
  813. OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
  814. OMAP_MMC_WRITE(host, BLEN, block_size - 1);
  815. set_data_timeout(host, req);
  816. /* cope with calling layer confusion; it issues "single
  817. * block" writes using multi-block scatterlists.
  818. */
  819. sg_len = (data->blocks == 1) ? 1 : data->sg_len;
  820. /* Only do DMA for entire blocks */
  821. for_each_sg(data->sg, sg, sg_len, i) {
  822. if ((sg->length % block_size) != 0) {
  823. use_dma = 0;
  824. break;
  825. }
  826. }
  827. host->sg_idx = 0;
  828. if (use_dma) {
  829. enum dma_data_direction dma_data_dir;
  830. struct dma_async_tx_descriptor *tx;
  831. struct dma_chan *c;
  832. u32 burst, *bp;
  833. u16 buf;
  834. /*
  835. * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
  836. * and 24xx. Use 16 or 32 word frames when the
  837. * blocksize is at least that large. Blocksize is
  838. * usually 512 bytes; but not for some SD reads.
  839. */
  840. burst = mmc_omap15xx() ? 32 : 64;
  841. if (burst > data->blksz)
  842. burst = data->blksz;
  843. burst >>= 1;
  844. if (data->flags & MMC_DATA_WRITE) {
  845. c = host->dma_tx;
  846. bp = &host->dma_tx_burst;
  847. buf = 0x0f80 | (burst - 1) << 0;
  848. dma_data_dir = DMA_TO_DEVICE;
  849. } else {
  850. c = host->dma_rx;
  851. bp = &host->dma_rx_burst;
  852. buf = 0x800f | (burst - 1) << 8;
  853. dma_data_dir = DMA_FROM_DEVICE;
  854. }
  855. if (!c)
  856. goto use_pio;
  857. /* Only reconfigure if we have a different burst size */
  858. if (*bp != burst) {
  859. struct dma_slave_config cfg = {
  860. .src_addr = host->phys_base +
  861. OMAP_MMC_REG(host, DATA),
  862. .dst_addr = host->phys_base +
  863. OMAP_MMC_REG(host, DATA),
  864. .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
  865. .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
  866. .src_maxburst = burst,
  867. .dst_maxburst = burst,
  868. };
  869. if (dmaengine_slave_config(c, &cfg))
  870. goto use_pio;
  871. *bp = burst;
  872. }
  873. host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
  874. dma_data_dir);
  875. if (host->sg_len == 0)
  876. goto use_pio;
  877. tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
  878. data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  879. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  880. if (!tx)
  881. goto use_pio;
  882. OMAP_MMC_WRITE(host, BUF, buf);
  883. tx->callback = mmc_omap_dma_callback;
  884. tx->callback_param = host;
  885. dmaengine_submit(tx);
  886. host->brs_received = 0;
  887. host->dma_done = 0;
  888. host->dma_in_use = 1;
  889. return;
  890. }
  891. use_pio:
  892. /* Revert to PIO? */
  893. OMAP_MMC_WRITE(host, BUF, 0x1f1f);
  894. host->total_bytes_left = data->blocks * block_size;
  895. host->sg_len = sg_len;
  896. mmc_omap_sg_to_buf(host);
  897. host->dma_in_use = 0;
  898. }
  899. static void mmc_omap_start_request(struct mmc_omap_host *host,
  900. struct mmc_request *req)
  901. {
  902. BUG_ON(host->mrq != NULL);
  903. host->mrq = req;
  904. /* only touch fifo AFTER the controller readies it */
  905. mmc_omap_prepare_data(host, req);
  906. mmc_omap_start_command(host, req->cmd);
  907. if (host->dma_in_use) {
  908. struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
  909. host->dma_tx : host->dma_rx;
  910. dma_async_issue_pending(c);
  911. }
  912. }
  913. static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
  914. {
  915. struct mmc_omap_slot *slot = mmc_priv(mmc);
  916. struct mmc_omap_host *host = slot->host;
  917. unsigned long flags;
  918. spin_lock_irqsave(&host->slot_lock, flags);
  919. if (host->mmc != NULL) {
  920. BUG_ON(slot->mrq != NULL);
  921. slot->mrq = req;
  922. spin_unlock_irqrestore(&host->slot_lock, flags);
  923. return;
  924. } else
  925. host->mmc = mmc;
  926. spin_unlock_irqrestore(&host->slot_lock, flags);
  927. mmc_omap_select_slot(slot, 1);
  928. mmc_omap_start_request(host, req);
  929. }
  930. static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
  931. int vdd)
  932. {
  933. struct mmc_omap_host *host;
  934. host = slot->host;
  935. if (slot->pdata->set_power != NULL)
  936. slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
  937. vdd);
  938. if (mmc_omap2()) {
  939. u16 w;
  940. if (power_on) {
  941. w = OMAP_MMC_READ(host, CON);
  942. OMAP_MMC_WRITE(host, CON, w | (1 << 11));
  943. } else {
  944. w = OMAP_MMC_READ(host, CON);
  945. OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
  946. }
  947. }
  948. }
  949. static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
  950. {
  951. struct mmc_omap_slot *slot = mmc_priv(mmc);
  952. struct mmc_omap_host *host = slot->host;
  953. int func_clk_rate = clk_get_rate(host->fclk);
  954. int dsor;
  955. if (ios->clock == 0)
  956. return 0;
  957. dsor = func_clk_rate / ios->clock;
  958. if (dsor < 1)
  959. dsor = 1;
  960. if (func_clk_rate / dsor > ios->clock)
  961. dsor++;
  962. if (dsor > 250)
  963. dsor = 250;
  964. slot->fclk_freq = func_clk_rate / dsor;
  965. if (ios->bus_width == MMC_BUS_WIDTH_4)
  966. dsor |= 1 << 15;
  967. return dsor;
  968. }
  969. static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  970. {
  971. struct mmc_omap_slot *slot = mmc_priv(mmc);
  972. struct mmc_omap_host *host = slot->host;
  973. int i, dsor;
  974. int clk_enabled, init_stream;
  975. mmc_omap_select_slot(slot, 0);
  976. dsor = mmc_omap_calc_divisor(mmc, ios);
  977. if (ios->vdd != slot->vdd)
  978. slot->vdd = ios->vdd;
  979. clk_enabled = 0;
  980. init_stream = 0;
  981. switch (ios->power_mode) {
  982. case MMC_POWER_OFF:
  983. mmc_omap_set_power(slot, 0, ios->vdd);
  984. break;
  985. case MMC_POWER_UP:
  986. /* Cannot touch dsor yet, just power up MMC */
  987. mmc_omap_set_power(slot, 1, ios->vdd);
  988. slot->power_mode = ios->power_mode;
  989. goto exit;
  990. case MMC_POWER_ON:
  991. mmc_omap_fclk_enable(host, 1);
  992. clk_enabled = 1;
  993. dsor |= 1 << 11;
  994. if (slot->power_mode != MMC_POWER_ON)
  995. init_stream = 1;
  996. break;
  997. }
  998. slot->power_mode = ios->power_mode;
  999. if (slot->bus_mode != ios->bus_mode) {
  1000. if (slot->pdata->set_bus_mode != NULL)
  1001. slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
  1002. ios->bus_mode);
  1003. slot->bus_mode = ios->bus_mode;
  1004. }
  1005. /* On insanely high arm_per frequencies something sometimes
  1006. * goes somehow out of sync, and the POW bit is not being set,
  1007. * which results in the while loop below getting stuck.
  1008. * Writing to the CON register twice seems to do the trick. */
  1009. for (i = 0; i < 2; i++)
  1010. OMAP_MMC_WRITE(host, CON, dsor);
  1011. slot->saved_con = dsor;
  1012. if (init_stream) {
  1013. /* worst case at 400kHz, 80 cycles makes 200 microsecs */
  1014. int usecs = 250;
  1015. /* Send clock cycles, poll completion */
  1016. OMAP_MMC_WRITE(host, IE, 0);
  1017. OMAP_MMC_WRITE(host, STAT, 0xffff);
  1018. OMAP_MMC_WRITE(host, CMD, 1 << 7);
  1019. while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
  1020. udelay(1);
  1021. usecs--;
  1022. }
  1023. OMAP_MMC_WRITE(host, STAT, 1);
  1024. }
  1025. exit:
  1026. mmc_omap_release_slot(slot, clk_enabled);
  1027. }
  1028. static const struct mmc_host_ops mmc_omap_ops = {
  1029. .request = mmc_omap_request,
  1030. .set_ios = mmc_omap_set_ios,
  1031. };
  1032. static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
  1033. {
  1034. struct mmc_omap_slot *slot = NULL;
  1035. struct mmc_host *mmc;
  1036. int r;
  1037. mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
  1038. if (mmc == NULL)
  1039. return -ENOMEM;
  1040. slot = mmc_priv(mmc);
  1041. slot->host = host;
  1042. slot->mmc = mmc;
  1043. slot->id = id;
  1044. slot->power_mode = MMC_POWER_UNDEFINED;
  1045. slot->pdata = &host->pdata->slots[id];
  1046. host->slots[id] = slot;
  1047. mmc->caps = 0;
  1048. if (host->pdata->slots[id].wires >= 4)
  1049. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1050. mmc->ops = &mmc_omap_ops;
  1051. mmc->f_min = 400000;
  1052. if (mmc_omap2())
  1053. mmc->f_max = 48000000;
  1054. else
  1055. mmc->f_max = 24000000;
  1056. if (host->pdata->max_freq)
  1057. mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
  1058. mmc->ocr_avail = slot->pdata->ocr_mask;
  1059. /* Use scatterlist DMA to reduce per-transfer costs.
  1060. * NOTE max_seg_size assumption that small blocks aren't
  1061. * normally used (except e.g. for reading SD registers).
  1062. */
  1063. mmc->max_segs = 32;
  1064. mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
  1065. mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
  1066. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1067. mmc->max_seg_size = mmc->max_req_size;
  1068. if (slot->pdata->get_cover_state != NULL) {
  1069. timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
  1070. tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
  1071. (unsigned long)slot);
  1072. }
  1073. r = mmc_add_host(mmc);
  1074. if (r < 0)
  1075. goto err_remove_host;
  1076. if (slot->pdata->name != NULL) {
  1077. r = device_create_file(&mmc->class_dev,
  1078. &dev_attr_slot_name);
  1079. if (r < 0)
  1080. goto err_remove_host;
  1081. }
  1082. if (slot->pdata->get_cover_state != NULL) {
  1083. r = device_create_file(&mmc->class_dev,
  1084. &dev_attr_cover_switch);
  1085. if (r < 0)
  1086. goto err_remove_slot_name;
  1087. tasklet_schedule(&slot->cover_tasklet);
  1088. }
  1089. return 0;
  1090. err_remove_slot_name:
  1091. if (slot->pdata->name != NULL)
  1092. device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
  1093. err_remove_host:
  1094. mmc_remove_host(mmc);
  1095. mmc_free_host(mmc);
  1096. return r;
  1097. }
  1098. static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
  1099. {
  1100. struct mmc_host *mmc = slot->mmc;
  1101. if (slot->pdata->name != NULL)
  1102. device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
  1103. if (slot->pdata->get_cover_state != NULL)
  1104. device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
  1105. tasklet_kill(&slot->cover_tasklet);
  1106. del_timer_sync(&slot->cover_timer);
  1107. flush_workqueue(slot->host->mmc_omap_wq);
  1108. mmc_remove_host(mmc);
  1109. mmc_free_host(mmc);
  1110. }
  1111. static int mmc_omap_probe(struct platform_device *pdev)
  1112. {
  1113. struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
  1114. struct mmc_omap_host *host = NULL;
  1115. struct resource *res;
  1116. int i, ret = 0;
  1117. int irq;
  1118. if (pdata == NULL) {
  1119. dev_err(&pdev->dev, "platform data missing\n");
  1120. return -ENXIO;
  1121. }
  1122. if (pdata->nr_slots == 0) {
  1123. dev_err(&pdev->dev, "no slots\n");
  1124. return -EPROBE_DEFER;
  1125. }
  1126. host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
  1127. GFP_KERNEL);
  1128. if (host == NULL)
  1129. return -ENOMEM;
  1130. irq = platform_get_irq(pdev, 0);
  1131. if (irq < 0)
  1132. return -ENXIO;
  1133. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1134. host->virt_base = devm_ioremap_resource(&pdev->dev, res);
  1135. if (IS_ERR(host->virt_base))
  1136. return PTR_ERR(host->virt_base);
  1137. INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
  1138. INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
  1139. INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
  1140. timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
  1141. spin_lock_init(&host->clk_lock);
  1142. timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
  1143. spin_lock_init(&host->dma_lock);
  1144. spin_lock_init(&host->slot_lock);
  1145. init_waitqueue_head(&host->slot_wq);
  1146. host->pdata = pdata;
  1147. host->features = host->pdata->slots[0].features;
  1148. host->dev = &pdev->dev;
  1149. platform_set_drvdata(pdev, host);
  1150. host->id = pdev->id;
  1151. host->irq = irq;
  1152. host->phys_base = res->start;
  1153. host->iclk = clk_get(&pdev->dev, "ick");
  1154. if (IS_ERR(host->iclk))
  1155. return PTR_ERR(host->iclk);
  1156. clk_enable(host->iclk);
  1157. host->fclk = clk_get(&pdev->dev, "fck");
  1158. if (IS_ERR(host->fclk)) {
  1159. ret = PTR_ERR(host->fclk);
  1160. goto err_free_iclk;
  1161. }
  1162. host->dma_tx_burst = -1;
  1163. host->dma_rx_burst = -1;
  1164. host->dma_tx = dma_request_chan(&pdev->dev, "tx");
  1165. if (IS_ERR(host->dma_tx)) {
  1166. ret = PTR_ERR(host->dma_tx);
  1167. if (ret == -EPROBE_DEFER) {
  1168. clk_put(host->fclk);
  1169. goto err_free_iclk;
  1170. }
  1171. host->dma_tx = NULL;
  1172. dev_warn(host->dev, "TX DMA channel request failed\n");
  1173. }
  1174. host->dma_rx = dma_request_chan(&pdev->dev, "rx");
  1175. if (IS_ERR(host->dma_rx)) {
  1176. ret = PTR_ERR(host->dma_rx);
  1177. if (ret == -EPROBE_DEFER) {
  1178. if (host->dma_tx)
  1179. dma_release_channel(host->dma_tx);
  1180. clk_put(host->fclk);
  1181. goto err_free_iclk;
  1182. }
  1183. host->dma_rx = NULL;
  1184. dev_warn(host->dev, "RX DMA channel request failed\n");
  1185. }
  1186. ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
  1187. if (ret)
  1188. goto err_free_dma;
  1189. if (pdata->init != NULL) {
  1190. ret = pdata->init(&pdev->dev);
  1191. if (ret < 0)
  1192. goto err_free_irq;
  1193. }
  1194. host->nr_slots = pdata->nr_slots;
  1195. host->reg_shift = (mmc_omap7xx() ? 1 : 2);
  1196. host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
  1197. if (!host->mmc_omap_wq) {
  1198. ret = -ENOMEM;
  1199. goto err_plat_cleanup;
  1200. }
  1201. for (i = 0; i < pdata->nr_slots; i++) {
  1202. ret = mmc_omap_new_slot(host, i);
  1203. if (ret < 0) {
  1204. while (--i >= 0)
  1205. mmc_omap_remove_slot(host->slots[i]);
  1206. goto err_destroy_wq;
  1207. }
  1208. }
  1209. return 0;
  1210. err_destroy_wq:
  1211. destroy_workqueue(host->mmc_omap_wq);
  1212. err_plat_cleanup:
  1213. if (pdata->cleanup)
  1214. pdata->cleanup(&pdev->dev);
  1215. err_free_irq:
  1216. free_irq(host->irq, host);
  1217. err_free_dma:
  1218. if (host->dma_tx)
  1219. dma_release_channel(host->dma_tx);
  1220. if (host->dma_rx)
  1221. dma_release_channel(host->dma_rx);
  1222. clk_put(host->fclk);
  1223. err_free_iclk:
  1224. clk_disable(host->iclk);
  1225. clk_put(host->iclk);
  1226. return ret;
  1227. }
  1228. static int mmc_omap_remove(struct platform_device *pdev)
  1229. {
  1230. struct mmc_omap_host *host = platform_get_drvdata(pdev);
  1231. int i;
  1232. BUG_ON(host == NULL);
  1233. for (i = 0; i < host->nr_slots; i++)
  1234. mmc_omap_remove_slot(host->slots[i]);
  1235. if (host->pdata->cleanup)
  1236. host->pdata->cleanup(&pdev->dev);
  1237. mmc_omap_fclk_enable(host, 0);
  1238. free_irq(host->irq, host);
  1239. clk_put(host->fclk);
  1240. clk_disable(host->iclk);
  1241. clk_put(host->iclk);
  1242. if (host->dma_tx)
  1243. dma_release_channel(host->dma_tx);
  1244. if (host->dma_rx)
  1245. dma_release_channel(host->dma_rx);
  1246. destroy_workqueue(host->mmc_omap_wq);
  1247. return 0;
  1248. }
  1249. #if IS_BUILTIN(CONFIG_OF)
  1250. static const struct of_device_id mmc_omap_match[] = {
  1251. { .compatible = "ti,omap2420-mmc", },
  1252. { },
  1253. };
  1254. MODULE_DEVICE_TABLE(of, mmc_omap_match);
  1255. #endif
  1256. static struct platform_driver mmc_omap_driver = {
  1257. .probe = mmc_omap_probe,
  1258. .remove = mmc_omap_remove,
  1259. .driver = {
  1260. .name = DRIVER_NAME,
  1261. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  1262. .of_match_table = of_match_ptr(mmc_omap_match),
  1263. },
  1264. };
  1265. module_platform_driver(mmc_omap_driver);
  1266. MODULE_DESCRIPTION("OMAP Multimedia Card driver");
  1267. MODULE_LICENSE("GPL");
  1268. MODULE_ALIAS("platform:" DRIVER_NAME);
  1269. MODULE_AUTHOR("Juha Yrjölä");